| Loop Id: 38 | Module: attention-native | Source: attention.cpp:52-53 | Coverage: 0.13% |
|---|
| Loop Id: 38 | Module: attention-native | Source: attention.cpp:52-53 | Coverage: 0.13% |
|---|
0x12fa0 LDP Q0, Q1, [X23, #2016] [1] |
0x12fa4 FSUB V16.4S, V1.4S, V21.4S |
0x12fa8 FSUB V0.4S, V0.4S, V21.4S |
0x12fac LDP Q2, Q3, [X23], #64 [1] |
0x12fb0 FSUB V17.4S, V2.4S, V21.4S |
0x12fb4 FSUB V18.4S, V3.4S, V21.4S |
0x12fb8 BL 10040 |
0x12fbc ORR V19.16B, V0.16B, V0.16B |
0x12fc0 ORR V0.16B, V16.16B, V16.16B |
0x12fc4 BL 10040 |
0x12fc8 ORR V16.16B, V0.16B, V0.16B |
0x12fcc ORR V0.16B, V17.16B, V17.16B |
0x12fd0 BL 10040 |
0x12fd4 ORR V17.16B, V0.16B, V0.16B |
0x12fd8 ORR V0.16B, V18.16B, V18.16B |
0x12fdc BL 10040 |
0x12fe0 FADD V20.4S, V19.4S, V20.4S |
0x12fe4 FADD V22.4S, V16.4S, V22.4S |
0x12fe8 FADD V23.4S, V17.4S, V23.4S |
0x12fec FADD V8.4S, V0.4S, V8.4S |
0x12ff0 SUBS X24, X24, #16 |
0x12ff4 B.NE 12fa0 |
/home/eoseret/llm-attention/attention.cpp: 52 - 53 |
-------------------------------------------------------------------------------- |
52: for (int idx = 0; idx <= row; ++idx) // vectorised |
53: sum += expf(S_row[idx] - max_val); |
| Coverage (%) | Name | Source Location | Module |
|---|---|---|---|
| ►100.00+ | __libc_start_call_main | libc.so.6 | |
| ○ | __libc_start_main | libc.so.6 | |
| ○ | _start | attention-native |
| min | med | avg | max |
|---|---|---|---|
| Percentile Index | 10 | 20 | 30 | 40 | 50 | 60 | 70 | 80 | 90 | 100 |
|---|---|---|---|---|---|---|---|---|---|---|
| Value |
| min | med | avg | max |
|---|---|---|---|
| Percentile Index | 10 | 20 | 30 | 40 | 50 | 60 | 70 | 80 | 90 | 100 |
|---|---|---|---|---|---|---|---|---|---|---|
| Value |
| Path / |
| Metric | Value |
|---|---|
| CQA speedup if no scalar integer | 1.00 |
| CQA speedup if FP arith vectorized | 1.00 |
| CQA speedup if fully vectorized | 1.00 |
| CQA speedup if no inter-iteration dependency | NA |
| CQA speedup if next bottleneck killed | 1.27 |
| Bottlenecks | P8, P9, P10, P11, |
| Function | main |
| Source | attention.cpp:52-53 |
| Source loop unroll info | unrolled by 16 |
| Source loop unroll confidence level | max |
| Unroll/vectorization loop type | NA |
| Unroll factor | 16 |
| CQA cycles | 3.50 |
| CQA cycles if no scalar integer | 3.50 |
| CQA cycles if FP arith vectorized | 3.50 |
| CQA cycles if fully vectorized | 3.50 |
| Front-end cycles | 2.75 |
| P0 cycles | 2.50 |
| P1 cycles | 2.50 |
| P2 cycles | 2.00 |
| P3 cycles | 2.00 |
| P4 cycles | 0.50 |
| P5 cycles | 0.50 |
| P6 cycles | 0.50 |
| P7 cycles | 0.50 |
| P8 cycles | 3.50 |
| P9 cycles | 3.50 |
| P10 cycles | 3.50 |
| P11 cycles | 3.50 |
| P12 cycles | 0.67 |
| P13 cycles | 0.67 |
| P14 cycles | 0.67 |
| P15 cycles | 0.00 |
| P16 cycles | 0.00 |
| DIV/SQRT cycles | 0.00 |
| Inter-iter dependencies cycles | 2 |
| FE+BE cycles (UFS) | NA |
| Stall cycles (UFS) | NA |
| Nb insns | 22.00 |
| Nb uops | 22.00 |
| Nb loads | NA |
| Nb stores | 0.00 |
| Nb stack references | 0.00 |
| FLOP/cycle | 9.14 |
| Nb FLOP add-sub | 32.00 |
| Nb FLOP mul | 0.00 |
| Nb FLOP fma | 0.00 |
| Nb FLOP div | 0.00 |
| Nb FLOP rcp | 0.00 |
| Nb FLOP sqrt | 0.00 |
| Nb FLOP rsqrt | 0.00 |
| Bytes/cycle | 0.00 |
| Bytes prefetched | 0.00 |
| Bytes loaded | 0.00 |
| Bytes stored | 0.00 |
| Stride 0 | 1.00 |
| Stride 1 | 0.00 |
| Stride n | 0.00 |
| Stride unknown | 0.00 |
| Stride indirect | 0.00 |
| Vectorization ratio all | 100.00 |
| Vectorization ratio load | 100.00 |
| Vectorization ratio store | NA |
| Vectorization ratio mul | NA |
| Vectorization ratio add_sub | 100.00 |
| Vectorization ratio fma | NA |
| Vectorization ratio div_sqrt | NA |
| Vectorization ratio other | 100.00 |
| Vector-efficiency ratio all | 100.00 |
| Vector-efficiency ratio load | 100.00 |
| Vector-efficiency ratio store | NA |
| Vector-efficiency ratio mul | NA |
| Vector-efficiency ratio add_sub | 100.00 |
| Vector-efficiency ratio fma | NA |
| Vector-efficiency ratio div_sqrt | NA |
| Vector-efficiency ratio other | 100.00 |
| Metric | Value |
|---|---|
| CQA speedup if no scalar integer | 1.00 |
| CQA speedup if FP arith vectorized | 1.00 |
| CQA speedup if fully vectorized | 1.00 |
| CQA speedup if no inter-iteration dependency | NA |
| CQA speedup if next bottleneck killed | 1.27 |
| Bottlenecks | P8, P9, P10, P11, |
| Function | main |
| Source | attention.cpp:52-53 |
| Source loop unroll info | unrolled by 16 |
| Source loop unroll confidence level | max |
| Unroll/vectorization loop type | NA |
| Unroll factor | 16 |
| CQA cycles | 3.50 |
| CQA cycles if no scalar integer | 3.50 |
| CQA cycles if FP arith vectorized | 3.50 |
| CQA cycles if fully vectorized | 3.50 |
| Front-end cycles | 2.75 |
| P0 cycles | 2.50 |
| P1 cycles | 2.50 |
| P2 cycles | 2.00 |
| P3 cycles | 2.00 |
| P4 cycles | 0.50 |
| P5 cycles | 0.50 |
| P6 cycles | 0.50 |
| P7 cycles | 0.50 |
| P8 cycles | 3.50 |
| P9 cycles | 3.50 |
| P10 cycles | 3.50 |
| P11 cycles | 3.50 |
| P12 cycles | 0.67 |
| P13 cycles | 0.67 |
| P14 cycles | 0.67 |
| P15 cycles | 0.00 |
| P16 cycles | 0.00 |
| DIV/SQRT cycles | 0.00 |
| Inter-iter dependencies cycles | 2 |
| FE+BE cycles (UFS) | NA |
| Stall cycles (UFS) | NA |
| Nb insns | 22.00 |
| Nb uops | 22.00 |
| Nb loads | NA |
| Nb stores | 0.00 |
| Nb stack references | 0.00 |
| FLOP/cycle | 9.14 |
| Nb FLOP add-sub | 32.00 |
| Nb FLOP mul | 0.00 |
| Nb FLOP fma | 0.00 |
| Nb FLOP div | 0.00 |
| Nb FLOP rcp | 0.00 |
| Nb FLOP sqrt | 0.00 |
| Nb FLOP rsqrt | 0.00 |
| Bytes/cycle | 0.00 |
| Bytes prefetched | 0.00 |
| Bytes loaded | 0.00 |
| Bytes stored | 0.00 |
| Stride 0 | 1.00 |
| Stride 1 | 0.00 |
| Stride n | 0.00 |
| Stride unknown | 0.00 |
| Stride indirect | 0.00 |
| Vectorization ratio all | 100.00 |
| Vectorization ratio load | 100.00 |
| Vectorization ratio store | NA |
| Vectorization ratio mul | NA |
| Vectorization ratio add_sub | 100.00 |
| Vectorization ratio fma | NA |
| Vectorization ratio div_sqrt | NA |
| Vectorization ratio other | 100.00 |
| Vector-efficiency ratio all | 100.00 |
| Vector-efficiency ratio load | 100.00 |
| Vector-efficiency ratio store | NA |
| Vector-efficiency ratio mul | NA |
| Vector-efficiency ratio add_sub | 100.00 |
| Vector-efficiency ratio fma | NA |
| Vector-efficiency ratio div_sqrt | NA |
| Vector-efficiency ratio other | 100.00 |
| Path / |
| Function | main |
| Source file and lines | attention.cpp:52-53 |
| Module | attention-native |
| nb instructions | 22 |
| nb uops | 22 |
| loop length | 88 |
| used w registers | 0 |
| used x registers | 2 |
| used b registers | 0 |
| used h registers | 0 |
| used s registers | 0 |
| used d registers | 0 |
| used q registers | 4 |
| used v registers | 13 |
| used z registers | 0 |
| nb stack references | 0 |
| micro-operation queue | 2.75 cycles |
| front end | 2.75 cycles |
| P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | P12 | P13 | P14 | P15 | P16 | |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| uops | 2.50 | 2.50 | 2.00 | 2.00 | 0.50 | 0.50 | 0.50 | 0.50 | 3.50 | 3.50 | 3.50 | 3.50 | 0.67 | 0.67 | 0.67 | 0.00 | 0.00 |
| cycles | 2.50 | 2.50 | 2.00 | 2.00 | 0.50 | 0.50 | 0.50 | 0.50 | 3.50 | 3.50 | 3.50 | 3.50 | 0.67 | 0.67 | 0.67 | 0.00 | 0.00 |
| Cycles executing div or sqrt instructions | NA |
| Longest recurrence chain latency (RecMII) | 2.00 |
| Front-end | 2.75 |
| Dispatch | 3.50 |
| Data deps. | 2.00 |
| Overall L1 | 3.50 |
| all | 100% |
| load | 100% |
| store | NA (no store vectorizable/vectorized instructions) |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | NA (no add-sub vectorizable/vectorized instructions) |
| fma | NA (no fma vectorizable/vectorized instructions) |
| other | 100% |
| all | 100% |
| load | NA (no load vectorizable/vectorized instructions) |
| store | NA (no store vectorizable/vectorized instructions) |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | 100% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | NA (no other vectorizable/vectorized instructions) |
| all | 100% |
| load | 100% |
| store | NA (no store vectorizable/vectorized instructions) |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | 100% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | 100% |
| all | 100% |
| load | 100% |
| store | NA (no store vectorizable/vectorized instructions) |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | NA (no add-sub vectorizable/vectorized instructions) |
| fma | NA (no fma vectorizable/vectorized instructions) |
| other | 100% |
| all | 100% |
| load | NA (no load vectorizable/vectorized instructions) |
| store | NA (no store vectorizable/vectorized instructions) |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | 100% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | NA (no other vectorizable/vectorized instructions) |
| all | 100% |
| load | 100% |
| store | NA (no store vectorizable/vectorized instructions) |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | 100% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | 100% |
| Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | P12 | P13 | P14 | P15 | P16 | Latency | Recip. throughput | Vectorization |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| LDP Q0, Q1, [X23, #2016] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 6 | 0.67 | vect (100.0%) |
| FSUB V16.4S, V1.4S, V21.4S | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 2 | 0.25 | vect (100.0%) |
| FSUB V0.4S, V0.4S, V21.4S | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 2 | 0.25 | vect (100.0%) |
| LDP Q2, Q3, [X23], #64 | 1 | 0 | 0 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 6 | 0.33 | vect (100.0%) |
| FSUB V17.4S, V2.4S, V21.4S | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 2 | 0.25 | vect (100.0%) |
| FSUB V18.4S, V3.4S, V21.4S | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 2 | 0.25 | vect (100.0%) |
| BL 10040 <@plt_start@+0x20> | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | N/A |
| ORR V19.16B, V0.16B, V0.16B | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 2 | 0.25 | vect (100.0%) |
| ORR V0.16B, V16.16B, V16.16B | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 2 | 0.25 | vect (100.0%) |
| BL 10040 <@plt_start@+0x20> | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | N/A |
| ORR V16.16B, V0.16B, V0.16B | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 2 | 0.25 | vect (100.0%) |
| ORR V0.16B, V17.16B, V17.16B | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 2 | 0.25 | vect (100.0%) |
| BL 10040 <@plt_start@+0x20> | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | N/A |
| ORR V17.16B, V0.16B, V0.16B | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 2 | 0.25 | vect (100.0%) |
| ORR V0.16B, V18.16B, V18.16B | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 2 | 0.25 | vect (100.0%) |
| BL 10040 <@plt_start@+0x20> | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | N/A |
| FADD V20.4S, V19.4S, V20.4S | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 2 | 0.25 | vect (100.0%) |
| FADD V22.4S, V16.4S, V22.4S | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 2 | 0.25 | vect (100.0%) |
| FADD V23.4S, V17.4S, V23.4S | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 2 | 0.25 | vect (100.0%) |
| FADD V8.4S, V0.4S, V8.4S | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 2 | 0.25 | vect (100.0%) |
| SUBS X24, X24, #16 | 1 | 0 | 0 | 0.25 | 0.25 | 0 | 0 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 | N/A |
| B.NE 12fa0 <main+0x1d80> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | N/A |
| Function | main |
| Source file and lines | attention.cpp:52-53 |
| Module | attention-native |
| nb instructions | 22 |
| nb uops | 22 |
| loop length | 88 |
| used w registers | 0 |
| used x registers | 2 |
| used b registers | 0 |
| used h registers | 0 |
| used s registers | 0 |
| used d registers | 0 |
| used q registers | 4 |
| used v registers | 13 |
| used z registers | 0 |
| nb stack references | 0 |
| micro-operation queue | 2.75 cycles |
| front end | 2.75 cycles |
| P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | P12 | P13 | P14 | P15 | P16 | |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| uops | 2.50 | 2.50 | 2.00 | 2.00 | 0.50 | 0.50 | 0.50 | 0.50 | 3.50 | 3.50 | 3.50 | 3.50 | 0.67 | 0.67 | 0.67 | 0.00 | 0.00 |
| cycles | 2.50 | 2.50 | 2.00 | 2.00 | 0.50 | 0.50 | 0.50 | 0.50 | 3.50 | 3.50 | 3.50 | 3.50 | 0.67 | 0.67 | 0.67 | 0.00 | 0.00 |
| Cycles executing div or sqrt instructions | NA |
| Longest recurrence chain latency (RecMII) | 2.00 |
| Front-end | 2.75 |
| Dispatch | 3.50 |
| Data deps. | 2.00 |
| Overall L1 | 3.50 |
| all | 100% |
| load | 100% |
| store | NA (no store vectorizable/vectorized instructions) |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | NA (no add-sub vectorizable/vectorized instructions) |
| fma | NA (no fma vectorizable/vectorized instructions) |
| other | 100% |
| all | 100% |
| load | NA (no load vectorizable/vectorized instructions) |
| store | NA (no store vectorizable/vectorized instructions) |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | 100% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | NA (no other vectorizable/vectorized instructions) |
| all | 100% |
| load | 100% |
| store | NA (no store vectorizable/vectorized instructions) |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | 100% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | 100% |
| all | 100% |
| load | 100% |
| store | NA (no store vectorizable/vectorized instructions) |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | NA (no add-sub vectorizable/vectorized instructions) |
| fma | NA (no fma vectorizable/vectorized instructions) |
| other | 100% |
| all | 100% |
| load | NA (no load vectorizable/vectorized instructions) |
| store | NA (no store vectorizable/vectorized instructions) |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | 100% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | NA (no other vectorizable/vectorized instructions) |
| all | 100% |
| load | 100% |
| store | NA (no store vectorizable/vectorized instructions) |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | 100% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | 100% |
| Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | P12 | P13 | P14 | P15 | P16 | Latency | Recip. throughput | Vectorization |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| LDP Q0, Q1, [X23, #2016] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 6 | 0.67 | vect (100.0%) |
| FSUB V16.4S, V1.4S, V21.4S | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 2 | 0.25 | vect (100.0%) |
| FSUB V0.4S, V0.4S, V21.4S | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 2 | 0.25 | vect (100.0%) |
| LDP Q2, Q3, [X23], #64 | 1 | 0 | 0 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 6 | 0.33 | vect (100.0%) |
| FSUB V17.4S, V2.4S, V21.4S | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 2 | 0.25 | vect (100.0%) |
| FSUB V18.4S, V3.4S, V21.4S | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 2 | 0.25 | vect (100.0%) |
| BL 10040 <@plt_start@+0x20> | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | N/A |
| ORR V19.16B, V0.16B, V0.16B | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 2 | 0.25 | vect (100.0%) |
| ORR V0.16B, V16.16B, V16.16B | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 2 | 0.25 | vect (100.0%) |
| BL 10040 <@plt_start@+0x20> | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | N/A |
| ORR V16.16B, V0.16B, V0.16B | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 2 | 0.25 | vect (100.0%) |
| ORR V0.16B, V17.16B, V17.16B | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 2 | 0.25 | vect (100.0%) |
| BL 10040 <@plt_start@+0x20> | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | N/A |
| ORR V17.16B, V0.16B, V0.16B | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 2 | 0.25 | vect (100.0%) |
| ORR V0.16B, V18.16B, V18.16B | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 2 | 0.25 | vect (100.0%) |
| BL 10040 <@plt_start@+0x20> | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | N/A |
| FADD V20.4S, V19.4S, V20.4S | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 2 | 0.25 | vect (100.0%) |
| FADD V22.4S, V16.4S, V22.4S | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 2 | 0.25 | vect (100.0%) |
| FADD V23.4S, V17.4S, V23.4S | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 2 | 0.25 | vect (100.0%) |
| FADD V8.4S, V0.4S, V8.4S | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 2 | 0.25 | vect (100.0%) |
| SUBS X24, X24, #16 | 1 | 0 | 0 | 0.25 | 0.25 | 0 | 0 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 | N/A |
| B.NE 12fa0 <main+0x1d80> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | N/A |
