OV - attention-native - Loop 33

	Loop Id: 33	Module: attention-native	Source: attention.cpp:26-315 [...]	Coverage: 0.06%

0x132ec LDR	S1, [X24]

0x132f0 LDR	X14, [SP, #88]

0x132f4 ADD	X8, X8, #1

0x132f8 FADD	S0, S1, S0

0x132fc CMP	X8, X14

0x13300 B.EQ	135a4

0x13304 ORR	W14, WZR, WZR

0x13308 ORR	W15, WZR, WZR

0x1330c B	13334

0x13320 LDR	X17, [SP, #312]

0x13324 ADD	W15, W15, #1

0x13328 ADD	W14, W14, W17

0x1332c CMP	W15, W17

0x13330 B.EQ	132ec

0x13334 MADD	W17, W15, W17, WZR

0x13338 MADD	W18, W15, W25, WZR

0x1333c ORR	X16, XZR, XZR

0x13340 CMN	W17, W6

0x13344 CSINC	W7, W9, WZR, #3

0x13348 B	13368

  (34) 0x1334c FCVT	S1, D1

  (34) 0x13350 ADD	W1, W18, W16

  (34) 0x13354 ADD	X16, X16, #1

  (34) 0x13358 STR	S1, [X24, W1,UXTW #2]

  (34) 0x1335c AND	X1, X25, #0x7fffffff

  (34) 0x13360 CMP	X16, X1

  (34) 0x13364 B.EQ	13320

  (34) 0x13368 LDR	X1, [SP, #336]

  (34) 0x1336c MOVI	D1, #0

  (34) 0x13370 CMP	X1, #4

  (34) 0x13374 B.CC	13384

  (34) 0x13378 CMN	W16, W6

  (34) 0x1337c CSINC	W1, W7, WZR, #3

  (34) 0x13380 TBZ	W1, #0, 13424

  (34) 0x13384 ORR	X1, XZR, XZR

  (34) 0x13388 LDR	X3, [SP, #312]

  (34) 0x1338c ORR	X2, X1, #0x1

  (34) 0x13390 TBZ	W3, #0, 133b4

  (34) 0x13394 ADD	W3, W17, W1

  (34) 0x13398 MADD	W1, W1, W25, W16

  (34) 0x1339c LDR	S2, [X27, W3,UXTW #2]

  (34) 0x133a0 LDR	S3, [X21, W1,UXTW #2]

  (34) 0x133a4 ORR	X1, XZR, X2

  (34) 0x133a8 FCVT	D2, S2

  (34) 0x133ac FCVT	D3, S3

  (34) 0x133b0 FMADD	D1, D2, D3, D1

  (34) 0x133b4 LDR	X3, [SP, #336]

  (34) 0x133b8 CMP	X3, X2

  (34) 0x133bc B.EQ	1334c

  (34) 0x133c0 LDR	X2, [SP, #336]

  (34) 0x133c4 MADD	X4, X25, X1, XZR

  (34) 0x133c8 ADD	X5, X16, X25

  (34) 0x133cc ADD	X3, X16, X4

  (34) 0x133d0 ADD	X4, X5, X4

  (34) 0x133d4 SUB	X2, X2, X1

  (34) 0x133d8 ADD	W1, W14, W1

  (34) 0x133dc HINT	#0

    (35) 0x133e0 LDR	S2, [X27, W1,UXTW #2]

    (35) 0x133e4 LDR	S3, [X21, W3,UXTW #2]

    (35) 0x133e8 ADD	W5, W1, #1

    (35) 0x133ec SUBS	X2, X2, #2

    (35) 0x133f0 ADD	X3, X3, X19

    (35) 0x133f4 ADD	W1, W1, #2

    (35) 0x133f8 FCVT	D2, S2

    (35) 0x133fc FCVT	D3, S3

    (35) 0x13400 FMADD	D1, D2, D3, D1

    (35) 0x13404 LDR	S2, [X27, W5,UXTW #2]

    (35) 0x13408 LDR	S3, [X21, W4,UXTW #2]

    (35) 0x1340c ADD	X4, X4, X19

    (35) 0x13410 FCVT	D2, S2

    (35) 0x13414 FCVT	D3, S3

    (35) 0x13418 FMADD	D1, D2, D3, D1

    (35) 0x1341c B.NE	133e0

  (34) 0x13420 B	1334c

  (34) 0x13424 LDR	X1, [SP, #336]

  (34) 0x13428 CMP	X1, #16

  (34) 0x1342c B.CS	1343c

  (34) 0x13430 ORR	X3, XZR, XZR

  (34) 0x13434 MOVI	D1, #0

  (34) 0x13438 B	13530

  (34) 0x1343c LDR	X3, [SP, #312]

  (34) 0x13440 MOVI	V1.2D, #0

  (34) 0x13444 ORR	W1, WZR, W14

  (34) 0x13448 ORR	X2, XZR, X16

  (34) 0x1344c MOVI	V2.2D, #0

  (34) 0x13450 MOVI	V3.2D, #0

  (34) 0x13454 MOVI	V5.2D, #0

  (34) 0x13458 MOVI	V6.2D, #0

  (34) 0x1345c MOVI	V7.2D, #0

  (34) 0x13460 MOVI	V4.2D, #0

  (34) 0x13464 MOVI	V16.2D, #0

  (34) 0x13468 AND	X3, X3, #0x0

    (36) 0x1346c ADD	X4, X27, W1,UXTW #2

    (36) 0x13470 SUBS	X3, X3, #16

    (36) 0x13474 ADD	W1, W1, #16

    (36) 0x13478 LDP	Q17, Q18, [X4]

    (36) 0x1347c LDP	Q19, Q20, [X4, #32]

    (36) 0x13480 ADD	X4, X21, W2,UXTW #2

    (36) 0x13484 ADD	X2, X2, #16

    (36) 0x13488 FCVTL	V22.2D, V18.2S

    (36) 0x1348c LDP	Q25, Q26, [X4]

    (36) 0x13490 LDP	Q27, Q28, [X4, #32]

    (36) 0x13494 FCVTL2	V18.2D, V18.4S

    (36) 0x13498 FCVTL	V24.2D, V20.2S

    (36) 0x1349c FCVTL2	V20.2D, V20.4S

    (36) 0x134a0 FCVTL	V21.2D, V17.2S

    (36) 0x134a4 FCVTL2	V17.2D, V17.4S

    (36) 0x134a8 FCVTL	V23.2D, V19.2S

    (36) 0x134ac FCVTL2	V19.2D, V19.4S

    (36) 0x134b0 FCVTL	V30.2D, V26.2S

    (36) 0x134b4 FCVTL2	V26.2D, V26.4S

    (36) 0x134b8 FCVTL	V8.2D, V28.2S

    (36) 0x134bc FCVTL2	V28.2D, V28.4S

    (36) 0x134c0 FCVTL	V29.2D, V25.2S

    (36) 0x134c4 FCVTL2	V25.2D, V25.4S

    (36) 0x134c8 FCVTL	V31.2D, V27.2S

    (36) 0x134cc FCVTL2	V27.2D, V27.4S

    (36) 0x134d0 FMLA	V6.2D, V26.2D, V18.2D

    (36) 0x134d4 FMLA	V5.2D, V30.2D, V22.2D

    (36) 0x134d8 FMLA	V1.2D, V28.2D, V20.2D

    (36) 0x134dc FMLA	V16.2D, V8.2D, V24.2D

    (36) 0x134e0 FMLA	V3.2D, V25.2D, V17.2D

    (36) 0x134e4 FMLA	V2.2D, V29.2D, V21.2D

    (36) 0x134e8 FMLA	V4.2D, V27.2D, V19.2D

    (36) 0x134ec FMLA	V7.2D, V31.2D, V23.2D

    (36) 0x134f0 B.NE	1346c

  (34) 0x134f4 FADD	V2.2D, V5.2D, V2.2D

  (34) 0x134f8 FADD	V3.2D, V6.2D, V3.2D

  (34) 0x134fc FADD	V5.2D, V16.2D, V7.2D

  (34) 0x13500 FADD	V1.2D, V1.2D, V4.2D

  (34) 0x13504 LDR	X1, [SP, #336]

  (34) 0x13508 FADD	V2.2D, V5.2D, V2.2D

  (34) 0x1350c FADD	V1.2D, V1.2D, V3.2D

  (34) 0x13510 FADD	V1.2D, V2.2D, V1.2D

  (34) 0x13514 FADDP	D1, V1.2D

  (34) 0x13518 CMP	X1, X11

  (34) 0x1351c B.EQ	1334c

  (34) 0x13520 LDR	X1, [SP, #312]

  (34) 0x13524 AND	X3, X1, #0x0

  (34) 0x13528 AND	X1, X1, #0x0

  (34) 0x1352c CBZ	X10, 13388

  (34) 0x13530 MOVI	V3.2D, #0

  (34) 0x13534 MOV	V3.D[0], V1.D[0]

  (34) 0x13538 ADD	X1, X13, X3

  (34) 0x1353c ADD	X2, X3, X16

  (34) 0x13540 ADD	W3, W14, W3

  (34) 0x13544 MOVI	V2.2D, #0

    (37) 0x13548 UBFM	X4, X3, #62, #31

    (37) 0x1354c ADDS	X1, X1, #4

    (37) 0x13550 ADD	W3, W3, #4

    (37) 0x13554 LDR	Q1, [X27, X4]

    (37) 0x13558 ORR	W4, WZR, W2

    (37) 0x1355c UBFM	X4, X4, #62, #61

    (37) 0x13560 ADD	X2, X2, #4

    (37) 0x13564 LDR	Q5, [X21, X4]

    (37) 0x13568 FCVTL	V4.2D, V1.2S

    (37) 0x1356c FCVTL2	V1.2D, V1.4S

    (37) 0x13570 FCVTL	V6.2D, V5.2S

    (37) 0x13574 FCVTL2	V5.2D, V5.4S

    (37) 0x13578 FMLA	V2.2D, V5.2D, V1.2D

    (37) 0x1357c FMLA	V3.2D, V6.2D, V4.2D

    (37) 0x13580 B.NE	13548

  (34) 0x13584 LDR	X1, [SP, #312]

  (34) 0x13588 FADD	V1.2D, V3.2D, V2.2D

  (34) 0x1358c LDR	X2, [SP, #336]

  (34) 0x13590 FADDP	D1, V1.2D

  (34) 0x13594 AND	X1, X1, #0x0

  (34) 0x13598 CMP	X2, X12

  (34) 0x1359c B.EQ	1334c

  (34) 0x135a0 B	13388

/home/eoseret/llm-attention/attention.cpp: 26 - 315

--------------------------------------------------------------------------------

26:    for (unsigned int i = 0; i < M; ++i) {

27:       for (unsigned int j = 0; j < N; ++j) {  //vectorized

28:          double sum = 0.0;

29: #pragma clang loop vectorize(enable)

30:          for (unsigned int k = 0; k < K; ++k) { //vectorized

31:             sum += (double)A[i * K + k] * (double)B[k * N + j];

32:          }

33:          C[i * N + j] = alpha * static_cast<float>(sum);

[...]

312:    for (size_t r = 0; r < rept; r++) {

313:       MatMul(h_P.data(), h_V.data(), h_O.data(), context_size, context_size, dim);

314:       float *out = h_O.data();

315:       sum_Output += out[0];

Coverage (%)	Name	Module
►100.00+	__libc_start_call_main	libc.so.6
○	__libc_start_main	libc.so.6
○	_start	attention-native

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	2.50
CQA speedup if FP arith vectorized	1.36
CQA speedup if fully vectorized	3.33
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.25
Bottlenecks	micro-operation queue,
Function	main
Source	attention.cpp:26-26,attention.cpp:312-312,attention.cpp:315-315
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	2.50
CQA cycles if no scalar integer	1.00
CQA cycles if FP arith vectorized	1.83
CQA cycles if fully vectorized	0.75
Front-end cycles	2.50
P0 cycles	2.00
P1 cycles	2.00
P2 cycles	2.00
P3 cycles	2.00
P4 cycles	2.00
P5 cycles	2.00
P6 cycles	2.00
P7 cycles	2.00
P8 cycles	0.25
P9 cycles	0.25
P10 cycles	0.25
P11 cycles	0.25
P12 cycles	1.00
P13 cycles	1.00
P14 cycles	1.00
P15 cycles	0.00
P16 cycles	0.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	20.00
Nb uops	20.00
Nb loads	NA
Nb stores	0.00
Nb stack references	2.00
FLOP/cycle	0.40
Nb FLOP add-sub	1.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	1.20
Bytes prefetched	0.00
Bytes loaded	3.00
Bytes stored	0.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	NA
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	0.00
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	32.69
Vector-efficiency ratio load	37.50
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	31.25
Vector-efficiency ratio fma	25.00
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	33.33

Metric	Value
CQA speedup if no scalar integer	2.50
CQA speedup if FP arith vectorized	1.36
CQA speedup if fully vectorized	3.33
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.25
Bottlenecks	micro-operation queue,
Function	main
Source	attention.cpp:26-26,attention.cpp:312-312,attention.cpp:315-315
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	2.50
CQA cycles if no scalar integer	1.00
CQA cycles if FP arith vectorized	1.83
CQA cycles if fully vectorized	0.75
Front-end cycles	2.50
P0 cycles	2.00
P1 cycles	2.00
P2 cycles	2.00
P3 cycles	2.00
P4 cycles	2.00
P5 cycles	2.00
P6 cycles	2.00
P7 cycles	2.00
P8 cycles	0.25
P9 cycles	0.25
P10 cycles	0.25
P11 cycles	0.25
P12 cycles	1.00
P13 cycles	1.00
P14 cycles	1.00
P15 cycles	0.00
P16 cycles	0.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	20.00
Nb uops	20.00
Nb loads	NA
Nb stores	0.00
Nb stack references	2.00
FLOP/cycle	0.40
Nb FLOP add-sub	1.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	1.20
Bytes prefetched	0.00
Bytes loaded	3.00
Bytes stored	0.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	NA
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	0.00
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	32.69
Vector-efficiency ratio load	37.50
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	31.25
Vector-efficiency ratio fma	25.00
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	33.33

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	main
Source file and lines	attention.cpp:26-315
Module	attention-native

The loop is defined in /home/eoseret/llm-attention/attention.cpp:26-33,312-315.

Analyzed code is defined in /home/eoseret/llm-attention/attention.cpp:26,312,315.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Failed to get the number of paths
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 2.50 to 1.00 cycles (2.50x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is not vectorized. Only 32% of vector register length is used (average across all VPU instructions). By vectorizing your loop, you can lower the cost of an iteration from 2.50 to 0.75 cycles (3.33x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ffast-math (included in Ofast) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 1 FP arithmetical operations:

1: addition or subtraction

The binary loop is loading 3 bytes.

Arithmetic intensity

Arithmetic intensity is 0.33 FP operations per loaded or stored byte.

General properties

nb instructions	20
nb uops	20
loop length	80
used w registers	9
used x registers	6
used b registers	0
used h registers	0
used s registers	3
used d registers	0
used q registers	0
used v registers	0
used z registers	0
nb stack references	2

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	2.50 cycles
front end	2.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	2.00	2.00	2.00	2.00	2.00	2.00	2.00	2.00	0.25	0.25	0.25	0.25	1.00	1.00	1.00	0.00	0.00
cycles	2.00	2.00	2.00	2.00	2.00	2.00	2.00	2.00	0.25	0.25	0.25	0.25	1.00	1.00	1.00	0.00	0.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	2.50
Dispatch	2.00
Overall L1	2.50

Vectorization ratios

INT

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
other	0%

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

INT

all	33%
load	37%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	33%
fma	25%
other	33%

all	25%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	25%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	32%
load	37%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	31%
fma	25%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	33%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 2.50 cycles. At this rate:

1% of peak load performance is reached (1.20 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 2.50 to 2.00 cycles (1.25x speedup).

ASM code

In the binary file, the address of the loop is: 13320

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput	Vectorization
LDR S1, [X24]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
LDR X14, [SP, #88]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	scal (50.0%)
ADD X8, X8, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
FADD S0, S1, S0	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (25.0%)
CMP X8, X14	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 135a4 <main+0x2384>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR W14, WZR, WZR	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
ORR W15, WZR, WZR	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
B 13334 <main+0x2114>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X17, [SP, #312]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
ADD W15, W15, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
ADD W14, W14, W17	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
CMP W15, W17	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 132ec <main+0x20cc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MADD W17, W15, W17, WZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	N/A
MADD W18, W15, W25, WZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
ORR X16, XZR, XZR	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
CMN W17, W6	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	1	0.33	N/A
CSINC W7, W9, WZR, #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
B 13368 <main+0x2148>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Function	main
Source file and lines	attention.cpp:26-315
Module	attention-native

The loop is defined in /home/eoseret/llm-attention/attention.cpp:26-33,312-315.

Analyzed code is defined in /home/eoseret/llm-attention/attention.cpp:26,312,315.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Failed to get the number of paths
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 2.50 to 1.00 cycles (2.50x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ffast-math (included in Ofast) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 1 FP arithmetical operations:

1: addition or subtraction

The binary loop is loading 3 bytes.

Arithmetic intensity

Arithmetic intensity is 0.33 FP operations per loaded or stored byte.

General properties

nb instructions	20
nb uops	20
loop length	80
used w registers	9
used x registers	6
used b registers	0
used h registers	0
used s registers	3
used d registers	0
used q registers	0
used v registers	0
used z registers	0
nb stack references	2

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	2.50 cycles
front end	2.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	2.00	2.00	2.00	2.00	2.00	2.00	2.00	2.00	0.25	0.25	0.25	0.25	1.00	1.00	1.00	0.00	0.00
cycles	2.00	2.00	2.00	2.00	2.00	2.00	2.00	2.00	0.25	0.25	0.25	0.25	1.00	1.00	1.00	0.00	0.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	2.50
Dispatch	2.00
Overall L1	2.50

Vectorization ratios

INT

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
other	0%

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

INT

all	33%
load	37%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	33%
fma	25%
other	33%

all	25%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	25%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	32%
load	37%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	31%
fma	25%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	33%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 2.50 cycles. At this rate:

1% of peak load performance is reached (1.20 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the loop is: 13320

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput	Vectorization
LDR S1, [X24]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
LDR X14, [SP, #88]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	scal (50.0%)
ADD X8, X8, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
FADD S0, S1, S0	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (25.0%)
CMP X8, X14	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 135a4 <main+0x2384>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR W14, WZR, WZR	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
ORR W15, WZR, WZR	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
B 13334 <main+0x2114>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X17, [SP, #312]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
ADD W15, W15, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
ADD W14, W14, W17	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
CMP W15, W17	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 132ec <main+0x20cc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MADD W17, W15, W17, WZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	N/A
MADD W18, W15, W25, WZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
ORR X16, XZR, XZR	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
CMN W17, W6	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	1	0.33	N/A
CSINC W7, W9, WZR, #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
B 13368 <main+0x2148>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code