OV - attention-armclang-native - Loop 82 - attention-armclang-native

	Loop Id: 82	Module: attention-armclang-native	Source: random.tcc:412-417	Coverage: 0.24%

0x11b48 ADD	X10, X15, X9

0x11b4c DUP	V6.2D, X27

0x11b50 ADD	X9, X9, #32

0x11b54 LDR	Q3, [X10, #1824]    [2]

0x11b58 ADD	X11, X10, #1816

0x11b5c EXT	V2.16B, V2.16B, V3.16B, #8

0x11b60 AND	V4.16B, V3.16B, V23.16B

0x11b64 AND	V2.16B, V2.16B, V22.16B

0x11b68 ORR	V2.16B, V4.16B, V2.16B

0x11b6c LDP	Q4, Q5, [X10]    [2]

0x11b70 USHR	V2.2D, V2.2D, #1

0x11b74 EOR	V2.16B, V2.16B, V4.16B

0x11b78 AND	V4.16B, V3.16B, V24.16B

0x11b7c CMEQ	V4.2D, V4.2D, #0

0x11b80 BCAX	V2.16B, V2.16B, V6.16B, V4.16B

0x11b84 STR	Q2, [X11]    [3]

0x11b88 LDR	Q2, [X10, #1840]    [2]

0x11b8c ADD	X10, X10, #1832

0x11b90 EXT	V3.16B, V3.16B, V2.16B, #8

0x11b94 AND	V4.16B, V2.16B, V23.16B

0x11b98 AND	V3.16B, V3.16B, V22.16B

0x11b9c ORR	V3.16B, V4.16B, V3.16B

0x11ba0 AND	V4.16B, V2.16B, V24.16B

0x11ba4 USHR	V3.2D, V3.2D, #1

0x11ba8 CMEQ	V4.2D, V4.2D, #0

0x11bac EOR	V3.16B, V3.16B, V5.16B

0x11bb0 BCAX	V3.16B, V3.16B, V6.16B, V4.16B

0x11bb4 STR	Q3, [X10]    [1]

0x11bb8 CMP	X9, #3168

0x11bbc B.NE	11b48

/usr/lib/gcc/aarch64-amazon-linux/14/../../../../include/c++/14/bits/random.tcc: 412 - 417

--------------------------------------------------------------------------------

412:       for (size_t __k = (__n - __m); __k < (__n - 1); ++__k)

413: 	{

414: 	  _UIntType __y = ((_M_x[__k] & __upper_mask)

415: 			   | (_M_x[__k + 1] & __lower_mask));

416: 	  _M_x[__k] = (_M_x[__k + (__m - __n)] ^ (__y >> 1)

417: 		       ^ ((__y & 0x01) ? __a : 0));

Coverage (%)	Name	Module
►100.00+	__libc_start_call_main	libc.so.6
○	__libc_start_main	libc.so.6
○	_start	attention-armclang-native

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.33
Bottlenecks	P8, P9, P10, P11,
Function	main
Source	random.tcc:412-417
Source loop unroll info	multi-versionned
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	5.00
CQA cycles if no scalar integer	5.00
CQA cycles if FP arith vectorized	5.00
CQA cycles if fully vectorized	5.00
Front-end cycles	3.75
P0 cycles	0.50
P1 cycles	0.50
P2 cycles	1.00
P3 cycles	1.08
P4 cycles	1.00
P5 cycles	1.00
P6 cycles	1.00
P7 cycles	0.92
P8 cycles	5.00
P9 cycles	5.00
P10 cycles	5.00
P11 cycles	5.00
P12 cycles	1.67
P13 cycles	1.67
P14 cycles	1.67
P15 cycles	0.00
P16 cycles	0.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	30.00
Nb uops	30.00
Nb loads	NA
Nb stores	2.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	0.00
Bytes prefetched	0.00
Bytes loaded	0.00
Bytes stored	0.00
Stride 0	0.00
Stride 1	0.00
Stride n	1.00
Stride unknown	2.00
Stride indirect	0.00
Vectorization ratio all	95.83
Vectorization ratio load	100.00
Vectorization ratio store	100.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	94.74
Vector-efficiency ratio all	97.92
Vector-efficiency ratio load	100.00
Vector-efficiency ratio store	100.00
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	97.37

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.33
Bottlenecks	P8, P9, P10, P11,
Function	main
Source	random.tcc:412-417
Source loop unroll info	multi-versionned
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	5.00
CQA cycles if no scalar integer	5.00
CQA cycles if FP arith vectorized	5.00
CQA cycles if fully vectorized	5.00
Front-end cycles	3.75
P0 cycles	0.50
P1 cycles	0.50
P2 cycles	1.00
P3 cycles	1.08
P4 cycles	1.00
P5 cycles	1.00
P6 cycles	1.00
P7 cycles	0.92
P8 cycles	5.00
P9 cycles	5.00
P10 cycles	5.00
P11 cycles	5.00
P12 cycles	1.67
P13 cycles	1.67
P14 cycles	1.67
P15 cycles	0.00
P16 cycles	0.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	30.00
Nb uops	30.00
Nb loads	NA
Nb stores	2.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	0.00
Bytes prefetched	0.00
Bytes loaded	0.00
Bytes stored	0.00
Stride 0	0.00
Stride 1	0.00
Stride n	1.00
Stride unknown	2.00
Stride indirect	0.00
Vectorization ratio all	95.83
Vectorization ratio load	100.00
Vectorization ratio store	100.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	94.74
Vector-efficiency ratio all	97.92
Vector-efficiency ratio load	100.00
Vector-efficiency ratio store	100.00
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	97.37

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	main
Source file and lines	random.tcc:412-417
Module	attention-armclang-native

The loop is defined in /usr/lib/gcc/aarch64-amazon-linux/14/../../../../include/c++/14/bits/random.tcc:412-417.

The related source loop is multi-versionned.

gain
potential
hint
expert

Vectorization

Your loop is highly vectorized. 97% of vector register length is used (average across all VPU instructions).

Details

95% of VPU instructions are used in vector version (process two or more data elements in vector registers):

94% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

No data for this section

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant unknown stride: 2 occurrence(s)
Constant non-unit stride: 1 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop does not load or store any data.

General properties

nb instructions	30
nb uops	30
loop length	120
used w registers	0
used x registers	5
used b registers	0
used h registers	0
used s registers	0
used d registers	0
used q registers	4
used v registers	8
used z registers	0
nb stack references	0

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	3.75 cycles
front end	3.75 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	0.50	0.50	1.00	1.08	1.00	1.00	1.00	0.92	5.00	5.00	5.00	5.00	1.67	1.67	1.67	0.00	0.00
cycles	0.50	0.50	1.00	1.08	1.00	1.00	1.00	0.92	5.00	5.00	5.00	5.00	1.67	1.67	1.67	0.00	0.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	3.75
Dispatch	5.00
Data deps.	1.00
Overall L1	5.00

Vectorization ratios

all	95%
load	100%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	94%

Vector efficiency ratios

all	97%
load	100%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	97%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 5.00 cycles.

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 11b48

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput	Vectorization
ADD X10, X15, X9	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
DUP V6.2D, X27	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	3	1	scal (50.0%)
ADD X9, X9, #32	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
LDR Q3, [X10, #1824]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
ADD X11, X10, #1816	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
EXT V2.16B, V2.16B, V3.16B, #8	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
AND V4.16B, V3.16B, V23.16B	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
AND V2.16B, V2.16B, V22.16B	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
ORR V2.16B, V4.16B, V2.16B	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
LDP Q4, Q5, [X10]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.67	vect (100.0%)
USHR V2.2D, V2.2D, #1	1	0	0	0	0	0	0	0	0	0	0.50	0	0.50	0	0	0	2	0.50	vect (100.0%)
EOR V2.16B, V2.16B, V4.16B	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
AND V4.16B, V3.16B, V24.16B	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
CMEQ V4.2D, V4.2D, #0	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
BCAX V2.16B, V2.16B, V6.16B, V4.16B	1	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	vect (100.0%)
STR Q2, [X11]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	vect (100.0%)
LDR Q2, [X10, #1840]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
ADD X10, X10, #1832	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
EXT V3.16B, V3.16B, V2.16B, #8	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
AND V4.16B, V2.16B, V23.16B	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
AND V3.16B, V3.16B, V22.16B	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
ORR V3.16B, V4.16B, V3.16B	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
AND V4.16B, V2.16B, V24.16B	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
USHR V3.2D, V3.2D, #1	1	0	0	0	0	0	0	0	0	0	0.50	0	0.50	0	0	0	2	0.50	vect (100.0%)
CMEQ V4.2D, V4.2D, #0	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
EOR V3.16B, V3.16B, V5.16B	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
BCAX V3.16B, V3.16B, V6.16B, V4.16B	1	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	vect (100.0%)
STR Q3, [X10]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	vect (100.0%)
CMP X9, #3168	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	1	0.33	N/A
B.NE 11b48 <main+0x928>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Function	main
Source file and lines	random.tcc:412-417
Module	attention-armclang-native

The loop is defined in /usr/lib/gcc/aarch64-amazon-linux/14/../../../../include/c++/14/bits/random.tcc:412-417.

The related source loop is multi-versionned.

gain
potential
hint
expert

Vectorization

Your loop is highly vectorized. 97% of vector register length is used (average across all VPU instructions).

Details

95% of VPU instructions are used in vector version (process two or more data elements in vector registers):

94% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

No data for this section

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant unknown stride: 2 occurrence(s)
Constant non-unit stride: 1 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop does not load or store any data.

General properties

nb instructions	30
nb uops	30
loop length	120
used w registers	0
used x registers	5
used b registers	0
used h registers	0
used s registers	0
used d registers	0
used q registers	4
used v registers	8
used z registers	0
nb stack references	0

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	3.75 cycles
front end	3.75 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	0.50	0.50	1.00	1.08	1.00	1.00	1.00	0.92	5.00	5.00	5.00	5.00	1.67	1.67	1.67	0.00	0.00
cycles	0.50	0.50	1.00	1.08	1.00	1.00	1.00	0.92	5.00	5.00	5.00	5.00	1.67	1.67	1.67	0.00	0.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	3.75
Dispatch	5.00
Data deps.	1.00
Overall L1	5.00

Vectorization ratios

all	95%
load	100%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	94%

Vector efficiency ratios

all	97%
load	100%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	97%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 5.00 cycles.

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 11b48

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput	Vectorization
ADD X10, X15, X9	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
DUP V6.2D, X27	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	3	1	scal (50.0%)
ADD X9, X9, #32	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
LDR Q3, [X10, #1824]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
ADD X11, X10, #1816	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
EXT V2.16B, V2.16B, V3.16B, #8	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
AND V4.16B, V3.16B, V23.16B	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
AND V2.16B, V2.16B, V22.16B	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
ORR V2.16B, V4.16B, V2.16B	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
LDP Q4, Q5, [X10]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.67	vect (100.0%)
USHR V2.2D, V2.2D, #1	1	0	0	0	0	0	0	0	0	0	0.50	0	0.50	0	0	0	2	0.50	vect (100.0%)
EOR V2.16B, V2.16B, V4.16B	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
AND V4.16B, V3.16B, V24.16B	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
CMEQ V4.2D, V4.2D, #0	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
BCAX V2.16B, V2.16B, V6.16B, V4.16B	1	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	vect (100.0%)
STR Q2, [X11]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	vect (100.0%)
LDR Q2, [X10, #1840]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
ADD X10, X10, #1832	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
EXT V3.16B, V3.16B, V2.16B, #8	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
AND V4.16B, V2.16B, V23.16B	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
AND V3.16B, V3.16B, V22.16B	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
ORR V3.16B, V4.16B, V3.16B	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
AND V4.16B, V2.16B, V24.16B	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
USHR V3.2D, V3.2D, #1	1	0	0	0	0	0	0	0	0	0	0.50	0	0.50	0	0	0	2	0.50	vect (100.0%)
CMEQ V4.2D, V4.2D, #0	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
EOR V3.16B, V3.16B, V5.16B	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
BCAX V3.16B, V3.16B, V6.16B, V4.16B	1	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	vect (100.0%)
STR Q3, [X10]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	vect (100.0%)
CMP X9, #3168	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	1	0.33	N/A
B.NE 11b48 <main+0x928>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Report Configuration

Vectorization

Details

Slow data structures access

Details

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Slow data structures access

Details

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code