OV - attention-armclang-native - Loop 81 - attention-armclang-native

	Loop Id: 81	Module: attention-armclang-native	Source: random.tcc:404-409	Coverage: 0.18%

0x119e8 ADD	X10, X15, X9

0x119ec ADD	X9, X9, #64

0x119f0 LDUR	Q3, [X10, #8]    [4]

0x119f4 LDUR	Q4, [X10, #24]    [4]

0x119f8 LDUR	Q5, [X10, #40]    [4]

0x119fc ADD	X12, X10, #3192

0x11a00 ADD	X11, X10, #3176

0x11a04 ADD	X13, X10, #3208

0x11a08 ADD	X14, X10, #3224

0x11a0c EXT	V6.16B, V2.16B, V3.16B, #8

0x11a10 LDUR	Q2, [X10, #56]    [4]

0x11a14 EXT	V7.16B, V3.16B, V4.16B, #8

0x11a18 AND	V19.16B, V4.16B, V23.16B

0x11a1c EXT	V16.16B, V4.16B, V5.16B, #8

0x11a20 AND	V18.16B, V3.16B, V23.16B

0x11a24 AND	V20.16B, V5.16B, V23.16B

0x11a28 AND	V3.16B, V3.16B, V24.16B

0x11a2c AND	V4.16B, V4.16B, V24.16B

0x11a30 AND	V7.16B, V7.16B, V22.16B

0x11a34 AND	V6.16B, V6.16B, V22.16B

0x11a38 AND	V16.16B, V16.16B, V22.16B

0x11a3c CMEQ	V3.2D, V3.2D, #0

0x11a40 CMEQ	V4.2D, V4.2D, #0

0x11a44 ORR	V7.16B, V19.16B, V7.16B

0x11a48 LDR	Q19, [X12]    [1]

0x11a4c ORR	V6.16B, V18.16B, V6.16B

0x11a50 LDR	Q18, [X11]    [2]

0x11a54 ORR	V16.16B, V20.16B, V16.16B

0x11a58 LDR	Q20, [X13]    [5]

0x11a5c EXT	V17.16B, V5.16B, V2.16B, #8

0x11a60 AND	V21.16B, V2.16B, V23.16B

0x11a64 USHR	V7.2D, V7.2D, #1

0x11a68 USHR	V6.2D, V6.2D, #1

0x11a6c USHR	V16.2D, V16.2D, #1

0x11a70 AND	V5.16B, V5.16B, V24.16B

0x11a74 AND	V17.16B, V17.16B, V22.16B

0x11a78 CMEQ	V5.2D, V5.2D, #0

0x11a7c ORR	V17.16B, V21.16B, V17.16B

0x11a80 LDR	Q21, [X14]    [3]

0x11a84 EOR	V7.16B, V7.16B, V19.16B

0x11a88 DUP	V19.2D, X27

0x11a8c EOR	V6.16B, V6.16B, V18.16B

0x11a90 AND	V18.16B, V2.16B, V24.16B

0x11a94 EOR	V16.16B, V16.16B, V20.16B

0x11a98 USHR	V17.2D, V17.2D, #1

0x11a9c BCAX	V3.16B, V6.16B, V19.16B, V3.16B

0x11aa0 CMEQ	V6.2D, V18.2D, #0

0x11aa4 BCAX	V4.16B, V7.16B, V19.16B, V4.16B

0x11aa8 BCAX	V5.16B, V16.16B, V19.16B, V5.16B

0x11aac STP	Q3, Q4, [X10]    [4]

0x11ab0 EOR	V17.16B, V17.16B, V21.16B

0x11ab4 BCAX	V6.16B, V17.16B, V19.16B, V6.16B

0x11ab8 STP	Q5, Q6, [X10, #32]    [4]

0x11abc CMP	X9, #1792

0x11ac0 B.NE	119e8

/usr/lib/gcc/aarch64-amazon-linux/14/../../../../include/c++/14/bits/random.tcc: 404 - 409

--------------------------------------------------------------------------------

404:       for (size_t __k = 0; __k < (__n - __m); ++__k)

405:         {

406: 	  _UIntType __y = ((_M_x[__k] & __upper_mask)

407: 			   | (_M_x[__k + 1] & __lower_mask));

408: 	  _M_x[__k] = (_M_x[__k + __m] ^ (__y >> 1)

409: 		       ^ ((__y & 0x01) ? __a : 0));

Coverage (%)	Name	Module
►100.00+	__libc_start_call_main	libc.so.6
○	__libc_start_main	libc.so.6
○	_start	attention-armclang-native

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.38
Bottlenecks	P8, P9, P10, P11,
Function	main
Source	random.tcc:404-409
Source loop unroll info	multi-versionned
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	9.50
CQA cycles if no scalar integer	9.50
CQA cycles if FP arith vectorized	9.50
CQA cycles if fully vectorized	9.50
Front-end cycles	6.88
P0 cycles	0.50
P1 cycles	0.50
P2 cycles	1.33
P3 cycles	1.42
P4 cycles	1.33
P5 cycles	1.33
P6 cycles	1.33
P7 cycles	1.25
P8 cycles	9.50
P9 cycles	9.50
P10 cycles	9.50
P11 cycles	9.50
P12 cycles	3.33
P13 cycles	3.33
P14 cycles	3.33
P15 cycles	0.00
P16 cycles	0.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	55.00
Nb uops	55.00
Nb loads	NA
Nb stores	2.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	0.00
Bytes prefetched	0.00
Bytes loaded	0.00
Bytes stored	0.00
Stride 0	0.00
Stride 1	0.00
Stride n	0.00
Stride unknown	5.00
Stride indirect	0.00
Vectorization ratio all	97.87
Vectorization ratio load	100.00
Vectorization ratio store	100.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	97.30
Vector-efficiency ratio all	98.94
Vector-efficiency ratio load	100.00
Vector-efficiency ratio store	100.00
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	98.65

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.38
Bottlenecks	P8, P9, P10, P11,
Function	main
Source	random.tcc:404-409
Source loop unroll info	multi-versionned
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	9.50
CQA cycles if no scalar integer	9.50
CQA cycles if FP arith vectorized	9.50
CQA cycles if fully vectorized	9.50
Front-end cycles	6.88
P0 cycles	0.50
P1 cycles	0.50
P2 cycles	1.33
P3 cycles	1.42
P4 cycles	1.33
P5 cycles	1.33
P6 cycles	1.33
P7 cycles	1.25
P8 cycles	9.50
P9 cycles	9.50
P10 cycles	9.50
P11 cycles	9.50
P12 cycles	3.33
P13 cycles	3.33
P14 cycles	3.33
P15 cycles	0.00
P16 cycles	0.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	55.00
Nb uops	55.00
Nb loads	NA
Nb stores	2.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	0.00
Bytes prefetched	0.00
Bytes loaded	0.00
Bytes stored	0.00
Stride 0	0.00
Stride 1	0.00
Stride n	0.00
Stride unknown	5.00
Stride indirect	0.00
Vectorization ratio all	97.87
Vectorization ratio load	100.00
Vectorization ratio store	100.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	97.30
Vector-efficiency ratio all	98.94
Vector-efficiency ratio load	100.00
Vector-efficiency ratio store	100.00
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	98.65

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	main
Source file and lines	random.tcc:404-409
Module	attention-armclang-native

The loop is defined in /usr/lib/gcc/aarch64-amazon-linux/14/../../../../include/c++/14/bits/random.tcc:404-409.

The related source loop is multi-versionned.

gain
potential
hint
expert

Vectorization

Your loop is highly vectorized. 98% of vector register length is used (average across all VPU instructions).

Details

97% of VPU instructions are used in vector version (process two or more data elements in vector registers):

97% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

No data for this section

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant unknown stride: 5 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop does not load or store any data.

General properties

nb instructions	55
nb uops	55
loop length	220
used w registers	0
used x registers	8
used b registers	0
used h registers	0
used s registers	0
used d registers	0
used q registers	9
used v registers	15
used z registers	0
nb stack references	0

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	6.88 cycles
front end	6.88 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	0.50	0.50	1.33	1.42	1.33	1.33	1.33	1.25	9.50	9.50	9.50	9.50	3.33	3.33	3.33	0.00	0.00
cycles	0.50	0.50	1.33	1.42	1.33	1.33	1.33	1.25	9.50	9.50	9.50	9.50	3.33	3.33	3.33	0.00	0.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	6.88
Dispatch	9.50
Data deps.	1.00
Overall L1	9.50

Vectorization ratios

all	97%
load	100%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	97%

Vector efficiency ratios

all	98%
load	100%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	98%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 9.50 cycles.

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 119e8

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput	Vectorization
ADD X10, X15, X9	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
ADD X9, X9, #64	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
LDUR Q3, [X10, #8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
LDUR Q4, [X10, #24]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
LDUR Q5, [X10, #40]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
ADD X12, X10, #3192	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
ADD X11, X10, #3176	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
ADD X13, X10, #3208	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
ADD X14, X10, #3224	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
EXT V6.16B, V2.16B, V3.16B, #8	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
LDUR Q2, [X10, #56]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
EXT V7.16B, V3.16B, V4.16B, #8	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
AND V19.16B, V4.16B, V23.16B	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
EXT V16.16B, V4.16B, V5.16B, #8	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
AND V18.16B, V3.16B, V23.16B	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
AND V20.16B, V5.16B, V23.16B	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
AND V3.16B, V3.16B, V24.16B	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
AND V4.16B, V4.16B, V24.16B	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
AND V7.16B, V7.16B, V22.16B	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
AND V6.16B, V6.16B, V22.16B	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
AND V16.16B, V16.16B, V22.16B	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
CMEQ V3.2D, V3.2D, #0	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
CMEQ V4.2D, V4.2D, #0	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
ORR V7.16B, V19.16B, V7.16B	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
LDR Q19, [X12]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
ORR V6.16B, V18.16B, V6.16B	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
LDR Q18, [X11]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
ORR V16.16B, V20.16B, V16.16B	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
LDR Q20, [X13]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
EXT V17.16B, V5.16B, V2.16B, #8	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
AND V21.16B, V2.16B, V23.16B	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
USHR V7.2D, V7.2D, #1	1	0	0	0	0	0	0	0	0	0	0.50	0	0.50	0	0	0	2	0.50	vect (100.0%)
USHR V6.2D, V6.2D, #1	1	0	0	0	0	0	0	0	0	0	0.50	0	0.50	0	0	0	2	0.50	vect (100.0%)
USHR V16.2D, V16.2D, #1	1	0	0	0	0	0	0	0	0	0	0.50	0	0.50	0	0	0	2	0.50	vect (100.0%)
AND V5.16B, V5.16B, V24.16B	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
AND V17.16B, V17.16B, V22.16B	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
CMEQ V5.2D, V5.2D, #0	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
ORR V17.16B, V21.16B, V17.16B	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
LDR Q21, [X14]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
EOR V7.16B, V7.16B, V19.16B	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
DUP V19.2D, X27	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	3	1	scal (50.0%)
EOR V6.16B, V6.16B, V18.16B	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
AND V18.16B, V2.16B, V24.16B	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
EOR V16.16B, V16.16B, V20.16B	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
USHR V17.2D, V17.2D, #1	1	0	0	0	0	0	0	0	0	0	0.50	0	0.50	0	0	0	2	0.50	vect (100.0%)
BCAX V3.16B, V6.16B, V19.16B, V3.16B	1	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	vect (100.0%)
CMEQ V6.2D, V18.2D, #0	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
BCAX V4.16B, V7.16B, V19.16B, V4.16B	1	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	vect (100.0%)
BCAX V5.16B, V16.16B, V19.16B, V5.16B	1	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	vect (100.0%)
STP Q3, Q4, [X10]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	1	vect (100.0%)
EOR V17.16B, V17.16B, V21.16B	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
BCAX V6.16B, V17.16B, V19.16B, V6.16B	1	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	vect (100.0%)
STP Q5, Q6, [X10, #32]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	1	vect (100.0%)
CMP X9, #1792	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	1	0.33	N/A
B.NE 119e8 <main+0x7c8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Function	main
Source file and lines	random.tcc:404-409
Module	attention-armclang-native

The loop is defined in /usr/lib/gcc/aarch64-amazon-linux/14/../../../../include/c++/14/bits/random.tcc:404-409.

The related source loop is multi-versionned.

gain
potential
hint
expert

Vectorization

Your loop is highly vectorized. 98% of vector register length is used (average across all VPU instructions).

Details

97% of VPU instructions are used in vector version (process two or more data elements in vector registers):

97% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

No data for this section

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant unknown stride: 5 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop does not load or store any data.

General properties

nb instructions	55
nb uops	55
loop length	220
used w registers	0
used x registers	8
used b registers	0
used h registers	0
used s registers	0
used d registers	0
used q registers	9
used v registers	15
used z registers	0
nb stack references	0

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	6.88 cycles
front end	6.88 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	0.50	0.50	1.33	1.42	1.33	1.33	1.33	1.25	9.50	9.50	9.50	9.50	3.33	3.33	3.33	0.00	0.00
cycles	0.50	0.50	1.33	1.42	1.33	1.33	1.33	1.25	9.50	9.50	9.50	9.50	3.33	3.33	3.33	0.00	0.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	6.88
Dispatch	9.50
Data deps.	1.00
Overall L1	9.50

Vectorization ratios

all	97%
load	100%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	97%

Vector efficiency ratios

all	98%
load	100%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	98%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 9.50 cycles.

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 119e8

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput	Vectorization
ADD X10, X15, X9	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
ADD X9, X9, #64	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
LDUR Q3, [X10, #8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
LDUR Q4, [X10, #24]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
LDUR Q5, [X10, #40]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
ADD X12, X10, #3192	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
ADD X11, X10, #3176	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
ADD X13, X10, #3208	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
ADD X14, X10, #3224	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
EXT V6.16B, V2.16B, V3.16B, #8	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
LDUR Q2, [X10, #56]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
EXT V7.16B, V3.16B, V4.16B, #8	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
AND V19.16B, V4.16B, V23.16B	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
EXT V16.16B, V4.16B, V5.16B, #8	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
AND V18.16B, V3.16B, V23.16B	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
AND V20.16B, V5.16B, V23.16B	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
AND V3.16B, V3.16B, V24.16B	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
AND V4.16B, V4.16B, V24.16B	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
AND V7.16B, V7.16B, V22.16B	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
AND V6.16B, V6.16B, V22.16B	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
AND V16.16B, V16.16B, V22.16B	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
CMEQ V3.2D, V3.2D, #0	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
CMEQ V4.2D, V4.2D, #0	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
ORR V7.16B, V19.16B, V7.16B	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
LDR Q19, [X12]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
ORR V6.16B, V18.16B, V6.16B	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
LDR Q18, [X11]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
ORR V16.16B, V20.16B, V16.16B	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
LDR Q20, [X13]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
EXT V17.16B, V5.16B, V2.16B, #8	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
AND V21.16B, V2.16B, V23.16B	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
USHR V7.2D, V7.2D, #1	1	0	0	0	0	0	0	0	0	0	0.50	0	0.50	0	0	0	2	0.50	vect (100.0%)
USHR V6.2D, V6.2D, #1	1	0	0	0	0	0	0	0	0	0	0.50	0	0.50	0	0	0	2	0.50	vect (100.0%)
USHR V16.2D, V16.2D, #1	1	0	0	0	0	0	0	0	0	0	0.50	0	0.50	0	0	0	2	0.50	vect (100.0%)
AND V5.16B, V5.16B, V24.16B	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
AND V17.16B, V17.16B, V22.16B	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
CMEQ V5.2D, V5.2D, #0	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
ORR V17.16B, V21.16B, V17.16B	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
LDR Q21, [X14]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
EOR V7.16B, V7.16B, V19.16B	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
DUP V19.2D, X27	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	3	1	scal (50.0%)
EOR V6.16B, V6.16B, V18.16B	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
AND V18.16B, V2.16B, V24.16B	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
EOR V16.16B, V16.16B, V20.16B	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
USHR V17.2D, V17.2D, #1	1	0	0	0	0	0	0	0	0	0	0.50	0	0.50	0	0	0	2	0.50	vect (100.0%)
BCAX V3.16B, V6.16B, V19.16B, V3.16B	1	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	vect (100.0%)
CMEQ V6.2D, V18.2D, #0	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
BCAX V4.16B, V7.16B, V19.16B, V4.16B	1	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	vect (100.0%)
BCAX V5.16B, V16.16B, V19.16B, V5.16B	1	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	vect (100.0%)
STP Q3, Q4, [X10]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	1	vect (100.0%)
EOR V17.16B, V17.16B, V21.16B	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
BCAX V6.16B, V17.16B, V19.16B, V6.16B	1	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	vect (100.0%)
STP Q5, Q6, [X10, #32]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	1	vect (100.0%)
CMP X9, #1792	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	1	0.33	N/A
B.NE 119e8 <main+0x7c8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Report Configuration

Vectorization

Details

Slow data structures access

Details

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Slow data structures access

Details

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code