OV - attention-armclang-native - Loop 80 - attention-armclang-native

	Loop Id: 80	Module: attention-armclang-native	Source: random.tcc:404-3368 [...]	Coverage: 0.55%

0x11940 LDR	X9, [SP, #5664]

0x11944 LDR	X10, [SP, #680]

0x11948 LDR	X11, [SP, #3848]

0x1194c ORR	X21, XZR, XZR

0x11950 AND	X9, X9, #0x0

0x11954 AND	X12, X10, #0x0

0x11958 SBFM	X10, X10, #0, #0

0x1195c ORR	X9, X12, X9

0x11960 AND	X10, X10, X27

0x11964 EOR	X9, X11, X9,LSR #1

0x11968 EOR	X9, X9, X10

0x1196c STR	X9, [SP, #5664]

0x11970 ORR	X9, XZR, X21

0x11974 ADD	X21, X21, #1

0x11978 ADD	X10, SP, #680

0x1197c SUBS	X8, X8, #1

0x11980 STR	X21, [SP, #5672]

0x11984 LDR	X9, [X10, X9,LSL #3]

0x11988 UBFM	X10, X9, #11, #42

0x1198c EOR	X9, X10, X9

0x11990 MOVZ	W10, #22144

0x11994 MOVK	W10, #40236

0x11998 AND	X10, X10, X9,LSL #7

0x1199c EOR	X9, X10, X9

0x119a0 MOVZ	W10, #61382

0x119a4 AND	X10, X10, X9,LSL #15

0x119a8 EOR	X9, X10, X9

0x119ac EOR	X9, X9, X9,LSR #18

0x119b0 UCVTF	S2, X9

0x119b4 MOVZ	W9, #20352

0x119b8 FMADD	S0, S2, S1, S0

0x119bc FMOV	S2, W9

0x119c0 FMUL	S1, S1, S2

0x119c4 B.EQ	11bc4

0x119c8 CMP	X21, #624

0x119cc B.CC	11970

0x119d0 ADD	X15, SP, #680

0x119d4 DUPM	Z22.D, #0x80000000

0x119d8 DUPM	Z23.D, #0x7ffffffe

0x119dc DUP	Z24.D, #1

0x119e0 ORR	X9, XZR, XZR

0x119e4 LD1R	{V2.2D}, [X15]

  (81) 0x119e8 ADD	X10, X15, X9

  (81) 0x119ec ADD	X9, X9, #64

  (81) 0x119f0 LDUR	Q3, [X10, #8]

  (81) 0x119f4 LDUR	Q4, [X10, #24]

  (81) 0x119f8 LDUR	Q5, [X10, #40]

  (81) 0x119fc ADD	X12, X10, #3192

  (81) 0x11a00 ADD	X11, X10, #3176

  (81) 0x11a04 ADD	X13, X10, #3208

  (81) 0x11a08 ADD	X14, X10, #3224

  (81) 0x11a0c EXT	V6.16B, V2.16B, V3.16B, #8

  (81) 0x11a10 LDUR	Q2, [X10, #56]

  (81) 0x11a14 EXT	V7.16B, V3.16B, V4.16B, #8

  (81) 0x11a18 AND	V19.16B, V4.16B, V23.16B

  (81) 0x11a1c EXT	V16.16B, V4.16B, V5.16B, #8

  (81) 0x11a20 AND	V18.16B, V3.16B, V23.16B

  (81) 0x11a24 AND	V20.16B, V5.16B, V23.16B

  (81) 0x11a28 AND	V3.16B, V3.16B, V24.16B

  (81) 0x11a2c AND	V4.16B, V4.16B, V24.16B

  (81) 0x11a30 AND	V7.16B, V7.16B, V22.16B

  (81) 0x11a34 AND	V6.16B, V6.16B, V22.16B

  (81) 0x11a38 AND	V16.16B, V16.16B, V22.16B

  (81) 0x11a3c CMEQ	V3.2D, V3.2D, #0

  (81) 0x11a40 CMEQ	V4.2D, V4.2D, #0

  (81) 0x11a44 ORR	V7.16B, V19.16B, V7.16B

  (81) 0x11a48 LDR	Q19, [X12]

  (81) 0x11a4c ORR	V6.16B, V18.16B, V6.16B

  (81) 0x11a50 LDR	Q18, [X11]

  (81) 0x11a54 ORR	V16.16B, V20.16B, V16.16B

  (81) 0x11a58 LDR	Q20, [X13]

  (81) 0x11a5c EXT	V17.16B, V5.16B, V2.16B, #8

  (81) 0x11a60 AND	V21.16B, V2.16B, V23.16B

  (81) 0x11a64 USHR	V7.2D, V7.2D, #1

  (81) 0x11a68 USHR	V6.2D, V6.2D, #1

  (81) 0x11a6c USHR	V16.2D, V16.2D, #1

  (81) 0x11a70 AND	V5.16B, V5.16B, V24.16B

  (81) 0x11a74 AND	V17.16B, V17.16B, V22.16B

  (81) 0x11a78 CMEQ	V5.2D, V5.2D, #0

  (81) 0x11a7c ORR	V17.16B, V21.16B, V17.16B

  (81) 0x11a80 LDR	Q21, [X14]

  (81) 0x11a84 EOR	V7.16B, V7.16B, V19.16B

  (81) 0x11a88 DUP	V19.2D, X27

  (81) 0x11a8c EOR	V6.16B, V6.16B, V18.16B

  (81) 0x11a90 AND	V18.16B, V2.16B, V24.16B

  (81) 0x11a94 EOR	V16.16B, V16.16B, V20.16B

  (81) 0x11a98 USHR	V17.2D, V17.2D, #1

  (81) 0x11a9c BCAX	V3.16B, V6.16B, V19.16B, V3.16B

  (81) 0x11aa0 CMEQ	V6.2D, V18.2D, #0

  (81) 0x11aa4 BCAX	V4.16B, V7.16B, V19.16B, V4.16B

  (81) 0x11aa8 BCAX	V5.16B, V16.16B, V19.16B, V5.16B

  (81) 0x11aac STP	Q3, Q4, [X10]

  (81) 0x11ab0 EOR	V17.16B, V17.16B, V21.16B

  (81) 0x11ab4 BCAX	V6.16B, V17.16B, V19.16B, V6.16B

  (81) 0x11ab8 STP	Q5, Q6, [X10, #32]

  (81) 0x11abc CMP	X9, #1792

  (81) 0x11ac0 B.NE	119e8

0x11ac4 LDR	X11, [SP, #2480]

0x11ac8 MOV	X10, V2.D[1]

0x11acc ORR	X9, XZR, XZR

0x11ad0 AND	X10, X10, #0x0

0x11ad4 AND	X12, X11, #0x0

0x11ad8 ORR	X10, X12, X10

0x11adc LDR	X12, [SP, #5648]

0x11ae0 EOR	X10, X12, X10,LSR #1

0x11ae4 SBFM	X12, X11, #0, #0

0x11ae8 AND	X12, X12, X27

0x11aec EOR	X10, X10, X12

0x11af0 STR	X10, [SP, #2472]

0x11af4 AND	X10, X11, #0x0

0x11af8 LDR	X11, [SP, #2488]

0x11afc AND	X12, X11, #0x0

0x11b00 ORR	X10, X12, X10

0x11b04 LDR	X12, [SP, #5656]

0x11b08 EOR	X10, X12, X10,LSR #1

0x11b0c SBFM	X12, X11, #0, #0

0x11b10 AND	X12, X12, X27

0x11b14 EOR	X10, X10, X12

0x11b18 STR	X10, [SP, #2480]

0x11b1c AND	X10, X11, #0x0

0x11b20 LDR	X11, [SP, #2496]

0x11b24 AND	X12, X11, #0x0

0x11b28 DUP	V2.2D, X11

0x11b2c ORR	X10, X12, X10

0x11b30 LDR	X12, [SP, #5664]

0x11b34 EOR	X10, X12, X10,LSR #1

0x11b38 SBFM	X12, X11, #0, #0

0x11b3c AND	X12, X12, X27

0x11b40 EOR	X10, X10, X12

0x11b44 STR	X10, [SP, #2488]

  (82) 0x11b48 ADD	X10, X15, X9

  (82) 0x11b4c DUP	V6.2D, X27

  (82) 0x11b50 ADD	X9, X9, #32

  (82) 0x11b54 LDR	Q3, [X10, #1824]

  (82) 0x11b58 ADD	X11, X10, #1816

  (82) 0x11b5c EXT	V2.16B, V2.16B, V3.16B, #8

  (82) 0x11b60 AND	V4.16B, V3.16B, V23.16B

  (82) 0x11b64 AND	V2.16B, V2.16B, V22.16B

  (82) 0x11b68 ORR	V2.16B, V4.16B, V2.16B

  (82) 0x11b6c LDP	Q4, Q5, [X10]

  (82) 0x11b70 USHR	V2.2D, V2.2D, #1

  (82) 0x11b74 EOR	V2.16B, V2.16B, V4.16B

  (82) 0x11b78 AND	V4.16B, V3.16B, V24.16B

  (82) 0x11b7c CMEQ	V4.2D, V4.2D, #0

  (82) 0x11b80 BCAX	V2.16B, V2.16B, V6.16B, V4.16B

  (82) 0x11b84 STR	Q2, [X11]

  (82) 0x11b88 LDR	Q2, [X10, #1840]

  (82) 0x11b8c ADD	X10, X10, #1832

  (82) 0x11b90 EXT	V3.16B, V3.16B, V2.16B, #8

  (82) 0x11b94 AND	V4.16B, V2.16B, V23.16B

  (82) 0x11b98 AND	V3.16B, V3.16B, V22.16B

  (82) 0x11b9c ORR	V3.16B, V4.16B, V3.16B

  (82) 0x11ba0 AND	V4.16B, V2.16B, V24.16B

  (82) 0x11ba4 USHR	V3.2D, V3.2D, #1

  (82) 0x11ba8 CMEQ	V4.2D, V4.2D, #0

  (82) 0x11bac EOR	V3.16B, V3.16B, V5.16B

  (82) 0x11bb0 BCAX	V3.16B, V3.16B, V6.16B, V4.16B

  (82) 0x11bb4 STR	Q3, [X10]

  (82) 0x11bb8 CMP	X9, #3168

  (82) 0x11bbc B.NE	11b48

0x11bc0 B	11940

/usr/lib/gcc/aarch64-amazon-linux/14/../../../../include/c++/14/bits/random.tcc: 404 - 3368

--------------------------------------------------------------------------------

404:       for (size_t __k = 0; __k < (__n - __m); ++__k)

405:         {

406: 	  _UIntType __y = ((_M_x[__k] & __upper_mask)

407: 			   | (_M_x[__k + 1] & __lower_mask));

408: 	  _M_x[__k] = (_M_x[__k + __m] ^ (__y >> 1)

409: 		       ^ ((__y & 0x01) ? __a : 0));

410:         }

411:

412:       for (size_t __k = (__n - __m); __k < (__n - 1); ++__k)

413: 	{

414: 	  _UIntType __y = ((_M_x[__k] & __upper_mask)

415: 			   | (_M_x[__k + 1] & __lower_mask));

416: 	  _M_x[__k] = (_M_x[__k + (__m - __n)] ^ (__y >> 1)

417: 		       ^ ((__y & 0x01) ? __a : 0));

418: 	}

419:

420:       _UIntType __y = ((_M_x[__n - 1] & __upper_mask)

421: 		       | (_M_x[0] & __lower_mask));

422:       _M_x[__n - 1] = (_M_x[__m - 1] ^ (__y >> 1)

423: 		       ^ ((__y & 0x01) ? __a : 0));

[...]

458:       if (_M_p >= state_size)

459: 	_M_gen_rand();

460:

461:       // Calculate o(x(i)).

462:       result_type __z = _M_x[_M_p++];

463:       __z ^= (__z >> __u) & __d;

464:       __z ^= (__z << __s) & __b;

465:       __z ^= (__z << __t) & __c;

466:       __z ^= (__z >> __l);

[...]

3365:       for (size_t __k = __m; __k != 0; --__k)

3366: 	{

3367: 	  __sum += _RealType(__urng() - __urng.min()) * __tmp;

3368: 	  __tmp *= __r;

Coverage (%)	Name	Module
►100.00+	__libc_start_call_main	libc.so.6
○	__libc_start_main	libc.so.6
○	_start	attention-armclang-native

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	7.60
CQA speedup if FP arith vectorized	1.94
CQA speedup if fully vectorized	1.25
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.13
Bottlenecks	micro-operation queue,
Function	main
Source	random.tcc:404-409,random.tcc:412-412,random.tcc:420-423,random.tcc:458-458,random.tcc:462-466,random.tcc:3365-3368
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	9.50
CQA cycles if no scalar integer	1.25
CQA cycles if FP arith vectorized	4.91
CQA cycles if fully vectorized	7.57
Front-end cycles	9.50
P0 cycles	1.50
P1 cycles	1.50
P2 cycles	8.42
P3 cycles	8.25
P4 cycles	8.33
P5 cycles	8.33
P6 cycles	8.33
P7 cycles	8.33
P8 cycles	2.00
P9 cycles	2.00
P10 cycles	2.00
P11 cycles	2.00
P12 cycles	5.50
P13 cycles	5.17
P14 cycles	5.33
P15 cycles	2.50
P16 cycles	2.50
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	76.00
Nb uops	76.00
Nb loads	NA
Nb stores	5.00
Nb stack references	14.00
FLOP/cycle	0.32
Nb FLOP add-sub	0.00
Nb FLOP mul	1.00
Nb FLOP fma	1.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	0.84
Bytes prefetched	0.00
Bytes loaded	8.00
Bytes stored	0.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	5.56
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	0.00
Vectorization ratio add_sub	0.00
Vectorization ratio fma	0.00
Vectorization ratio div_sqrt	NA
Vectorization ratio other	10.53
Vector-efficiency ratio all	53.65
Vector-efficiency ratio load	50.00
Vector-efficiency ratio store	50.00
Vector-efficiency ratio mul	25.00
Vector-efficiency ratio add_sub	50.00
Vector-efficiency ratio fma	25.00
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	59.54

Metric	Value
CQA speedup if no scalar integer	7.60
CQA speedup if FP arith vectorized	1.94
CQA speedup if fully vectorized	1.25
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.13
Bottlenecks	micro-operation queue,
Function	main
Source	random.tcc:404-409,random.tcc:412-412,random.tcc:420-423,random.tcc:458-458,random.tcc:462-466,random.tcc:3365-3368
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	9.50
CQA cycles if no scalar integer	1.25
CQA cycles if FP arith vectorized	4.91
CQA cycles if fully vectorized	7.57
Front-end cycles	9.50
P0 cycles	1.50
P1 cycles	1.50
P2 cycles	8.42
P3 cycles	8.25
P4 cycles	8.33
P5 cycles	8.33
P6 cycles	8.33
P7 cycles	8.33
P8 cycles	2.00
P9 cycles	2.00
P10 cycles	2.00
P11 cycles	2.00
P12 cycles	5.50
P13 cycles	5.17
P14 cycles	5.33
P15 cycles	2.50
P16 cycles	2.50
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	76.00
Nb uops	76.00
Nb loads	NA
Nb stores	5.00
Nb stack references	14.00
FLOP/cycle	0.32
Nb FLOP add-sub	0.00
Nb FLOP mul	1.00
Nb FLOP fma	1.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	0.84
Bytes prefetched	0.00
Bytes loaded	8.00
Bytes stored	0.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	5.56
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	0.00
Vectorization ratio add_sub	0.00
Vectorization ratio fma	0.00
Vectorization ratio div_sqrt	NA
Vectorization ratio other	10.53
Vector-efficiency ratio all	53.65
Vector-efficiency ratio load	50.00
Vector-efficiency ratio store	50.00
Vector-efficiency ratio mul	25.00
Vector-efficiency ratio add_sub	50.00
Vector-efficiency ratio fma	25.00
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	59.54

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	main
Source file and lines	random.tcc:404-3368
Module	attention-armclang-native

The loop is defined in /usr/lib/gcc/aarch64-amazon-linux/14/../../../../include/c++/14/bits/random.tcc:404-423,458-466,3365-3368.

Analyzed code is defined in /usr/lib/gcc/aarch64-amazon-linux/14/../../../../include/c++/14/bits/random.tcc:404-409,412,420-423,458,462-466,3365-3368.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Failed to get the number of paths
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 9.50 to 1.25 cycles (7.60x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is probably not vectorized. Only 53% of vector register length is used (average across all VPU instructions). By vectorizing your loop, you can lower the cost of an iteration from 9.50 to 7.57 cycles (1.25x speedup).

Details

Store and arithmetical VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ffast-math (included in Ofast) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

FMA

Detected 1 FMA (fused multiply-add) operations.

Conversion instructions

Detected expensive conversion instructions.

Details

UCVTF: 1 occurrences►
- /usr/lib/gcc/aarch64-amazon-linux/14/../../../../include/c++/14/bits/random.tcc:3367

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 3 FP arithmetical operations:

1: addition or subtraction (all inside FMA instructions)
2: multiply (1 inside FMA instructions)

The binary loop is loading 8 bytes.

Arithmetic intensity

Arithmetic intensity is 0.37 FP operations per loaded or stored byte.

General properties

nb instructions	76
nb uops	76
loop length	304
used w registers	2
used x registers	9
used b registers	0
used h registers	0
used s registers	4
used d registers	0
used q registers	0
used v registers	1
used z registers	3
nb stack references	14

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	9.50 cycles
front end	9.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	1.50	1.50	8.42	8.25	8.33	8.33	8.33	8.33	2.00	2.00	2.00	2.00	5.50	5.17	5.33	2.50	2.50
cycles	1.50	1.50	8.42	8.25	8.33	8.33	8.33	8.33	2.00	2.00	2.00	2.00	5.50	5.17	5.33	2.50	2.50

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	9.50
Dispatch	8.42
Overall L1	9.50

Vectorization ratios

INT

all	6%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	11%

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	0%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

INT+FP

all	5%
load	0%
store	0%
mul	0%
add-sub	0%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	10%

Vector efficiency ratios

INT

all	56%
load	50%
store	50%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	50%
fma	NA (no fma vectorizable/vectorized instructions)
other	61%

all	25%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	25%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	25%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	25%

INT+FP

all	53%
load	50%
store	50%
mul	25%
add-sub	50%
fma	25%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	59%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 9.50 cycles. At this rate:

0% of peak load performance is reached (0.84 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 9.50 to 8.42 cycles (1.13x speedup).

ASM code

In the binary file, the address of the loop is: 119c8

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
LDR X9, [SP, #5664]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X10, [SP, #680]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X11, [SP, #3848]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
ORR X21, XZR, XZR	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
AND X9, X9, #0x0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
AND X12, X10, #0x0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
SBFM X10, X10, #0, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ORR X9, X12, X9	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
AND X10, X10, X27	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
EOR X9, X11, X9,LSR #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
EOR X9, X9, X10	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STR X9, [SP, #5664]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ORR X9, XZR, X21	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X21, X21, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ADD X10, SP, #680	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUBS X8, X8, #1	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
STR X21, [SP, #5672]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X9, [X10, X9,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
UBFM X10, X9, #11, #42	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
EOR X9, X10, X9	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOVZ W10, #22144	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOVK W10, #40236	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
AND X10, X10, X9,LSL #7	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
EOR X9, X10, X9	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOVZ W10, #61382	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
AND X10, X10, X9,LSL #15	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
EOR X9, X10, X9	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
EOR X9, X9, X9,LSR #18	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
UCVTF S2, X9	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (50.0%)
MOVZ W9, #20352	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
FMADD S0, S2, S1, S0	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25	scal (25.0%)
FMOV S2, W9	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
FMUL S1, S1, S2	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	scal (25.0%)
B.EQ 11bc4 <main+0x9a4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X21, #624	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.CC 11970 <main+0x750>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X15, SP, #680	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
DUPM Z22.D, #0x80000000	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
DUPM Z23.D, #0x7ffffffe	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
DUP Z24.D, #1	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (6.3%)
ORR X9, XZR, XZR	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LD1R {V2.2D}, [X15]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	0	0	8	0.33	scal (50.0%)
LDR X11, [SP, #2480]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
MOV X10, V2.D[1]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	1	scal (50.0%)
ORR X9, XZR, XZR	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
AND X10, X10, #0x0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
AND X12, X11, #0x0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ORR X10, X12, X10	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR X12, [SP, #5648]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
EOR X10, X12, X10,LSR #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SBFM X12, X11, #0, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (100.0%)
AND X12, X12, X27	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
EOR X10, X10, X12	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STR X10, [SP, #2472]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
AND X10, X11, #0x0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR X11, [SP, #2488]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
AND X12, X11, #0x0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ORR X10, X12, X10	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR X12, [SP, #5656]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
EOR X10, X12, X10,LSR #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SBFM X12, X11, #0, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (100.0%)
AND X12, X12, X27	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
EOR X10, X10, X12	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STR X10, [SP, #2480]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
AND X10, X11, #0x0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR X11, [SP, #2496]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
AND X12, X11, #0x0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
DUP V2.2D, X11	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (50.0%)
ORR X10, X12, X10	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR X12, [SP, #5664]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
EOR X10, X12, X10,LSR #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SBFM X12, X11, #0, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (100.0%)
AND X12, X12, X27	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
EOR X10, X10, X12	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STR X10, [SP, #2488]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
B 11940 <main+0x720>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Function	main
Source file and lines	random.tcc:404-3368
Module	attention-armclang-native

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Failed to get the number of paths
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 9.50 to 1.25 cycles (7.60x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

Workaround

Try another compiler or update/tune your current one:
- recompile with ffast-math (included in Ofast) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

FMA

Detected 1 FMA (fused multiply-add) operations.

Conversion instructions

Detected expensive conversion instructions.

Details

UCVTF: 1 occurrences►
- /usr/lib/gcc/aarch64-amazon-linux/14/../../../../include/c++/14/bits/random.tcc:3367

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 3 FP arithmetical operations:

1: addition or subtraction (all inside FMA instructions)
2: multiply (1 inside FMA instructions)

The binary loop is loading 8 bytes.

Arithmetic intensity

Arithmetic intensity is 0.37 FP operations per loaded or stored byte.

General properties

nb instructions	76
nb uops	76
loop length	304
used w registers	2
used x registers	9
used b registers	0
used h registers	0
used s registers	4
used d registers	0
used q registers	0
used v registers	1
used z registers	3
nb stack references	14

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	9.50 cycles
front end	9.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	1.50	1.50	8.42	8.25	8.33	8.33	8.33	8.33	2.00	2.00	2.00	2.00	5.50	5.17	5.33	2.50	2.50
cycles	1.50	1.50	8.42	8.25	8.33	8.33	8.33	8.33	2.00	2.00	2.00	2.00	5.50	5.17	5.33	2.50	2.50

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	9.50
Dispatch	8.42
Overall L1	9.50

Vectorization ratios

INT

all	6%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	11%

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	0%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

INT+FP

all	5%
load	0%
store	0%
mul	0%
add-sub	0%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	10%

Vector efficiency ratios

INT

all	56%
load	50%
store	50%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	50%
fma	NA (no fma vectorizable/vectorized instructions)
other	61%

all	25%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	25%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	25%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	25%

INT+FP

all	53%
load	50%
store	50%
mul	25%
add-sub	50%
fma	25%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	59%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 9.50 cycles. At this rate:

0% of peak load performance is reached (0.84 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the loop is: 119c8

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
LDR X9, [SP, #5664]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X10, [SP, #680]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X11, [SP, #3848]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
ORR X21, XZR, XZR	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
AND X9, X9, #0x0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
AND X12, X10, #0x0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
SBFM X10, X10, #0, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ORR X9, X12, X9	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
AND X10, X10, X27	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
EOR X9, X11, X9,LSR #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
EOR X9, X9, X10	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STR X9, [SP, #5664]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ORR X9, XZR, X21	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X21, X21, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ADD X10, SP, #680	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUBS X8, X8, #1	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
STR X21, [SP, #5672]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X9, [X10, X9,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
UBFM X10, X9, #11, #42	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
EOR X9, X10, X9	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOVZ W10, #22144	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOVK W10, #40236	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
AND X10, X10, X9,LSL #7	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
EOR X9, X10, X9	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOVZ W10, #61382	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
AND X10, X10, X9,LSL #15	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
EOR X9, X10, X9	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
EOR X9, X9, X9,LSR #18	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
UCVTF S2, X9	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (50.0%)
MOVZ W9, #20352	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
FMADD S0, S2, S1, S0	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25	scal (25.0%)
FMOV S2, W9	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
FMUL S1, S1, S2	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	scal (25.0%)
B.EQ 11bc4 <main+0x9a4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X21, #624	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.CC 11970 <main+0x750>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X15, SP, #680	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
DUPM Z22.D, #0x80000000	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
DUPM Z23.D, #0x7ffffffe	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
DUP Z24.D, #1	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (6.3%)
ORR X9, XZR, XZR	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LD1R {V2.2D}, [X15]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	0	0	8	0.33	scal (50.0%)
LDR X11, [SP, #2480]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
MOV X10, V2.D[1]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	1	scal (50.0%)
ORR X9, XZR, XZR	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
AND X10, X10, #0x0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
AND X12, X11, #0x0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ORR X10, X12, X10	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR X12, [SP, #5648]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
EOR X10, X12, X10,LSR #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SBFM X12, X11, #0, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (100.0%)
AND X12, X12, X27	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
EOR X10, X10, X12	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STR X10, [SP, #2472]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
AND X10, X11, #0x0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR X11, [SP, #2488]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
AND X12, X11, #0x0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ORR X10, X12, X10	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR X12, [SP, #5656]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
EOR X10, X12, X10,LSR #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SBFM X12, X11, #0, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (100.0%)
AND X12, X12, X27	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
EOR X10, X10, X12	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STR X10, [SP, #2480]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
AND X10, X11, #0x0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR X11, [SP, #2496]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
AND X12, X11, #0x0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
DUP V2.2D, X11	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (50.0%)
ORR X10, X12, X10	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR X12, [SP, #5664]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
EOR X10, X12, X10,LSR #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SBFM X12, X11, #0, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (100.0%)
AND X12, X12, X27	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
EOR X10, X10, X12	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STR X10, [SP, #2488]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
B 11940 <main+0x720>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

FMA

Conversion instructions

Details

Workaround

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

FMA

Conversion instructions

Details

Workaround

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code