OV - attention-armclang-native - Loop 70 - attention-armclang-native

	Loop Id: 70	Module: attention-armclang-native	Source: random.tcc:404-3368 [...]	Coverage: 0.06%

0x121a8 ADD	X10, SP, #680

0x121ac LDR	X9, [SP, #5664]

0x121b0 ORR	X21, XZR, XZR

0x121b4 LDR	X10, [X10]

0x121b8 AND	X9, X9, #0x0

0x121bc AND	X11, X10, #0x0

0x121c0 SBFM	X10, X10, #0, #0

0x121c4 ORR	X9, X11, X9

0x121c8 LDR	X11, [SP, #3848]

0x121cc AND	X10, X10, X27

0x121d0 EOR	X9, X11, X9,LSR #1

0x121d4 EOR	X9, X9, X10

0x121d8 STR	X9, [SP, #5664]

0x121dc ORR	X9, XZR, X21

0x121e0 ADD	X21, X21, #1

0x121e4 ADD	X10, SP, #680

0x121e8 SUBS	X8, X8, #1

0x121ec STR	X21, [SP, #5672]

0x121f0 LDR	X9, [X10, X9,LSL #3]

0x121f4 UBFM	X10, X9, #11, #42

0x121f8 EOR	X9, X10, X9

0x121fc MOVZ	W10, #22144

0x12200 MOVK	W10, #40236

0x12204 AND	X10, X10, X9,LSL #7

0x12208 EOR	X9, X10, X9

0x1220c MOVZ	W10, #61382

0x12210 AND	X10, X10, X9,LSL #15

0x12214 EOR	X9, X10, X9

0x12218 EOR	X9, X9, X9,LSR #18

0x1221c UCVTF	S2, X9

0x12220 MOVZ	W9, #20352

0x12224 FMADD	S0, S2, S1, S0

0x12228 FMOV	S2, W9

0x1222c FMUL	S1, S1, S2

0x12230 B.EQ	12420

0x12234 CMP	X21, #624

0x12238 B.CC	121dc

0x1223c ADD	X9, SP, #680

0x12240 DUPM	Z22.D, #0x80000000

0x12244 DUPM	Z23.D, #0x7ffffffe

0x12248 DUP	Z24.D, #1

0x1224c MOVZ	W10, #224

0x12250 LD1R	{V2.2D}, [X9]

0x12254 HINT	#0

0x12258 HINT	#0

0x1225c HINT	#0

  (71) 0x12260 LDUR	Q3, [X9, #8]

  (71) 0x12264 LDUR	Q4, [X9, #24]

  (71) 0x12268 LDUR	Q5, [X9, #40]

  (71) 0x1226c ADD	X11, X9, #3176

  (71) 0x12270 SUBS	X10, X10, #8

  (71) 0x12274 EXT	V6.16B, V2.16B, V3.16B, #8

  (71) 0x12278 LDUR	Q2, [X9, #56]

  (71) 0x1227c EXT	V7.16B, V3.16B, V4.16B, #8

  (71) 0x12280 EXT	V16.16B, V4.16B, V5.16B, #8

  (71) 0x12284 AND	V18.16B, V3.16B, V23.16B

  (71) 0x12288 AND	V19.16B, V4.16B, V23.16B

  (71) 0x1228c AND	V20.16B, V5.16B, V23.16B

  (71) 0x12290 AND	V3.16B, V3.16B, V24.16B

  (71) 0x12294 AND	V4.16B, V4.16B, V24.16B

  (71) 0x12298 AND	V6.16B, V6.16B, V22.16B

  (71) 0x1229c AND	V7.16B, V7.16B, V22.16B

  (71) 0x122a0 AND	V16.16B, V16.16B, V22.16B

  (71) 0x122a4 CMEQ	V3.2D, V3.2D, #0

  (71) 0x122a8 CMEQ	V4.2D, V4.2D, #0

  (71) 0x122ac ORR	V6.16B, V18.16B, V6.16B

  (71) 0x122b0 ORR	V7.16B, V19.16B, V7.16B

  (71) 0x122b4 LDP	Q18, Q19, [X11]

  (71) 0x122b8 ORR	V16.16B, V20.16B, V16.16B

  (71) 0x122bc EXT	V17.16B, V5.16B, V2.16B, #8

  (71) 0x122c0 AND	V21.16B, V2.16B, V23.16B

  (71) 0x122c4 USHR	V7.2D, V7.2D, #1

  (71) 0x122c8 USHR	V6.2D, V6.2D, #1

  (71) 0x122cc USHR	V16.2D, V16.2D, #1

  (71) 0x122d0 AND	V5.16B, V5.16B, V24.16B

  (71) 0x122d4 AND	V17.16B, V17.16B, V22.16B

  (71) 0x122d8 EOR	V7.16B, V7.16B, V19.16B

  (71) 0x122dc DUP	V19.2D, X27

  (71) 0x122e0 CMEQ	V5.2D, V5.2D, #0

  (71) 0x122e4 ORR	V17.16B, V21.16B, V17.16B

  (71) 0x122e8 LDP	Q20, Q21, [X11, #32]

  (71) 0x122ec EOR	V6.16B, V6.16B, V18.16B

  (71) 0x122f0 AND	V18.16B, V2.16B, V24.16B

  (71) 0x122f4 BCAX	V4.16B, V7.16B, V19.16B, V4.16B

  (71) 0x122f8 USHR	V17.2D, V17.2D, #1

  (71) 0x122fc BCAX	V3.16B, V6.16B, V19.16B, V3.16B

  (71) 0x12300 CMEQ	V6.2D, V18.2D, #0

  (71) 0x12304 EOR	V17.16B, V17.16B, V21.16B

  (71) 0x12308 EOR	V16.16B, V16.16B, V20.16B

  (71) 0x1230c BCAX	V6.16B, V17.16B, V19.16B, V6.16B

  (71) 0x12310 STP	Q3, Q4, [X9]

  (71) 0x12314 BCAX	V5.16B, V16.16B, V19.16B, V5.16B

  (71) 0x12318 STP	Q5, Q6, [X9, #32]

  (71) 0x1231c ADD	X9, X9, #64

  (71) 0x12320 B.NE	12260

0x12324 LDR	X10, [SP, #2480]

0x12328 MOV	X9, V2.D[1]

0x1232c AND	X9, X9, #0x0

0x12330 AND	X11, X10, #0x0

0x12334 ORR	X9, X11, X9

0x12338 LDR	X11, [SP, #5648]

0x1233c EOR	X9, X11, X9,LSR #1

0x12340 SBFM	X11, X10, #0, #0

0x12344 AND	X11, X11, X27

0x12348 EOR	X9, X9, X11

0x1234c STR	X9, [SP, #2472]

0x12350 AND	X9, X10, #0x0

0x12354 LDR	X10, [SP, #2488]

0x12358 AND	X11, X10, #0x0

0x1235c ORR	X9, X11, X9

0x12360 LDR	X11, [SP, #5656]

0x12364 EOR	X9, X11, X9,LSR #1

0x12368 SBFM	X11, X10, #0, #0

0x1236c AND	X11, X11, X27

0x12370 EOR	X9, X9, X11

0x12374 STR	X9, [SP, #2480]

0x12378 AND	X9, X10, #0x0

0x1237c LDR	X10, [SP, #2496]

0x12380 AND	X11, X10, #0x0

0x12384 DUP	V2.2D, X10

0x12388 ORR	X9, X11, X9

0x1238c LDR	X11, [SP, #5664]

0x12390 EOR	X9, X11, X9,LSR #1

0x12394 SBFM	X11, X10, #0, #0

0x12398 MOVZ	W10, #396

0x1239c AND	X11, X11, X27

0x123a0 EOR	X9, X9, X11

0x123a4 STR	X9, [SP, #2488]

0x123a8 ADD	X9, SP, #680

  (72) 0x123ac LDR	Q3, [X9, #1824]

  (72) 0x123b0 DUP	V6.2D, X27

  (72) 0x123b4 ADD	X11, X9, #1816

  (72) 0x123b8 SUBS	X10, X10, #4

  (72) 0x123bc EXT	V2.16B, V2.16B, V3.16B, #8

  (72) 0x123c0 AND	V4.16B, V3.16B, V23.16B

  (72) 0x123c4 AND	V2.16B, V2.16B, V22.16B

  (72) 0x123c8 ORR	V2.16B, V4.16B, V2.16B

  (72) 0x123cc LDP	Q4, Q5, [X9]

  (72) 0x123d0 USHR	V2.2D, V2.2D, #1

  (72) 0x123d4 EOR	V2.16B, V2.16B, V4.16B

  (72) 0x123d8 AND	V4.16B, V3.16B, V24.16B

  (72) 0x123dc CMEQ	V4.2D, V4.2D, #0

  (72) 0x123e0 BCAX	V4.16B, V2.16B, V6.16B, V4.16B

  (72) 0x123e4 LDR	Q2, [X9, #1840]

  (72) 0x123e8 ADD	X9, X9, #32

  (72) 0x123ec EXT	V3.16B, V3.16B, V2.16B, #8

  (72) 0x123f0 AND	V7.16B, V2.16B, V23.16B

  (72) 0x123f4 AND	V3.16B, V3.16B, V22.16B

  (72) 0x123f8 ORR	V3.16B, V7.16B, V3.16B

  (72) 0x123fc USHR	V3.2D, V3.2D, #1

  (72) 0x12400 EOR	V3.16B, V3.16B, V5.16B

  (72) 0x12404 AND	V5.16B, V2.16B, V24.16B

  (72) 0x12408 CMEQ	V5.2D, V5.2D, #0

  (72) 0x1240c BCAX	V3.16B, V3.16B, V6.16B, V5.16B

  (72) 0x12410 STP	Q4, Q3, [X11]

  (72) 0x12414 B.NE	123ac

0x12418 B	121a8

/usr/lib/gcc/aarch64-amazon-linux/14/../../../../include/c++/14/bits/random.tcc: 404 - 3368

--------------------------------------------------------------------------------

404:       for (size_t __k = 0; __k < (__n - __m); ++__k)

405:         {

406: 	  _UIntType __y = ((_M_x[__k] & __upper_mask)

407: 			   | (_M_x[__k + 1] & __lower_mask));

408: 	  _M_x[__k] = (_M_x[__k + __m] ^ (__y >> 1)

409: 		       ^ ((__y & 0x01) ? __a : 0));

410:         }

411:

412:       for (size_t __k = (__n - __m); __k < (__n - 1); ++__k)

413: 	{

414: 	  _UIntType __y = ((_M_x[__k] & __upper_mask)

415: 			   | (_M_x[__k + 1] & __lower_mask));

416: 	  _M_x[__k] = (_M_x[__k + (__m - __n)] ^ (__y >> 1)

417: 		       ^ ((__y & 0x01) ? __a : 0));

418: 	}

419:

420:       _UIntType __y = ((_M_x[__n - 1] & __upper_mask)

421: 		       | (_M_x[0] & __lower_mask));

422:       _M_x[__n - 1] = (_M_x[__m - 1] ^ (__y >> 1)

423: 		       ^ ((__y & 0x01) ? __a : 0));

[...]

458:       if (_M_p >= state_size)

459: 	_M_gen_rand();

460:

461:       // Calculate o(x(i)).

462:       result_type __z = _M_x[_M_p++];

463:       __z ^= (__z >> __u) & __d;

464:       __z ^= (__z << __s) & __b;

465:       __z ^= (__z << __t) & __c;

466:       __z ^= (__z >> __l);

[...]

3365:       for (size_t __k = __m; __k != 0; --__k)

3366: 	{

3367: 	  __sum += _RealType(__urng() - __urng.min()) * __tmp;

3368: 	  __tmp *= __r;

Coverage (%)	Name	Module
►100.00+	__libc_start_call_main	libc.so.6
○	__libc_start_main	libc.so.6
○	_start	attention-armclang-native

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	1.82
CQA speedup if FP arith vectorized	2.26
CQA speedup if fully vectorized	1.43
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.09
Bottlenecks
Function	main
Source	random.tcc:404-409,random.tcc:412-412,random.tcc:420-423,random.tcc:458-458,random.tcc:462-466,random.tcc:3365-3368
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	6.38
CQA cycles if no scalar integer	3.50
CQA cycles if FP arith vectorized	2.82
CQA cycles if fully vectorized	4.46
Front-end cycles	6.38
P0 cycles	1.25
P1 cycles	1.25
P2 cycles	5.83
P3 cycles	5.67
P4 cycles	5.75
P5 cycles	5.75
P6 cycles	5.75
P7 cycles	5.75
P8 cycles	1.38
P9 cycles	1.38
P10 cycles	1.38
P11 cycles	1.38
P12 cycles	3.17
P13 cycles	2.83
P14 cycles	3.00
P15 cycles	1.50
P16 cycles	1.50
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	3
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	52.50
Nb uops	51.00
Nb loads	NA
Nb stores	3.00
Nb stack references	7.00
FLOP/cycle	0.47
Nb FLOP add-sub	0.00
Nb FLOP mul	1.00
Nb FLOP fma	1.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	0.41
Bytes prefetched	0.00
Bytes loaded	4.00
Bytes stored	0.00
Stride 0	0.00
Stride 1	0.00
Stride n	1.00
Stride unknown	2.00
Stride indirect	0.00
Vectorization ratio all	3.03
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	0.00
Vectorization ratio add_sub	0.00
Vectorization ratio fma	0.00
Vectorization ratio div_sqrt	NA
Vectorization ratio other	5.26
Vector-efficiency ratio all	45.74
Vector-efficiency ratio load	50.00
Vector-efficiency ratio store	50.00
Vector-efficiency ratio mul	25.00
Vector-efficiency ratio add_sub	50.00
Vector-efficiency ratio fma	25.00
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	48.52

Metric	Value
CQA speedup if no scalar integer	2.44
CQA speedup if FP arith vectorized	2.12
CQA speedup if fully vectorized	1.21
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.11
Bottlenecks	micro-operation queue,
Function	main
Source	random.tcc:404-409,random.tcc:412-412,random.tcc:420-423,random.tcc:458-458,random.tcc:462-466,random.tcc:3365-3368
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	9.75
CQA cycles if no scalar integer	4.00
CQA cycles if FP arith vectorized	4.60
CQA cycles if fully vectorized	8.07
Front-end cycles	9.75
P0 cycles	1.50
P1 cycles	1.50
P2 cycles	8.75
P3 cycles	8.58
P4 cycles	8.67
P5 cycles	8.67
P6 cycles	8.67
P7 cycles	8.67
P8 cycles	2.00
P9 cycles	2.00
P10 cycles	2.00
P11 cycles	2.00
P12 cycles	5.50
P13 cycles	5.17
P14 cycles	5.33
P15 cycles	2.50
P16 cycles	2.50
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	3
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	81.00
Nb uops	78.00
Nb loads	NA
Nb stores	5.00
Nb stack references	13.00
FLOP/cycle	0.31
Nb FLOP add-sub	0.00
Nb FLOP mul	1.00
Nb FLOP fma	1.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	0.82
Bytes prefetched	0.00
Bytes loaded	8.00
Bytes stored	0.00
Stride 0	0.00
Stride 1	0.00
Stride n	1.00
Stride unknown	2.00
Stride indirect	0.00
Vectorization ratio all	6.06
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	0.00
Vectorization ratio add_sub	0.00
Vectorization ratio fma	0.00
Vectorization ratio div_sqrt	NA
Vectorization ratio other	10.53
Vector-efficiency ratio all	53.98
Vector-efficiency ratio load	50.00
Vector-efficiency ratio store	50.00
Vector-efficiency ratio mul	25.00
Vector-efficiency ratio add_sub	50.00
Vector-efficiency ratio fma	25.00
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	59.54

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	2.91
CQA speedup if fully vectorized	3.56
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.03
Bottlenecks	micro-operation queue,
Function	main
Source	random.tcc:404-409,random.tcc:412-412,random.tcc:420-423,random.tcc:458-458,random.tcc:462-466,random.tcc:3365-3368
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	3.00
CQA cycles if no scalar integer	3.00
CQA cycles if FP arith vectorized	1.03
CQA cycles if fully vectorized	0.84
Front-end cycles	3.00
P0 cycles	1.00
P1 cycles	1.00
P2 cycles	2.92
P3 cycles	2.75
P4 cycles	2.83
P5 cycles	2.83
P6 cycles	2.83
P7 cycles	2.83
P8 cycles	0.75
P9 cycles	0.75
P10 cycles	0.75
P11 cycles	0.75
P12 cycles	0.83
P13 cycles	0.50
P14 cycles	0.67
P15 cycles	0.50
P16 cycles	0.50
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	3
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	24.00
Nb uops	24.00
Nb loads	NA
Nb stores	1.00
Nb stack references	1.00
FLOP/cycle	1.00
Nb FLOP add-sub	0.00
Nb FLOP mul	1.00
Nb FLOP fma	1.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	0.00
Bytes prefetched	0.00
Bytes loaded	0.00
Bytes stored	0.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	NA
Vectorization ratio store	0.00
Vectorization ratio mul	0.00
Vectorization ratio add_sub	0.00
Vectorization ratio fma	0.00
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	37.50
Vector-efficiency ratio load	NA
Vector-efficiency ratio store	50.00
Vector-efficiency ratio mul	25.00
Vector-efficiency ratio add_sub	50.00
Vector-efficiency ratio fma	25.00
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	37.50

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	main
Source file and lines	random.tcc:404-3368
Module	attention-armclang-native

The loop is defined in /usr/lib/gcc/aarch64-amazon-linux/14/../../../../include/c++/14/bits/random.tcc:404-423,458-466,3365-3368.

Analyzed code is defined in /usr/lib/gcc/aarch64-amazon-linux/14/../../../../include/c++/14/bits/random.tcc:404-409,412,420-423,458,462-466,3365-3368.

Warnings:
Non-innermost loop: analyzing only self part (ignoring child loops).
The structure of this loop is probably <if then [else] end>.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Vectorization

Your loop is probably not vectorized. Only 45% of vector register length is used (average across all VPU instructions). By vectorizing your loop, you can lower the cost of an iteration from 6.38 to 4.46 cycles (1.43x speedup).

Details

Store and arithmetical VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ffast-math (included in Ofast) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

FMA

Detected 1 FMA (fused multiply-add) operations.

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant unknown stride: 2 occurrence(s)
Constant non-unit stride: 1 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Conversion instructions

Detected expensive conversion instructions.

Details

UCVTF: 0 occurrences

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 3 FP arithmetical operations:

1: addition or subtraction (all inside FMA instructions)
2: multiply (1 inside FMA instructions)

The binary loop is loading 4 bytes.

Arithmetic intensity

Arithmetic intensity is 0.75 FP operations per loaded or stored byte.

General properties

nb instructions	52.50
nb uops	51
loop length	210
used w registers	2
used x registers	6
used b registers	0
used h registers	0
used s registers	4
used d registers	0
used q registers	0
used v registers	0.50
used z registers	1.50
nb stack references	7

Front-end

MACRO FUSION NOT POSSIBLE

micro-operation queue	6.38 cycles
front end	6.38 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	1.25	1.25	5.83	5.67	5.75	5.75	5.75	5.75	1.38	1.38	1.38	1.38	3.17	2.83	3.00	1.50	1.50
cycles	1.25	1.25	5.83	5.67	5.75	5.75	5.75	5.75	1.38	1.38	1.38	1.38	3.17	2.83	3.00	1.50	1.50

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	3.00

Cycles summary

Front-end	6.38
Dispatch	5.83
Data deps.	3.00
Overall L1	6.38

Vectorization ratios

INT

all	3%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	5%

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	0%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

INT+FP

all	3%
load	0%
store	0%
mul	0%
add-sub	0%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	5%

Vector efficiency ratios

INT

all	53%
load	50%
store	50%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	50%
fma	NA (no fma vectorizable/vectorized instructions)
other	55%

all	25%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	25%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	25%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	25%

INT+FP

all	45%
load	50%
store	50%
mul	25%
add-sub	50%
fma	25%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	48%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 6.38 cycles. At this rate:

0% of peak load performance is reached (0.41 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))

Function	main
Source file and lines	random.tcc:404-3368
Module	attention-armclang-native

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 9.75 to 4.00 cycles (2.44x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is probably not vectorized. Only 53% of vector register length is used (average across all VPU instructions). By vectorizing your loop, you can lower the cost of an iteration from 9.75 to 8.07 cycles (1.21x speedup).

Details

Workaround

Try another compiler or update/tune your current one:
- recompile with ffast-math (included in Ofast) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

FMA

Detected 1 FMA (fused multiply-add) operations.

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant unknown stride: 2 occurrence(s)
Constant non-unit stride: 1 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Conversion instructions

Detected expensive conversion instructions.

Details

UCVTF: 1 occurrences►
- /usr/lib/gcc/aarch64-amazon-linux/14/../../../../include/c++/14/bits/random.tcc:3367

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 3 FP arithmetical operations:

1: addition or subtraction (all inside FMA instructions)
2: multiply (1 inside FMA instructions)

The binary loop is loading 8 bytes.

Arithmetic intensity

Arithmetic intensity is 0.37 FP operations per loaded or stored byte.

General properties

nb instructions	81
nb uops	78
loop length	324
used w registers	2
used x registers	7
used b registers	0
used h registers	0
used s registers	4
used d registers	0
used q registers	0
used v registers	1
used z registers	3
nb stack references	13

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	9.75 cycles
front end	9.75 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	1.50	1.50	8.75	8.58	8.67	8.67	8.67	8.67	2.00	2.00	2.00	2.00	5.50	5.17	5.33	2.50	2.50
cycles	1.50	1.50	8.75	8.58	8.67	8.67	8.67	8.67	2.00	2.00	2.00	2.00	5.50	5.17	5.33	2.50	2.50

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	3.00

Cycles summary

Front-end	9.75
Dispatch	8.75
Data deps.	3.00
Overall L1	9.75

Vectorization ratios

INT

all	6%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	11%

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	0%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

INT+FP

all	6%
load	0%
store	0%
mul	0%
add-sub	0%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	10%

Vector efficiency ratios

INT

all	56%
load	50%
store	50%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	50%
fma	NA (no fma vectorizable/vectorized instructions)
other	61%

all	25%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	25%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	25%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	25%

INT+FP

all	53%
load	50%
store	50%
mul	25%
add-sub	50%
fma	25%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	59%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 9.75 cycles. At this rate:

0% of peak load performance is reached (0.82 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 9.75 to 8.75 cycles (1.11x speedup).

ASM code

In the binary file, the address of the loop is: 12234

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
ADD X10, SP, #680	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR X9, [SP, #5664]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ORR X21, XZR, XZR	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
LDR X10, [X10]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
AND X9, X9, #0x0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
AND X11, X10, #0x0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
SBFM X10, X10, #0, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ORR X9, X11, X9	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR X11, [SP, #3848]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
AND X10, X10, X27	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
EOR X9, X11, X9,LSR #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
EOR X9, X9, X10	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STR X9, [SP, #5664]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ORR X9, XZR, X21	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X21, X21, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ADD X10, SP, #680	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUBS X8, X8, #1	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
STR X21, [SP, #5672]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X9, [X10, X9,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
UBFM X10, X9, #11, #42	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
EOR X9, X10, X9	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOVZ W10, #22144	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOVK W10, #40236	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
AND X10, X10, X9,LSL #7	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
EOR X9, X10, X9	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOVZ W10, #61382	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
AND X10, X10, X9,LSL #15	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
EOR X9, X10, X9	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
EOR X9, X9, X9,LSR #18	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
UCVTF S2, X9	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (50.0%)
MOVZ W9, #20352	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
FMADD S0, S2, S1, S0	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25	scal (25.0%)
FMOV S2, W9	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
FMUL S1, S1, S2	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	scal (25.0%)
B.EQ 12420 <main+0x1200>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X21, #624	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.CC 121dc <main+0xfbc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X9, SP, #680	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
DUPM Z22.D, #0x80000000	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
DUPM Z23.D, #0x7ffffffe	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
DUP Z24.D, #1	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (6.3%)
MOVZ W10, #224	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LD1R {V2.2D}, [X9]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	0	0	8	0.33	scal (50.0%)
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
LDR X10, [SP, #2480]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
MOV X9, V2.D[1]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	1	scal (50.0%)
AND X9, X9, #0x0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
AND X11, X10, #0x0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ORR X9, X11, X9	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR X11, [SP, #5648]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
EOR X9, X11, X9,LSR #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SBFM X11, X10, #0, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (100.0%)
AND X11, X11, X27	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
EOR X9, X9, X11	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STR X9, [SP, #2472]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
AND X9, X10, #0x0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR X10, [SP, #2488]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
AND X11, X10, #0x0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ORR X9, X11, X9	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR X11, [SP, #5656]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
EOR X9, X11, X9,LSR #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SBFM X11, X10, #0, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (100.0%)
AND X11, X11, X27	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
EOR X9, X9, X11	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STR X9, [SP, #2480]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
AND X9, X10, #0x0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR X10, [SP, #2496]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
AND X11, X10, #0x0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
DUP V2.2D, X10	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (50.0%)
ORR X9, X11, X9	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR X11, [SP, #5664]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
EOR X9, X11, X9,LSR #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SBFM X11, X10, #0, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (100.0%)
MOVZ W10, #396	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
AND X11, X11, X27	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
EOR X9, X9, X11	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STR X9, [SP, #2488]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X9, SP, #680	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
B 121a8 <main+0xf88>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Function	main
Source file and lines	random.tcc:404-3368
Module	attention-armclang-native

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. Only 37% of vector register length is used (average across all VPU instructions). By vectorizing your loop, you can lower the cost of an iteration from 3.00 to 0.84 cycles (3.56x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ffast-math (included in Ofast) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

FMA

Detected 1 FMA (fused multiply-add) operations.

Conversion instructions

Detected expensive conversion instructions.

Details

UCVTF: 1 occurrences►
- /usr/lib/gcc/aarch64-amazon-linux/14/../../../../include/c++/14/bits/random.tcc:3367

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 3 FP arithmetical operations:

1: addition or subtraction (all inside FMA instructions)
2: multiply (1 inside FMA instructions)

The binary loop does not load or store any data.

General properties

nb instructions	24
nb uops	24
loop length	96
used w registers	2
used x registers	5
used b registers	0
used h registers	0
used s registers	4
used d registers	0
used q registers	0
used v registers	0
used z registers	0
nb stack references	1

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	3.00 cycles
front end	3.00 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	1.00	1.00	2.92	2.75	2.83	2.83	2.83	2.83	0.75	0.75	0.75	0.75	0.83	0.50	0.67	0.50	0.50
cycles	1.00	1.00	2.92	2.75	2.83	2.83	2.83	2.83	0.75	0.75	0.75	0.75	0.83	0.50	0.67	0.50	0.50

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	3.00

Cycles summary

Front-end	3.00
Dispatch	2.92
Data deps.	3.00
Overall L1	3.00

Vectorization ratios

INT

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	0%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

INT+FP

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	0%
mul	0%
add-sub	0%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

INT

all	50%
load	NA (no load vectorizable/vectorized instructions)
store	50%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	50%
fma	NA (no fma vectorizable/vectorized instructions)
other	50%

all	25%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	25%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	25%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	25%

INT+FP

all	37%
load	NA (no load vectorizable/vectorized instructions)
store	50%
mul	25%
add-sub	50%
fma	25%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	37%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 3.00 cycles.

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck).

ASM code

In the binary file, the address of the loop is: 12234

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
ORR X9, XZR, X21	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X21, X21, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X10, SP, #680	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUBS X8, X8, #1	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
STR X21, [SP, #5672]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X9, [X10, X9,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
UBFM X10, X9, #11, #42	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
EOR X9, X10, X9	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOVZ W10, #22144	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOVK W10, #40236	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
AND X10, X10, X9,LSL #7	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
EOR X9, X10, X9	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOVZ W10, #61382	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
AND X10, X10, X9,LSL #15	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
EOR X9, X10, X9	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
EOR X9, X9, X9,LSR #18	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
UCVTF S2, X9	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (50.0%)
MOVZ W9, #20352	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
FMADD S0, S2, S1, S0	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25	scal (25.0%)
FMOV S2, W9	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
FMUL S1, S1, S2	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	scal (25.0%)
B.EQ 12420 <main+0x1200>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X21, #624	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	N/A
B.CC 121dc <main+0xfbc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Report Configuration

Vectorization

Details

Workaround

FMA

Slow data structures access

Details

Workaround

Conversion instructions

Details

Workaround

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Code clean check

Workaround

Vectorization

Details

Workaround

FMA

Slow data structures access

Details

Workaround

Conversion instructions

Details

Workaround

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Workaround

FMA

Conversion instructions

Details

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code