OV - attention-armclang-native - Loop 66 - attention-armclang-native

0x124e0 LDR	X10, [SP, #584]

0x124e4 ADD	W8, W8, #1

0x124e8 ADD	W9, W9, W24

0x124ec CMP	W8, W10

0x124f0 B.EQ	125ac

0x124f4 MUL	W11, W8, W24

0x124f8 ORR	X10, XZR, XZR

0x124fc B	12540

  (67) 0x12500 MOVI	D0, #0

  (67) 0x12504 ADD	W13, W11, W12

  (67) 0x12508 MADD	W12, W12, W24, W10

  (67) 0x1250c LDR	S1, [X19, W13,UXTW #2]

  (67) 0x12510 LDR	S2, [X22, W12,UXTW #2]

  (67) 0x12514 FCVT	D1, S1

  (67) 0x12518 FCVT	D2, S2

  (67) 0x1251c FMADD	D0, D1, D2, D0

  (67) 0x12520 LDR	X13, [SP, #648]

  (67) 0x12524 FCVT	S0, D0

  (67) 0x12528 ADD	W12, W11, W10

  (67) 0x1252c ADD	X10, X10, #1

  (67) 0x12530 STR	S0, [X13, W12,UXTW #2]

  (67) 0x12534 AND	X12, X24, #0x7fffffff

  (67) 0x12538 CMP	X10, X12

  (67) 0x1253c B.EQ	124e0

  (67) 0x12540 LDUR	X12, [X29, #472]

  (67) 0x12544 CBZ	X12, 12500

  (67) 0x12548 MOVI	D0, #0

  (67) 0x1254c AND	X16, X24, #0x0

  (67) 0x12550 ORR	X12, XZR, XZR

  (67) 0x12554 ORR	X13, XZR, X10

  (67) 0x12558 ORR	W14, WZR, W9

  (67) 0x1255c HINT	#0

    (68) 0x12560 SUB	W15, W14, #1

    (68) 0x12564 LDR	S2, [X22, W13,UXTW #2]

    (68) 0x12568 ADD	X12, X12, #2

    (68) 0x1256c LDR	S1, [X19, W15,UXTW #2]

    (68) 0x12570 ADD	W15, W24, W13

    (68) 0x12574 ADD	X13, X13, X20

    (68) 0x12578 FCVT	D2, S2

    (68) 0x1257c FCVT	D1, S1

    (68) 0x12580 FMADD	D0, D1, D2, D0

    (68) 0x12584 LDR	S1, [X19, W14,UXTW #2]

    (68) 0x12588 LDR	S2, [X22, W15,UXTW #2]

    (68) 0x1258c ADD	W14, W14, #2

    (68) 0x12590 FCVT	D1, S1

    (68) 0x12594 FCVT	D2, S2

    (68) 0x12598 FMADD	D0, D1, D2, D0

    (68) 0x1259c CMP	X16, X12

    (68) 0x125a0 B.NE	12560

  (67) 0x125a4 TBNZ	W24, #0, 12504

  (67) 0x125a8 B	12520

/home/eoseret/llm-attention/attention_v2.cpp: 26 - 175

--------------------------------------------------------------------------------

26:    for (unsigned int i = 0; i < M; ++i) {

27:       for (unsigned int j = 0; j < N; ++j) {  //vectorized

28:          double sum = 0.0;

29: #pragma clang loop vectorize(enable)

30:          for (unsigned int k = 0; k < K; ++k) { //vectorized

31:             sum += (double)A[i * K + k] * (double)B[k * N + j];

32:          }

33:          C[i * N + j] = alpha * static_cast<float>(sum);

[...]

175:       start = std::chrono::steady_clock::now();

Coverage (%)	Name	Module
►100.00+	__libc_start_call_main	libc.so.6
○	__libc_start_main	libc.so.6
○	_start	attention-armclang-native

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	4.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.20
Bottlenecks	micro-operation queue, P0, P1,
Function	main
Source	attention_v2.cpp:26-26,attention_v2.cpp:175-175
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	1.00
CQA cycles if no scalar integer	1.00
CQA cycles if FP arith vectorized	1.00
CQA cycles if fully vectorized	0.25
Front-end cycles	1.00
P0 cycles	1.00
P1 cycles	1.00
P2 cycles	0.83
P3 cycles	0.83
P4 cycles	0.83
P5 cycles	0.83
P6 cycles	0.83
P7 cycles	0.83
P8 cycles	0.00
P9 cycles	0.00
P10 cycles	0.00
P11 cycles	0.00
P12 cycles	0.33
P13 cycles	0.33
P14 cycles	0.33
P15 cycles	0.00
P16 cycles	0.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	8.00
Nb uops	8.00
Nb loads	NA
Nb stores	0.00
Nb stack references	1.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	0.00
Bytes prefetched	0.00
Bytes loaded	0.00
Bytes stored	0.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	NA
Vectorization ratio store	NA
Vectorization ratio mul	0.00
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	NA
Vector-efficiency ratio all	25.00
Vector-efficiency ratio load	NA
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	25.00
Vector-efficiency ratio add_sub	25.00
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	NA

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	4.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.20
Bottlenecks	micro-operation queue, P0, P1,
Function	main
Source	attention_v2.cpp:26-26,attention_v2.cpp:175-175
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	1.00
CQA cycles if no scalar integer	1.00
CQA cycles if FP arith vectorized	1.00
CQA cycles if fully vectorized	0.25
Front-end cycles	1.00
P0 cycles	1.00
P1 cycles	1.00
P2 cycles	0.83
P3 cycles	0.83
P4 cycles	0.83
P5 cycles	0.83
P6 cycles	0.83
P7 cycles	0.83
P8 cycles	0.00
P9 cycles	0.00
P10 cycles	0.00
P11 cycles	0.00
P12 cycles	0.33
P13 cycles	0.33
P14 cycles	0.33
P15 cycles	0.00
P16 cycles	0.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	8.00
Nb uops	8.00
Nb loads	NA
Nb stores	0.00
Nb stack references	1.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	0.00
Bytes prefetched	0.00
Bytes loaded	0.00
Bytes stored	0.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	NA
Vectorization ratio store	NA
Vectorization ratio mul	0.00
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	NA
Vector-efficiency ratio all	25.00
Vector-efficiency ratio load	NA
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	25.00
Vector-efficiency ratio add_sub	25.00
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	NA

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	main
Source file and lines	attention_v2.cpp:26-175
Module	attention-armclang-native

The loop is defined in /home/eoseret/llm-attention/attention_v2.cpp:26-33,175.

Analyzed code is defined in /home/eoseret/llm-attention/attention_v2.cpp:26,175.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Failed to get the number of paths
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. 4 data elements could be processed at once in vector registers. By vectorizing your loop, you can lower the cost of an iteration from 1.00 to 0.25 cycles (4.00x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ffast-math (included in Ofast) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop does not load or store any data.

General properties

nb instructions	8
nb uops	8
loop length	32
used w registers	5
used x registers	2
used b registers	0
used h registers	0
used s registers	1
used d registers	0
used q registers	0
used v registers	0
used z registers	0
nb stack references	1

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	1.00 cycles
front end	1.00 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	1.00	1.00	0.83	0.83	0.83	0.83	0.83	0.83	0.00	0.00	0.00	0.00	0.33	0.33	0.33	0.00	0.00
cycles	1.00	1.00	0.83	0.83	0.83	0.83	0.83	0.83	0.00	0.00	0.00	0.00	0.33	0.33	0.33	0.00	0.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

NA

Cycles summary

Front-end	1.00
Dispatch	1.00
Overall L1	1.00

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

Vector efficiency ratios

all	25%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	25%
add-sub	25%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 1.00 cycles.

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 1.00 to 0.83 cycles (1.20x speedup).

ASM code

In the binary file, the address of the loop is: 124f4

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P12	P13	P14	Latency	Recip. throughput	Vectorization
LDR X10, [SP, #584]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
ADD W8, W8, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	1	0.17	N/A
ADD W9, W9, W24	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	1	0.17	scal (25.0%)
CMP W8, W10	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	1	0.33	N/A
B.EQ 125ac <main+0x138c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MUL W11, W8, W24	1	0	0	0	0	0	0	0.50	0.50	0	0	0	2	0.50	scal (25.0%)
ORR X10, XZR, XZR	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	1	0.17	N/A
B 12540 <main+0x1320>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Function	main
Source file and lines	attention_v2.cpp:26-175
Module	attention-armclang-native

The loop is defined in /home/eoseret/llm-attention/attention_v2.cpp:26-33,175.

Analyzed code is defined in /home/eoseret/llm-attention/attention_v2.cpp:26,175.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Failed to get the number of paths
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. 4 data elements could be processed at once in vector registers. By vectorizing your loop, you can lower the cost of an iteration from 1.00 to 0.25 cycles (4.00x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ffast-math (included in Ofast) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop does not load or store any data.

General properties

nb instructions	8
nb uops	8
loop length	32
used w registers	5
used x registers	2
used b registers	0
used h registers	0
used s registers	1
used d registers	0
used q registers	0
used v registers	0
used z registers	0
nb stack references	1

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	1.00 cycles
front end	1.00 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	1.00	1.00	0.83	0.83	0.83	0.83	0.83	0.83	0.00	0.00	0.00	0.00	0.33	0.33	0.33	0.00	0.00
cycles	1.00	1.00	0.83	0.83	0.83	0.83	0.83	0.83	0.00	0.00	0.00	0.00	0.33	0.33	0.33	0.00	0.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

NA

Cycles summary

Front-end	1.00
Dispatch	1.00
Overall L1	1.00

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

Vector efficiency ratios

all	25%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	25%
add-sub	25%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 1.00 cycles.

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 1.00 to 0.83 cycles (1.20x speedup).

ASM code

In the binary file, the address of the loop is: 124f4

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P12	P13	P14	Latency	Recip. throughput	Vectorization
LDR X10, [SP, #584]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
ADD W8, W8, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	1	0.17	N/A
ADD W9, W9, W24	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	1	0.17	scal (25.0%)
CMP W8, W10	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	1	0.33	N/A
B.EQ 125ac <main+0x138c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MUL W11, W8, W24	1	0	0	0	0	0	0	0.50	0.50	0	0	0	2	0.50	scal (25.0%)
ORR X10, XZR, XZR	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	1	0.17	N/A
B 12540 <main+0x1320>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Report Configuration

Vectorization

Details

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code