OV - attention-armclang-native - Loop 61 - attention-armclang-native

	Loop Id: 61	Module: attention-armclang-native	Source: attention_v2.cpp:26-33	Coverage: 0.37%

0x12740 MOVI	D0, #0

0x12744 ADD	W13, W11, W12

0x12748 MADD	W12, W12, W24, W10

0x1274c LDR	S1, [X19, W13,UXTW #2]

0x12750 LDR	S2, [X21, W12,UXTW #2]

0x12754 FCVT	D1, S1

0x12758 FCVT	D2, S2

0x1275c FMADD	D0, D1, D2, D0

0x12760 FCVT	S0, D0

0x12764 ADD	W12, W11, W10

0x12768 ADD	X10, X10, #1

0x1276c STR	S0, [X26, W12,UXTW #2]

0x12770 AND	X12, X24, #0x7fffffff

0x12774 CMP	X10, X12

0x12778 B.EQ	12720

0x1277c LDUR	X12, [X29, #472]

0x12780 CBZ	X12, 12740

0x12784 MOVI	D0, #0

0x12788 AND	X16, X24, #0x0

0x1278c ORR	X12, XZR, XZR

0x12790 ORR	X13, XZR, X10

0x12794 ORR	W14, WZR, W9

0x12798 HINT	#0

0x1279c HINT	#0

  (62) 0x127a0 SUB	W15, W14, #1

  (62) 0x127a4 LDR	S2, [X21, W13,UXTW #2]

  (62) 0x127a8 ADD	X12, X12, #2

  (62) 0x127ac LDR	S1, [X19, W15,UXTW #2]

  (62) 0x127b0 ADD	W15, W24, W13

  (62) 0x127b4 ADD	X13, X13, X20

  (62) 0x127b8 FCVT	D2, S2

  (62) 0x127bc FCVT	D1, S1

  (62) 0x127c0 FMADD	D0, D1, D2, D0

  (62) 0x127c4 LDR	S1, [X19, W14,UXTW #2]

  (62) 0x127c8 LDR	S2, [X21, W15,UXTW #2]

  (62) 0x127cc ADD	W14, W14, #2

  (62) 0x127d0 FCVT	D1, S1

  (62) 0x127d4 FCVT	D2, S2

  (62) 0x127d8 FMADD	D0, D1, D2, D0

  (62) 0x127dc CMP	X16, X12

  (62) 0x127e0 B.NE	127a0

0x127e4 TBNZ	W24, #0, 12744

0x127e8 B	12760

/home/eoseret/llm-attention/attention_v2.cpp: 26 - 33

--------------------------------------------------------------------------------

26:    for (unsigned int i = 0; i < M; ++i) {

27:       for (unsigned int j = 0; j < N; ++j) {  //vectorized

28:          double sum = 0.0;

29: #pragma clang loop vectorize(enable)

30:          for (unsigned int k = 0; k < K; ++k) { //vectorized

31:             sum += (double)A[i * K + k] * (double)B[k * N + j];

32:          }

33:          C[i * N + j] = alpha * static_cast<float>(sum);

Coverage (%)	Name	Module
►100.00+	__libc_start_call_main	libc.so.6
○	__libc_start_main	libc.so.6
○	_start	attention-armclang-native

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	1.72
CQA speedup if FP arith vectorized	1.29
CQA speedup if fully vectorized	3.52
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.47
Bottlenecks
Function	main
Source	attention_v2.cpp:26-27,attention_v2.cpp:30-33
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	2.29
CQA cycles if no scalar integer	1.33
CQA cycles if FP arith vectorized	1.78
CQA cycles if fully vectorized	0.65
Front-end cycles	2.29
P0 cycles	1.50
P1 cycles	1.50
P2 cycles	1.36
P3 cycles	1.42
P4 cycles	1.33
P5 cycles	1.33
P6 cycles	1.31
P7 cycles	1.25
P8 cycles	1.33
P9 cycles	1.25
P10 cycles	1.25
P11 cycles	1.17
P12 cycles	1.28
P13 cycles	0.94
P14 cycles	1.11
P15 cycles	0.00
P16 cycles	0.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	19.67
Nb uops	18.33
Nb loads	NA
Nb stores	1.00
Nb stack references	0.00
FLOP/cycle	0.58
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.67
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	3.00
Bytes prefetched	0.00
Bytes loaded	4.00
Bytes stored	3.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	0.00
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	37.01
Vector-efficiency ratio load	25.00
Vector-efficiency ratio store	25.00
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	50.00
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	40.00

Metric	Value
CQA speedup if no scalar integer	1.42
CQA speedup if FP arith vectorized	1.42
CQA speedup if fully vectorized	3.58
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.42
Bottlenecks	micro-operation queue,
Function	main
Source	attention_v2.cpp:26-27,attention_v2.cpp:30-33
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	2.13
CQA cycles if no scalar integer	1.50
CQA cycles if FP arith vectorized	1.50
CQA cycles if fully vectorized	0.59
Front-end cycles	2.13
P0 cycles	1.00
P1 cycles	1.00
P2 cycles	1.00
P3 cycles	1.08
P4 cycles	1.00
P5 cycles	1.00
P6 cycles	1.00
P7 cycles	0.92
P8 cycles	1.50
P9 cycles	1.50
P10 cycles	1.50
P11 cycles	1.50
P12 cycles	1.50
P13 cycles	1.17
P14 cycles	1.33
P15 cycles	0.00
P16 cycles	0.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	17.00
Nb uops	17.00
Nb loads	NA
Nb stores	1.00
Nb stack references	0.00
FLOP/cycle	0.94
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	1.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	4.24
Bytes prefetched	0.00
Bytes loaded	6.00
Bytes stored	3.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	0.00
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	34.38
Vector-efficiency ratio load	25.00
Vector-efficiency ratio store	25.00
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	50.00
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	37.50

Metric	Value
CQA speedup if no scalar integer	2.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	3.43
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.41
Bottlenecks	micro-operation queue, P0, P1,
Function	main
Source	attention_v2.cpp:26-27,attention_v2.cpp:30-33
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	2.00
CQA cycles if no scalar integer	1.00
CQA cycles if FP arith vectorized	2.00
CQA cycles if fully vectorized	0.58
Front-end cycles	2.00
P0 cycles	2.00
P1 cycles	2.00
P2 cycles	1.42
P3 cycles	1.42
P4 cycles	1.33
P5 cycles	1.33
P6 cycles	1.25
P7 cycles	1.25
P8 cycles	1.00
P9 cycles	0.75
P10 cycles	0.75
P11 cycles	0.50
P12 cycles	0.83
P13 cycles	0.50
P14 cycles	0.67
P15 cycles	0.00
P16 cycles	0.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	18.00
Nb uops	16.00
Nb loads	NA
Nb stores	1.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	1.50
Bytes prefetched	0.00
Bytes loaded	0.00
Bytes stored	3.00
Stride 0	0.00
Stride 1	0.00
Stride n	0.00
Stride unknown	1.00
Stride indirect	1.00
Vectorization ratio all	0.00
Vectorization ratio load	NA
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	41.67
Vector-efficiency ratio load	NA
Vector-efficiency ratio store	25.00
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	45.00

Metric	Value
CQA speedup if no scalar integer	1.83
CQA speedup if FP arith vectorized	1.50
CQA speedup if fully vectorized	3.56
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.57
Bottlenecks	micro-operation queue,
Function	main
Source	attention_v2.cpp:26-27,attention_v2.cpp:30-33
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	2.75
CQA cycles if no scalar integer	1.50
CQA cycles if FP arith vectorized	1.83
CQA cycles if fully vectorized	0.77
Front-end cycles	2.75
P0 cycles	1.50
P1 cycles	1.50
P2 cycles	1.67
P3 cycles	1.75
P4 cycles	1.67
P5 cycles	1.67
P6 cycles	1.67
P7 cycles	1.58
P8 cycles	1.50
P9 cycles	1.50
P10 cycles	1.50
P11 cycles	1.50
P12 cycles	1.50
P13 cycles	1.17
P14 cycles	1.33
P15 cycles	0.00
P16 cycles	0.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	24.00
Nb uops	22.00
Nb loads	NA
Nb stores	1.00
Nb stack references	0.00
FLOP/cycle	0.73
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	1.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	3.27
Bytes prefetched	0.00
Bytes loaded	6.00
Bytes stored	3.00
Stride 0	0.00
Stride 1	0.00
Stride n	0.00
Stride unknown	1.00
Stride indirect	1.00
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	0.00
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	35.00
Vector-efficiency ratio load	25.00
Vector-efficiency ratio store	25.00
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	50.00
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	37.50

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	main
Source file and lines	attention_v2.cpp:26-33
Module	attention-armclang-native

The loop is defined in /home/eoseret/llm-attention/attention_v2.cpp:26-33.

Analyzed code is defined in /home/eoseret/llm-attention/attention_v2.cpp:26-27,30-33.

Warnings:
Non-innermost loop: analyzing only self part (ignoring child loops).
This loop has 3 execution paths.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. Only 37% of vector register length is used (average across all VPU instructions). By vectorizing your loop, you can lower the cost of an iteration from 2.29 to 0.65 cycles (3.52x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ffast-math (included in Ofast) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

FMA

Detected 0.67 FMA (fused multiply-add) operations.

Conversion instructions

Detected expensive conversion instructions.

Details

FCVT: 0 occurrences

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 1.3333333333333 FP arithmetical operations:

0.67: addition or subtraction (all inside FMA instructions)
0.67: multiply (all inside FMA instructions)

The binary loop is loading 4 bytes. The binary loop is storing 3 bytes.

Arithmetic intensity

Arithmetic intensity is 0.19 FP operations per loaded or stored byte.

General properties

nb instructions	19.67
nb uops	18.33
loop length	78.67
used w registers	6.67
used x registers	8.33
used b registers	0
used h registers	0
used s registers	2.33
used d registers	2.33
used q registers	0
used v registers	0
used z registers	0
nb stack references	0

Front-end

MACRO FUSION NOT POSSIBLE

micro-operation queue	2.29 cycles
front end	2.29 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	1.50	1.50	1.36	1.42	1.33	1.33	1.31	1.25	1.33	1.25	1.25	1.17	1.28	0.94	1.11	0.00	0.00
cycles	1.50	1.50	1.36	1.42	1.33	1.33	1.31	1.25	1.33	1.25	1.25	1.17	1.28	0.94	1.11	0.00	0.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	2.29
Dispatch	1.75
Data deps.	1.00
Overall L1	2.29

Vectorization ratios

INT

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

INT+FP

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

INT

all	34%
load	25%
store	25%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	45%

all	41%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	50%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	38%

INT+FP

all	37%
load	25%
store	25%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	50%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	40%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 2.29 cycles. At this rate:

1% of peak load performance is reached (1.67 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
2% of peak store performance is reached (1.33 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

Function	main
Source file and lines	attention_v2.cpp:26-33
Module	attention-armclang-native

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 2.13 to 1.50 cycles (1.42x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is not vectorized. Only 34% of vector register length is used (average across all VPU instructions). By vectorizing your loop, you can lower the cost of an iteration from 2.13 to 0.59 cycles (3.58x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ffast-math (included in Ofast) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

FMA

Detected 1 FMA (fused multiply-add) operations.

Conversion instructions

Detected expensive conversion instructions.

Details

FCVT: 3 occurrences►
- /home/eoseret/llm-attention/attention_v2.cpp:31
- /home/eoseret/llm-attention/attention_v2.cpp:31
- /home/eoseret/llm-attention/attention_v2.cpp:33

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 2 FP arithmetical operations:

1: addition or subtraction (all inside FMA instructions)
1: multiply (all inside FMA instructions)

The binary loop is loading 6 bytes. The binary loop is storing 3 bytes.

Arithmetic intensity

Arithmetic intensity is 0.22 FP operations per loaded or stored byte.

General properties

nb instructions	17
nb uops	17
loop length	68
used w registers	5
used x registers	7
used b registers	0
used h registers	0
used s registers	3
used d registers	3
used q registers	0
used v registers	0
used z registers	0
nb stack references	0

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	2.13 cycles
front end	2.13 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	1.00	1.00	1.00	1.08	1.00	1.00	1.00	0.92	1.50	1.50	1.50	1.50	1.50	1.17	1.33	0.00	0.00
cycles	1.00	1.00	1.00	1.08	1.00	1.00	1.00	0.92	1.50	1.50	1.50	1.50	1.50	1.17	1.33	0.00	0.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	2.13
Dispatch	1.50
Data deps.	1.00
Overall L1	2.13

Vectorization ratios

INT

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

INT+FP

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

INT

all	31%
load	25%
store	25%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	50%

all	37%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	50%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	33%

INT+FP

all	34%
load	25%
store	25%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	50%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	37%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 2.13 cycles. At this rate:

2% of peak load performance is reached (2.82 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
2% of peak store performance is reached (1.41 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 2.13 to 1.50 cycles (1.42x speedup).

ASM code

In the binary file, the address of the loop is: 1277c

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput	Vectorization
MOVI D0, #0	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (50.0%)
ADD W13, W11, W12	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
MADD W12, W12, W24, W10	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	N/A
LDR S1, [X19, W13,UXTW #2]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
LDR S2, [X21, W12,UXTW #2]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
FCVT D1, S1	1	0	0	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	3	0.50	scal (25.0%)
FCVT D2, S2	1	0	0	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	3	0.50	scal (25.0%)
FMADD D0, D1, D2, D0	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	scal (50.0%)
FCVT S0, D0	1	0	0	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	3	0.50	scal (50.0%)
ADD W12, W11, W10	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
ADD X10, X10, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
STR S0, [X26, W12,UXTW #2]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	scal (25.0%)
AND X12, X24, #0x7fffffff	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
CMP X10, X12	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	1	0.33	N/A
B.EQ 12720 <main+0x1500>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDUR X12, [X29, #472]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
CBZ X12, 12740 <main+0x1520>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Function	main
Source file and lines	attention_v2.cpp:26-33
Module	attention-armclang-native

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 2.00 to 1.00 cycles (2.00x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is not vectorized. Only 41% of vector register length is used (average across all VPU instructions). By vectorizing your loop, you can lower the cost of an iteration from 2.00 to 0.58 cycles (3.43x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ffast-math (included in Ofast) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant unknown stride: 1 occurrence(s)
Irregular (variable stride) or indirect: 1 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)
Try to remove indirect accesses. If applicable, precompute elements out of the innermost loop.

Conversion instructions

Detected expensive conversion instructions.

Details

FCVT: 1 occurrences►
- /home/eoseret/llm-attention/attention_v2.cpp:33

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is storing 3 bytes.

General properties

nb instructions	18
nb uops	16
loop length	72
used w registers	7
used x registers	8
used b registers	0
used h registers	0
used s registers	1
used d registers	1
used q registers	0
used v registers	0
used z registers	0
nb stack references	0

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	2.00 cycles
front end	2.00 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	2.00	2.00	1.42	1.42	1.33	1.33	1.25	1.25	1.00	0.75	0.75	0.50	0.83	0.50	0.67	0.00	0.00
cycles	2.00	2.00	1.42	1.42	1.33	1.33	1.25	1.25	1.00	0.75	0.75	0.50	0.83	0.50	0.67	0.00	0.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	2.00
Dispatch	2.00
Data deps.	1.00
Overall L1	2.00

Vectorization ratios

INT

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

INT+FP

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

INT

all	40%
load	NA (no load vectorizable/vectorized instructions)
store	25%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	43%

all	50%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	50%

INT+FP

all	41%
load	NA (no load vectorizable/vectorized instructions)
store	25%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	45%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 2.00 cycles. At this rate:

3% of peak store performance is reached (1.50 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the loop is: 1277c

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
FCVT S0, D0	1	0	0	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	0	0	3	0.50	scal (50.0%)
ADD W12, W11, W10	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X10, X10, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STR S0, [X26, W12,UXTW #2]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (25.0%)
AND X12, X24, #0x7fffffff	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP X10, X12	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	N/A
B.EQ 12720 <main+0x1500>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDUR X12, [X29, #472]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CBZ X12, 12740 <main+0x1520>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVI D0, #0	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
AND X16, X24, #0x0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ORR X12, XZR, XZR	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ORR X13, XZR, X10	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ORR W14, WZR, W9	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
HINT #0																					N/A
HINT #0																					N/A
TBNZ W24, #0, 12744 <main+0x1524>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
B 12760 <main+0x1540>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Function	main
Source file and lines	attention_v2.cpp:26-33
Module	attention-armclang-native

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 2.75 to 1.50 cycles (1.83x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is not vectorized. Only 35% of vector register length is used (average across all VPU instructions). By vectorizing your loop, you can lower the cost of an iteration from 2.75 to 0.77 cycles (3.56x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ffast-math (included in Ofast) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

FMA

Detected 1 FMA (fused multiply-add) operations.

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant unknown stride: 1 occurrence(s)
Irregular (variable stride) or indirect: 1 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)
Try to remove indirect accesses. If applicable, precompute elements out of the innermost loop.

Conversion instructions

Detected expensive conversion instructions.

Details

FCVT: 3 occurrences►
- /home/eoseret/llm-attention/attention_v2.cpp:31
- /home/eoseret/llm-attention/attention_v2.cpp:31
- /home/eoseret/llm-attention/attention_v2.cpp:33

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 2 FP arithmetical operations:

1: addition or subtraction (all inside FMA instructions)
1: multiply (all inside FMA instructions)

The binary loop is loading 6 bytes. The binary loop is storing 3 bytes.

Arithmetic intensity

Arithmetic intensity is 0.22 FP operations per loaded or stored byte.

General properties

nb instructions	24
nb uops	22
loop length	96
used w registers	8
used x registers	10
used b registers	0
used h registers	0
used s registers	3
used d registers	3
used q registers	0
used v registers	0
used z registers	0
nb stack references	0

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	2.75 cycles
front end	2.75 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	1.50	1.50	1.67	1.75	1.67	1.67	1.67	1.58	1.50	1.50	1.50	1.50	1.50	1.17	1.33	0.00	0.00
cycles	1.50	1.50	1.67	1.75	1.67	1.67	1.67	1.58	1.50	1.50	1.50	1.50	1.50	1.17	1.33	0.00	0.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	2.75
Dispatch	1.75
Data deps.	1.00
Overall L1	2.75

Vectorization ratios

INT

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

INT+FP

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

INT

all	33%
load	25%
store	25%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	41%

all	37%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	50%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	33%

INT+FP

all	35%
load	25%
store	25%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	50%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	37%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 2.75 cycles. At this rate:

2% of peak load performance is reached (2.18 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
2% of peak store performance is reached (1.09 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the loop is: 1277c

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
ADD W13, W11, W12	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MADD W12, W12, W24, W10	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
LDR S1, [X19, W13,UXTW #2]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
LDR S2, [X21, W12,UXTW #2]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
FCVT D1, S1	1	0	0	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	0	0	3	0.50	scal (25.0%)
FCVT D2, S2	1	0	0	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	0	0	3	0.50	scal (25.0%)
FMADD D0, D1, D2, D0	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25	scal (50.0%)
FCVT S0, D0	1	0	0	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	0	0	3	0.50	scal (50.0%)
ADD W12, W11, W10	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X10, X10, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STR S0, [X26, W12,UXTW #2]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (25.0%)
AND X12, X24, #0x7fffffff	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP X10, X12	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	N/A
B.EQ 12720 <main+0x1500>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDUR X12, [X29, #472]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CBZ X12, 12740 <main+0x1520>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVI D0, #0	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
AND X16, X24, #0x0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ORR X12, XZR, XZR	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ORR X13, XZR, X10	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ORR W14, WZR, W9	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
HINT #0																					N/A
HINT #0																					N/A
TBNZ W24, #0, 12744 <main+0x1524>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Report Configuration

Vectorization

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Workaround

FMA

Conversion instructions

Details

Workaround

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Code clean check

Workaround

Vectorization

Details

Workaround

FMA

Conversion instructions

Details

Workaround

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Slow data structures access

Details

Workaround

Conversion instructions

Details

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

FMA

Slow data structures access

Details

Workaround

Conversion instructions

Details

Workaround

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks