OV - attention-armclang-native - Loop 52 - attention-armclang-native

0x129e8 ADD	W9, W9, #1

0x129ec ADD	W8, W8, W24

0x129f0 CMP	W9, W21

0x129f4 B.EQ	12ca4

0x129f8 LDUR	X13, [X29, #472]

0x129fc MUL	W11, W9, W24

0x12a00 MUL	W12, W9, W21

0x12a04 ORR	X10, XZR, XZR

0x12a08 CMN	W11, W13

0x12a0c LDR	W13, [SP, #388]

0x12a10 CSINC	W13, W13, WZR, #3

0x12a14 B	12a44

  (53) 0x12a20 FCVT	S0, D0

  (53) 0x12a24 LDR	X15, [SP, #576]

  (53) 0x12a28 ADD	W14, W12, W10

  (53) 0x12a2c ADD	X10, X10, #1

  (53) 0x12a30 FDIV	S0, S0, S9

  (53) 0x12a34 STR	S0, [X15, W14,UXTW #2]

  (53) 0x12a38 LDR	X14, [SP, #656]

  (53) 0x12a3c CMP	X10, X14

  (53) 0x12a40 B.EQ	129e8

  (53) 0x12a44 MOVI	D0, #0

  (53) 0x12a48 AND	X14, X24, #0x7fffffff

  (53) 0x12a4c CMP	X14, #4

  (53) 0x12a50 B.CC	12a64

  (53) 0x12a54 LDUR	X14, [X29, #472]

  (53) 0x12a58 CMN	W10, W14

  (53) 0x12a5c CSINC	W14, W13, WZR, #3

  (53) 0x12a60 TBZ	W14, #0, 12b08

  (53) 0x12a64 ORR	X14, XZR, XZR

  (53) 0x12a68 ORR	X15, X14, #0x1

  (53) 0x12a6c TBZ	W24, #0, 12a94

  (53) 0x12a70 LDR	X17, [SP, #648]

  (53) 0x12a74 ADD	W16, W11, W14

  (53) 0x12a78 MADD	W14, W14, W21, W10

  (53) 0x12a7c LDR	S2, [X28, W14,UXTW #2]

  (53) 0x12a80 ORR	X14, XZR, X15

  (53) 0x12a84 LDR	S1, [X17, W16,UXTW #2]

  (53) 0x12a88 FCVT	D2, S2

  (53) 0x12a8c FCVT	D1, S1

  (53) 0x12a90 FMADD	D0, D1, D2, D0

  (53) 0x12a94 LDR	X0, [SP, #648]

  (53) 0x12a98 LDR	X1, [SP, #552]

  (53) 0x12a9c AND	X16, X24, #0x7fffffff

  (53) 0x12aa0 CMP	X16, X15

  (53) 0x12aa4 B.EQ	12a20

  (53) 0x12aa8 MUL	X17, X21, X14

  (53) 0x12aac AND	X15, X24, #0x7fffffff

  (53) 0x12ab0 ADD	X18, X10, X21

  (53) 0x12ab4 SUB	X15, X15, X14

  (53) 0x12ab8 ADD	W14, W8, W14

  (53) 0x12abc ADD	X16, X10, X17

  (53) 0x12ac0 ADD	X17, X18, X17

    (54) 0x12ac4 LDR	S1, [X0, W14,UXTW #2]

    (54) 0x12ac8 LDR	S2, [X28, W16,UXTW #2]

    (54) 0x12acc ADD	W18, W14, #1

    (54) 0x12ad0 SUBS	X15, X15, #2

    (54) 0x12ad4 ADD	X16, X16, X1

    (54) 0x12ad8 ADD	W14, W14, #2

    (54) 0x12adc FCVT	D1, S1

    (54) 0x12ae0 FCVT	D2, S2

    (54) 0x12ae4 FMADD	D0, D1, D2, D0

    (54) 0x12ae8 LDR	S1, [X0, W18,UXTW #2]

    (54) 0x12aec LDR	S2, [X28, W17,UXTW #2]

    (54) 0x12af0 ADD	X17, X17, X1

    (54) 0x12af4 FCVT	D1, S1

    (54) 0x12af8 FCVT	D2, S2

    (54) 0x12afc FMADD	D0, D1, D2, D0

    (54) 0x12b00 B.NE	12ac4

  (53) 0x12b04 B	12a20

  (53) 0x12b08 AND	X14, X24, #0x7fffffff

  (53) 0x12b0c CMP	X14, #16

  (53) 0x12b10 B.CS	12b24

  (53) 0x12b14 LDR	X18, [SP, #648]

  (53) 0x12b18 ORR	X16, XZR, XZR

  (53) 0x12b1c MOVI	D0, #0

  (53) 0x12b20 B	12c2c

  (53) 0x12b24 LDR	X18, [SP, #648]

  (53) 0x12b28 AND	X16, X24, #0x0

  (53) 0x12b2c MOVI	V0.2D, #0

  (53) 0x12b30 ORR	W14, WZR, W8

  (53) 0x12b34 ORR	X15, XZR, X10

  (53) 0x12b38 MOVI	V1.2D, #0

  (53) 0x12b3c MOVI	V2.2D, #0

  (53) 0x12b40 MOVI	V4.2D, #0

  (53) 0x12b44 MOVI	V5.2D, #0

  (53) 0x12b48 MOVI	V6.2D, #0

  (53) 0x12b4c MOVI	V3.2D, #0

  (53) 0x12b50 MOVI	V7.2D, #0

  (53) 0x12b54 HINT	#0

  (53) 0x12b58 HINT	#0

  (53) 0x12b5c HINT	#0

    (55) 0x12b60 ADD	X17, X18, W14,UXTW #2

    (55) 0x12b64 SUBS	X16, X16, #16

    (55) 0x12b68 ADD	W14, W14, #16

    (55) 0x12b6c LDP	Q16, Q17, [X17]

    (55) 0x12b70 LDP	Q18, Q19, [X17, #32]

    (55) 0x12b74 ADD	X17, X28, W15,UXTW #2

    (55) 0x12b78 ADD	X15, X15, #16

    (55) 0x12b7c FCVTL	V21.2D, V17.2S

    (55) 0x12b80 LDP	Q24, Q25, [X17]

    (55) 0x12b84 LDP	Q26, Q27, [X17, #32]

    (55) 0x12b88 FCVTL2	V17.2D, V17.4S

    (55) 0x12b8c FCVTL	V23.2D, V19.2S

    (55) 0x12b90 FCVTL2	V19.2D, V19.4S

    (55) 0x12b94 FCVTL	V20.2D, V16.2S

    (55) 0x12b98 FCVTL2	V16.2D, V16.4S

    (55) 0x12b9c FCVTL	V22.2D, V18.2S

    (55) 0x12ba0 FCVTL2	V18.2D, V18.4S

    (55) 0x12ba4 FCVTL	V29.2D, V25.2S

    (55) 0x12ba8 FCVTL2	V25.2D, V25.4S

    (55) 0x12bac FCVTL	V31.2D, V27.2S

    (55) 0x12bb0 FCVTL2	V27.2D, V27.4S

    (55) 0x12bb4 FCVTL	V28.2D, V24.2S

    (55) 0x12bb8 FCVTL2	V24.2D, V24.4S

    (55) 0x12bbc FCVTL	V30.2D, V26.2S

    (55) 0x12bc0 FCVTL2	V26.2D, V26.4S

    (55) 0x12bc4 FMLA	V5.2D, V25.2D, V17.2D

    (55) 0x12bc8 FMLA	V4.2D, V29.2D, V21.2D

    (55) 0x12bcc FMLA	V0.2D, V27.2D, V19.2D

    (55) 0x12bd0 FMLA	V7.2D, V31.2D, V23.2D

    (55) 0x12bd4 FMLA	V2.2D, V24.2D, V16.2D

    (55) 0x12bd8 FMLA	V1.2D, V28.2D, V20.2D

    (55) 0x12bdc FMLA	V3.2D, V26.2D, V18.2D

    (55) 0x12be0 FMLA	V6.2D, V30.2D, V22.2D

    (55) 0x12be4 B.NE	12b60

  (53) 0x12be8 FADD	V1.2D, V4.2D, V1.2D

  (53) 0x12bec FADD	V2.2D, V5.2D, V2.2D

  (53) 0x12bf0 FADD	V4.2D, V7.2D, V6.2D

  (53) 0x12bf4 FADD	V0.2D, V0.2D, V3.2D

  (53) 0x12bf8 AND	X14, X24, #0x7fffffff

  (53) 0x12bfc AND	X15, X24, #0x0

  (53) 0x12c00 FADD	V1.2D, V4.2D, V1.2D

  (53) 0x12c04 FADD	V0.2D, V0.2D, V2.2D

  (53) 0x12c08 FADD	V0.2D, V1.2D, V0.2D

  (53) 0x12c0c FADDP	D0, V0.2D

  (53) 0x12c10 CMP	X14, X15

  (53) 0x12c14 B.EQ	12a20

  (53) 0x12c18 LDR	X18, [SP, #648]

  (53) 0x12c1c AND	X16, X24, #0x0

  (53) 0x12c20 AND	X14, X24, #0x0

  (53) 0x12c24 AND	X15, X24, #0x0

  (53) 0x12c28 CBZ	X15, 12a68

  (53) 0x12c2c LDR	X14, [SP, #528]

  (53) 0x12c30 MOVI	V2.2D, #0

  (53) 0x12c34 MOV	V2.D[0], V0.D[0]

  (53) 0x12c38 ADD	X15, X16, X10

  (53) 0x12c3c MOVI	V1.2D, #0

  (53) 0x12c40 ADD	X14, X14, X16

  (53) 0x12c44 ADD	W16, W8, W16

    (56) 0x12c48 UBFM	X17, X16, #62, #31

    (56) 0x12c4c ADDS	X14, X14, #4

    (56) 0x12c50 ADD	W16, W16, #4

    (56) 0x12c54 LDR	Q0, [X18, X17]

    (56) 0x12c58 ORR	W17, WZR, W15

    (56) 0x12c5c UBFM	X17, X17, #62, #61

    (56) 0x12c60 ADD	X15, X15, #4

    (56) 0x12c64 LDR	Q4, [X28, X17]

    (56) 0x12c68 FCVTL	V3.2D, V0.2S

    (56) 0x12c6c FCVTL2	V0.2D, V0.4S

    (56) 0x12c70 FCVTL	V5.2D, V4.2S

    (56) 0x12c74 FCVTL2	V4.2D, V4.4S

    (56) 0x12c78 FMLA	V1.2D, V4.2D, V0.2D

    (56) 0x12c7c FMLA	V2.2D, V5.2D, V3.2D

    (56) 0x12c80 B.NE	12c48

  (53) 0x12c84 FADD	V0.2D, V2.2D, V1.2D

  (53) 0x12c88 AND	X14, X24, #0x0

  (53) 0x12c8c AND	X15, X24, #0x7fffffff

  (53) 0x12c90 AND	X16, X24, #0x0

  (53) 0x12c94 FADDP	D0, V0.2D

  (53) 0x12c98 CMP	X15, X16

  (53) 0x12c9c B.EQ	12a20

  (53) 0x12ca0 B	12a68

/home/eoseret/llm-attention/attention_v2.cpp: 26 - 33

--------------------------------------------------------------------------------

26:    for (unsigned int i = 0; i < M; ++i) {

27:       for (unsigned int j = 0; j < N; ++j) {  //vectorized

28:          double sum = 0.0;

29: #pragma clang loop vectorize(enable)

30:          for (unsigned int k = 0; k < K; ++k) { //vectorized

31:             sum += (double)A[i * K + k] * (double)B[k * N + j];

32:          }

33:          C[i * N + j] = alpha * static_cast<float>(sum);

Coverage (%)	Name	Module
►100.00+	__libc_start_call_main	libc.so.6
○	__libc_start_main	libc.so.6
○	_start	attention-armclang-native

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	3.69
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.13
Bottlenecks	micro-operation queue,
Function	main
Source	attention_v2.cpp:26-26
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	1.50
CQA cycles if no scalar integer	1.50
CQA cycles if FP arith vectorized	1.50
CQA cycles if fully vectorized	0.41
Front-end cycles	1.50
P0 cycles	1.00
P1 cycles	1.00
P2 cycles	1.33
P3 cycles	1.33
P4 cycles	1.33
P5 cycles	1.33
P6 cycles	1.33
P7 cycles	1.33
P8 cycles	0.00
P9 cycles	0.00
P10 cycles	0.00
P11 cycles	0.00
P12 cycles	0.67
P13 cycles	0.67
P14 cycles	0.67
P15 cycles	0.00
P16 cycles	0.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	12.00
Nb uops	12.00
Nb loads	NA
Nb stores	0.00
Nb stack references	1.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	2.00
Bytes prefetched	0.00
Bytes loaded	3.00
Bytes stored	0.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	NA
Vectorization ratio store	NA
Vectorization ratio mul	0.00
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	30.00
Vector-efficiency ratio load	NA
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	25.00
Vector-efficiency ratio add_sub	25.00
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	37.50

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	3.69
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.13
Bottlenecks	micro-operation queue,
Function	main
Source	attention_v2.cpp:26-26
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	1.50
CQA cycles if no scalar integer	1.50
CQA cycles if FP arith vectorized	1.50
CQA cycles if fully vectorized	0.41
Front-end cycles	1.50
P0 cycles	1.00
P1 cycles	1.00
P2 cycles	1.33
P3 cycles	1.33
P4 cycles	1.33
P5 cycles	1.33
P6 cycles	1.33
P7 cycles	1.33
P8 cycles	0.00
P9 cycles	0.00
P10 cycles	0.00
P11 cycles	0.00
P12 cycles	0.67
P13 cycles	0.67
P14 cycles	0.67
P15 cycles	0.00
P16 cycles	0.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	12.00
Nb uops	12.00
Nb loads	NA
Nb stores	0.00
Nb stack references	1.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	2.00
Bytes prefetched	0.00
Bytes loaded	3.00
Bytes stored	0.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	NA
Vectorization ratio store	NA
Vectorization ratio mul	0.00
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	30.00
Vector-efficiency ratio load	NA
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	25.00
Vector-efficiency ratio add_sub	25.00
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	37.50

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	main
Source file and lines	attention_v2.cpp:26-33
Module	attention-armclang-native

The loop is defined in /home/eoseret/llm-attention/attention_v2.cpp:26-33.

Analyzed code is defined in /home/eoseret/llm-attention/attention_v2.cpp:26.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Failed to get the number of paths
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. Only 30% of vector register length is used (average across all VPU instructions). By vectorizing your loop, you can lower the cost of an iteration from 1.50 to 0.41 cycles (3.69x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ffast-math (included in Ofast) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 3 bytes.

General properties

nb instructions	12
nb uops	12
loop length	48
used w registers	8
used x registers	4
used b registers	0
used h registers	0
used s registers	1
used d registers	0
used q registers	0
used v registers	0
used z registers	0
nb stack references	1

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	1.50 cycles
front end	1.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	1.00	1.00	1.33	1.33	1.33	1.33	1.33	1.33	0.00	0.00	0.00	0.00	0.67	0.67	0.67	0.00	0.00
cycles	1.00	1.00	1.33	1.33	1.33	1.33	1.33	1.33	0.00	0.00	0.00	0.00	0.67	0.67	0.67	0.00	0.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

NA

Cycles summary

Front-end	1.50
Dispatch	1.33
Overall L1	1.50

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	30%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	25%
add-sub	25%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	37%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 1.50 cycles. At this rate:

2% of peak load performance is reached (2.00 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 1.50 to 1.33 cycles (1.12x speedup).

ASM code

In the binary file, the address of the loop is: 129f8

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P12	P13	P14	Latency	Recip. throughput	Vectorization
ADD W9, W9, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	1	0.17	scal (25.0%)
ADD W8, W8, W24	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	1	0.17	scal (25.0%)
CMP W9, W21	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	1	0.33	scal (25.0%)
B.EQ 12ca4 <main+0x1a84>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDUR X13, [X29, #472]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
MUL W11, W9, W24	1	0	0	0	0	0	0	0.50	0.50	0	0	0	2	0.50	N/A
MUL W12, W9, W21	1	0	0	0	0	0	0	0.50	0.50	0	0	0	2	0.50	scal (25.0%)
ORR X10, XZR, XZR	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	1	0.17	scal (50.0%)
CMN W11, W13	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	1	0.33	N/A
LDR W13, [SP, #388]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
CSINC W13, W13, WZR, #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	1	0.17	N/A
B 12a44 <main+0x1824>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Function	main
Source file and lines	attention_v2.cpp:26-33
Module	attention-armclang-native

The loop is defined in /home/eoseret/llm-attention/attention_v2.cpp:26-33.

Analyzed code is defined in /home/eoseret/llm-attention/attention_v2.cpp:26.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Failed to get the number of paths
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. Only 30% of vector register length is used (average across all VPU instructions). By vectorizing your loop, you can lower the cost of an iteration from 1.50 to 0.41 cycles (3.69x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ffast-math (included in Ofast) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 3 bytes.

General properties

nb instructions	12
nb uops	12
loop length	48
used w registers	8
used x registers	4
used b registers	0
used h registers	0
used s registers	1
used d registers	0
used q registers	0
used v registers	0
used z registers	0
nb stack references	1

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	1.50 cycles
front end	1.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	1.00	1.00	1.33	1.33	1.33	1.33	1.33	1.33	0.00	0.00	0.00	0.00	0.67	0.67	0.67	0.00	0.00
cycles	1.00	1.00	1.33	1.33	1.33	1.33	1.33	1.33	0.00	0.00	0.00	0.00	0.67	0.67	0.67	0.00	0.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

NA

Cycles summary

Front-end	1.50
Dispatch	1.33
Overall L1	1.50

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	30%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	25%
add-sub	25%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	37%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 1.50 cycles. At this rate:

2% of peak load performance is reached (2.00 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 1.50 to 1.33 cycles (1.12x speedup).

ASM code

In the binary file, the address of the loop is: 129f8

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P12	P13	P14	Latency	Recip. throughput	Vectorization
ADD W9, W9, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	1	0.17	scal (25.0%)
ADD W8, W8, W24	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	1	0.17	scal (25.0%)
CMP W9, W21	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	1	0.33	scal (25.0%)
B.EQ 12ca4 <main+0x1a84>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDUR X13, [X29, #472]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
MUL W11, W9, W24	1	0	0	0	0	0	0	0.50	0.50	0	0	0	2	0.50	N/A
MUL W12, W9, W21	1	0	0	0	0	0	0	0.50	0.50	0	0	0	2	0.50	scal (25.0%)
ORR X10, XZR, XZR	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	1	0.17	scal (50.0%)
CMN W11, W13	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	1	0.33	N/A
LDR W13, [SP, #388]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
CSINC W13, W13, WZR, #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	1	0.17	N/A
B 12a44 <main+0x1824>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Report Configuration

Vectorization

Details

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code