OV - attention-armclang-native - Loop 46 - attention-armclang-native

	Loop Id: 46	Module: attention-armclang-native	Source: attention_v2.cpp:43-61	Coverage: 0.12%

0x12d04 LDR	X8, [SP, #400]

0x12d08 LDR	X9, [SP, #504]

0x12d0c MOVZ	W27, #45279

0x12d10 ADD	X13, X13, #1

0x12d14 STR	X21, [SP, #464]

0x12d18 MOVK	W27, #39176

0x12d1c STR	S22, [X8, X28,LSL #2]

0x12d20 LDP	X8, X12, [SP, #472]

0x12d24 LDR	X28, [SP, #392]

0x12d28 ADD	X9, X9, X8

0x12d2c ADD	X12, X12, X8

0x12d30 STR	X9, [SP, #504]

0x12d34 LDR	X9, [SP, #488]

0x12d38 ADD	X9, X9, X8

0x12d3c STR	X9, [SP, #488]

0x12d40 LDR	X9, [SP, #496]

0x12d44 ADD	X9, X9, X8

0x12d48 LDR	X8, [SP, #656]

0x12d4c CMP	X21, X8

0x12d50 LDR	X21, [SP, #448]

0x12d54 B.EQ	13180

0x12d58 AND	X14, X13, #0x0

0x12d5c AND	X8, X13, #0x0

0x12d60 STR	X9, [SP, #496]

0x12d64 STR	X8, [SP, #424]

0x12d68 CMP	X13, #4

0x12d6c B.CS	12d84

0x12d70 MOVN	W9, #128

0x12d74 LDR	X28, [SP, #504]

0x12d78 ORR	X8, XZR, XZR

0x12d7c FMOV	S12, W9

0x12d80 B	12e24

0x12d84 LDR	X28, [SP, #504]

0x12d88 CMP	X13, #16

0x12d8c B.CS	12da0

0x12d90 MOVN	W9, #128

0x12d94 ORR	X8, XZR, XZR

0x12d98 FMOV	S12, W9

0x12d9c B	12dfc

0x12da0 MVNI	V0.4S, #128

0x12da4 MVNI	V1.4S, #128

0x12da8 MVNI	V2.4S, #128

0x12dac MVNI	V3.4S, #128

0x12db0 AND	X9, X13, #0x0

0x12db4 AND	X8, X13, #0x0

0x12db8 AND	X11, X13, #0x0

0x12dbc ORR	X10, XZR, X12

  (35) 0x12dc0 LDP	Q4, Q5, [X10, #2016]

  (35) 0x12dc4 SUBS	X11, X11, #16

  (35) 0x12dc8 FMAXNM	V1.4S, V5.4S, V1.4S

  (35) 0x12dcc FMAXNM	V0.4S, V4.4S, V0.4S

  (35) 0x12dd0 LDP	Q6, Q7, [X10], #64

  (35) 0x12dd4 FMAXNM	V2.4S, V6.4S, V2.4S

  (35) 0x12dd8 FMAXNM	V3.4S, V7.4S, V3.4S

  (35) 0x12ddc B.NE	12dc0

0x12de0 FMAXNM	V0.4S, V0.4S, V1.4S

0x12de4 FMAXNM	V0.4S, V0.4S, V2.4S

0x12de8 FMAXNM	V0.4S, V0.4S, V3.4S

0x12dec FMAXNMV	S12, V0.4S

0x12df0 CMP	X13, X8

0x12df4 B.EQ	12e38

0x12df8 CBZ	X9, 12e24

0x12dfc DUP	V0.4S, V12.S[0]

0x12e00 SUB	X9, X8, X14

0x12e04 ADD	X10, X28, X8,LSL #2

0x12e08 AND	X8, X13, #0x0

  (51) 0x12e0c LDR	Q1, [X10], #16

  (51) 0x12e10 ADDS	X9, X9, #4

  (51) 0x12e14 FMAXNM	V0.4S, V1.4S, V0.4S

  (51) 0x12e18 B.NE	12e0c

0x12e1c FMAXNMV	S12, V0.4S

0x12e20 B	12e30

  (50) 0x12e24 LDR	S0, [X28, X8,LSL #2]

  (50) 0x12e28 ADD	X8, X8, #1

  (50) 0x12e2c FMAXNM	S12, S0, S12

  (50) 0x12e30 CMP	X13, X8

  (50) 0x12e34 B.NE	12e24

0x12e38 STR	X13, [SP, #616]

0x12e3c STR	Q12, [SP, #592]

0x12e40 STR	X12, [SP, #480]

0x12e44 STR	X14, [SP, #440]

0x12e48 CMP	X13, #4

0x12e4c B.CS	12e60

0x12e50 MOVI	D22, #0

0x12e54 ORR	X21, XZR, XZR

0x12e58 B	12fa0

0x12e60 CMP	X13, #16

0x12e64 B.CS	12e80

0x12e68 ORR	X21, XZR, XZR

0x12e6c MOVI	D22, #0

0x12e70 B	12f34

0x12e80 DUP	V21.4S, V12.S[0]

0x12e84 AND	X8, X13, #0x0

0x12e88 AND	X21, X13, #0x0

0x12e8c AND	X22, X13, #0x0

0x12e90 MOVI	V20.2D, #0

0x12e94 ORR	X25, XZR, X12

0x12e98 STR	X8, [SP, #624]

0x12e9c MOVI	V22.2D, #0

0x12ea0 MOVI	V23.2D, #0

0x12ea4 MOVI	V11.2D, #0

  (36) 0x12ea8 LDP	Q0, Q1, [X25, #2016]

  (36) 0x12eac FSUB	V16.4S, V1.4S, V21.4S

  (36) 0x12eb0 FSUB	V0.4S, V0.4S, V21.4S

  (36) 0x12eb4 LDP	Q2, Q3, [X25], #64

  (36) 0x12eb8 FSUB	V17.4S, V2.4S, V21.4S

  (36) 0x12ebc FSUB	V18.4S, V3.4S, V21.4S

  (36) 0x12ec0 BL	10040

  (36) 0x12ec4 ORR	V19.16B, V0.16B, V0.16B

  (36) 0x12ec8 ORR	V0.16B, V16.16B, V16.16B

  (36) 0x12ecc BL	10040

  (36) 0x12ed0 ORR	V16.16B, V0.16B, V0.16B

  (36) 0x12ed4 ORR	V0.16B, V17.16B, V17.16B

  (36) 0x12ed8 BL	10040

  (36) 0x12edc ORR	V17.16B, V0.16B, V0.16B

  (36) 0x12ee0 ORR	V0.16B, V18.16B, V18.16B

  (36) 0x12ee4 BL	10040

  (36) 0x12ee8 FADD	V20.4S, V19.4S, V20.4S

  (36) 0x12eec FADD	V22.4S, V16.4S, V22.4S

  (36) 0x12ef0 FADD	V23.4S, V17.4S, V23.4S

  (36) 0x12ef4 FADD	V11.4S, V0.4S, V11.4S

  (36) 0x12ef8 SUBS	X22, X22, #16

  (36) 0x12efc B.NE	12ea8

0x12f00 FADD	V0.4S, V22.4S, V20.4S

0x12f04 LDR	X13, [SP, #616]

0x12f08 FADD	V0.4S, V23.4S, V0.4S

0x12f0c FADD	V0.4S, V11.4S, V0.4S

0x12f10 FADDP	V0.4S, V0.4S, V0.4S

0x12f14 FADDP	S22, V0.2S

0x12f18 CMP	X13, X21

0x12f1c B.NE	12f28

0x12f20 LDP	X25, X22, [SP, #408]

0x12f24 B	12fcc

0x12f28 LDP	X25, X22, [SP, #408]

0x12f2c LDR	X8, [SP, #624]

0x12f30 CBZ	X8, 12fa0

0x12f34 LDR	X8, [SP, #440]

0x12f38 MOVI	V16.2D, #0

0x12f3c MOV	V16.S[0], V22.S[0]

0x12f40 DUP	V17.4S, V12.S[0]

0x12f44 UBFM	X25, X21, #62, #61

0x12f48 SUB	X22, X21, X8

0x12f4c AND	X21, X13, #0x0

0x12f50 HINT	#0

0x12f54 HINT	#0

0x12f58 HINT	#0

0x12f5c HINT	#0

  (49) 0x12f60 LDR	Q0, [X28, X25]

  (49) 0x12f64 FSUB	V0.4S, V0.4S, V17.4S

  (49) 0x12f68 BL	10040

  (49) 0x12f6c FADD	V16.4S, V0.4S, V16.4S

  (49) 0x12f70 ADDS	X22, X22, #4

  (49) 0x12f74 ADD	X25, X25, #16

  (49) 0x12f78 B.NE	12f60

0x12f7c FADDP	V0.4S, V16.4S, V16.4S

0x12f80 LDR	X13, [SP, #616]

0x12f84 LDP	X25, X22, [SP, #408]

0x12f88 FADDP	S22, V0.2S

0x12f8c CMP	X13, X21

0x12f90 B.EQ	12fcc

0x12f94 HINT	#0

0x12f98 HINT	#0

0x12f9c HINT	#0

  (37) 0x12fa0 LDR	S0, [X28, X21,LSL #2]

  (37) 0x12fa4 STR	Q22, [SP, #624]

  (37) 0x12fa8 FSUB	S0, S0, S12

  (37) 0x12fac BL	101c0

  (37) 0x12fb0 LDR	Q22, [SP, #624]

  (37) 0x12fb4 LDR	Q12, [SP, #592]

  (37) 0x12fb8 LDR	X13, [SP, #616]

  (37) 0x12fbc ADD	X21, X21, #1

  (37) 0x12fc0 FADD	S22, S0, S22

  (37) 0x12fc4 CMP	X13, X21

  (37) 0x12fc8 B.NE	12fa0

0x12fcc STR	Q22, [SP, #624]

0x12fd0 CMP	X13, #4

0x12fd4 B.CS	12fe8

0x12fd8 ORR	X9, XZR, X28

0x12fdc LDR	X28, [SP, #496]

0x12fe0 ORR	X21, XZR, XZR

0x12fe4 B	13100

0x12fe8 CMP	X13, #16

0x12fec B.CS	13000

0x12ff0 ORR	X9, XZR, X28

0x12ff4 LDR	X28, [SP, #496]

0x12ff8 ORR	X21, XZR, XZR

0x12ffc B	13098

0x13000 LDP	X25, X22, [SP, #480]

0x13004 LDR	X28, [SP, #424]

0x13008 DUP	V20.4S, V22.S[0]

0x1300c DUP	V21.4S, V12.S[0]

0x13010 AND	X27, X13, #0x0

0x13014 AND	X21, X13, #0x0

0x13018 HINT	#0

0x1301c HINT	#0

  (38) 0x13020 LDP	Q0, Q1, [X25, #2016]

  (38) 0x13024 FSUB	V16.4S, V1.4S, V21.4S

  (38) 0x13028 FSUB	V0.4S, V0.4S, V21.4S

  (38) 0x1302c LDP	Q2, Q3, [X25], #64

  (38) 0x13030 FSUB	V17.4S, V2.4S, V21.4S

  (38) 0x13034 FSUB	V18.4S, V3.4S, V21.4S

  (38) 0x13038 BL	10040

  (38) 0x1303c ORR	V19.16B, V0.16B, V0.16B

  (38) 0x13040 ORR	V0.16B, V16.16B, V16.16B

  (38) 0x13044 BL	10040

  (38) 0x13048 ORR	V16.16B, V0.16B, V0.16B

  (38) 0x1304c ORR	V0.16B, V17.16B, V17.16B

  (38) 0x13050 BL	10040

  (38) 0x13054 ORR	V17.16B, V0.16B, V0.16B

  (38) 0x13058 ORR	V0.16B, V18.16B, V18.16B

  (38) 0x1305c BL	10040

  (38) 0x13060 FDIV	V1.4S, V19.4S, V20.4S

  (38) 0x13064 SUBS	X28, X28, #16

  (38) 0x13068 FDIV	V2.4S, V16.4S, V20.4S

  (38) 0x1306c STP	Q1, Q2, [X22, #2016]

  (38) 0x13070 FDIV	V1.4S, V17.4S, V20.4S

  (38) 0x13074 FDIV	V0.4S, V0.4S, V20.4S

  (38) 0x13078 STP	Q1, Q0, [X22], #64

  (38) 0x1307c B.NE	13020

0x13080 LDR	X13, [SP, #616]

0x13084 LDP	X25, X22, [SP, #408]

0x13088 LDP	X28, X9, [SP, #496]

0x1308c CMP	X13, X21

0x13090 B.EQ	13134

0x13094 CBZ	X27, 13100

0x13098 LDR	X8, [SP, #440]

0x1309c DUP	V16.4S, V22.S[0]

0x130a0 DUP	V17.4S, V12.S[0]

0x130a4 UBFM	X25, X21, #62, #61

0x130a8 SUB	X22, X21, X8

0x130ac AND	X21, X13, #0x0

0x130b0 HINT	#0

0x130b4 HINT	#0

0x130b8 HINT	#0

0x130bc HINT	#0

  (48) 0x130c0 LDR	Q0, [X9, X25]

  (48) 0x130c4 ORR	X27, XZR, X9

  (48) 0x130c8 FSUB	V0.4S, V0.4S, V17.4S

  (48) 0x130cc BL	10040

  (48) 0x130d0 FDIV	V0.4S, V0.4S, V16.4S

  (48) 0x130d4 ADDS	X22, X22, #4

  (48) 0x130d8 ORR	X9, XZR, X27

  (48) 0x130dc STR	Q0, [X28, X25]

  (48) 0x130e0 ADD	X25, X25, #16

  (48) 0x130e4 B.NE	130c0

0x130e8 LDR	X13, [SP, #616]

0x130ec LDP	X25, X22, [SP, #408]

0x130f0 CMP	X13, X21

0x130f4 B.EQ	13134

0x130f8 HINT	#0

0x130fc HINT	#0

  (47) 0x13100 LDR	S0, [X9, X21,LSL #2]

  (47) 0x13104 ORR	X27, XZR, X9

  (47) 0x13108 FSUB	S0, S0, S12

  (47) 0x1310c BL	101c0

  (47) 0x13110 LDR	Q22, [SP, #624]

  (47) 0x13114 LDR	Q12, [SP, #592]

  (47) 0x13118 LDR	X13, [SP, #616]

  (47) 0x1311c ORR	X9, XZR, X27

  (47) 0x13120 FDIV	S0, S0, S22

  (47) 0x13124 STR	S0, [X28, X21,LSL #2]

  (47) 0x13128 ADD	X21, X21, #1

  (47) 0x1312c CMP	X13, X21

  (47) 0x13130 B.NE	13100

0x13134 LDR	X28, [SP, #464]

0x13138 LDR	X8, [SP, #656]

0x1313c ADD	X21, X28, #1

0x13140 CMP	X21, X8

0x13144 B.CS	12d04

0x13148 LDP	X9, X8, [SP, #328]

0x1314c MOVZ	X10, #4

0x13150 ORR	W1, WZR, WZR

0x13154 MADD	X9, X9, X28, X10

0x13158 SUB	W8, W8, W28

0x1315c UBFM	X8, X8, #62, #31

0x13160 AND	X9, X9, #0x0

0x13164 ADD	X2, X8, #4

0x13168 ADD	X0, X23, X9

0x1316c BL	100c0

0x13170 LDR	Q22, [SP, #624]

0x13174 LDR	X13, [SP, #616]

0x13178 B	12d04

/home/eoseret/llm-attention/attention_v2.cpp: 43 - 61

--------------------------------------------------------------------------------

43:    for (int row = 0; row < N; ++row) {

44:       const float *S_row = &S[row * N];

45:

46:       float max_val = -FLT_MAX;

47:       for (int idx = 0; idx <= row; ++idx) // vectorised

48:          if (S_row[idx] > max_val) max_val = S_row[idx];

49:

50:       float sum = 0.0f;

51: #pragma clang loop vectorize(enable)

52:       for (int idx = 0; idx <= row; ++idx) // vectorised

53:          sum += expf(S_row[idx] - max_val);

54:

55:       for (int idx = 0; idx <= row; ++idx)  //vectorised

56:          P[row * N + idx] = expf(S_row[idx] - max_val) / sum;

57:

58:       for (int idx = row + 1; idx < N; ++idx)

59:          P[row * N + idx] = 0.0f;

60:

61:       D[row] = sum;

Coverage (%)	Name	Module
►100.00+	__libc_start_call_main	libc.so.6
○	__libc_start_main	libc.so.6
○	_start	attention-armclang-native

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	2.72
CQA speedup if FP arith vectorized	1.01
CQA speedup if fully vectorized	1.21
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.39
Bottlenecks	micro-operation queue,
Function	main
Source	attention_v2.cpp:43-44,attention_v2.cpp:47-47,attention_v2.cpp:52-52,attention_v2.cpp:55-55,attention_v2.cpp:58-61
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	20.38
CQA cycles if no scalar integer	7.50
CQA cycles if FP arith vectorized	20.26
CQA cycles if fully vectorized	16.83
Front-end cycles	20.38
P0 cycles	13.00
P1 cycles	13.00
P2 cycles	10.25
P3 cycles	10.25
P4 cycles	10.17
P5 cycles	10.17
P6 cycles	10.08
P7 cycles	10.08
P8 cycles	9.00
P9 cycles	9.00
P10 cycles	9.00
P11 cycles	9.00
P12 cycles	14.67
P13 cycles	14.67
P14 cycles	14.67
P15 cycles	4.50
P16 cycles	4.50
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	178.00
Nb uops	163.00
Nb loads	NA
Nb stores	12.00
Nb stack references	43.00
FLOP/cycle	1.08
Nb FLOP add-sub	22.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	0.15
Bytes prefetched	0.00
Bytes loaded	0.00
Bytes stored	3.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	20.41
Vectorization ratio load	7.69
Vectorization ratio store	16.67
Vectorization ratio mul	NA
Vectorization ratio add_sub	35.71
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	20.34
Vector-efficiency ratio all	60.46
Vector-efficiency ratio load	76.92
Vector-efficiency ratio store	56.25
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	67.86
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	55.93

Metric	Value
CQA speedup if no scalar integer	2.72
CQA speedup if FP arith vectorized	1.01
CQA speedup if fully vectorized	1.21
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.39
Bottlenecks	micro-operation queue,
Function	main
Source	attention_v2.cpp:43-44,attention_v2.cpp:47-47,attention_v2.cpp:52-52,attention_v2.cpp:55-55,attention_v2.cpp:58-61
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	20.38
CQA cycles if no scalar integer	7.50
CQA cycles if FP arith vectorized	20.26
CQA cycles if fully vectorized	16.83
Front-end cycles	20.38
P0 cycles	13.00
P1 cycles	13.00
P2 cycles	10.25
P3 cycles	10.25
P4 cycles	10.17
P5 cycles	10.17
P6 cycles	10.08
P7 cycles	10.08
P8 cycles	9.00
P9 cycles	9.00
P10 cycles	9.00
P11 cycles	9.00
P12 cycles	14.67
P13 cycles	14.67
P14 cycles	14.67
P15 cycles	4.50
P16 cycles	4.50
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	178.00
Nb uops	163.00
Nb loads	NA
Nb stores	12.00
Nb stack references	43.00
FLOP/cycle	1.08
Nb FLOP add-sub	22.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	0.15
Bytes prefetched	0.00
Bytes loaded	0.00
Bytes stored	3.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	20.41
Vectorization ratio load	7.69
Vectorization ratio store	16.67
Vectorization ratio mul	NA
Vectorization ratio add_sub	35.71
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	20.34
Vector-efficiency ratio all	60.46
Vector-efficiency ratio load	76.92
Vector-efficiency ratio store	56.25
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	67.86
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	55.93

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	main
Source file and lines	attention_v2.cpp:43-61
Module	attention-armclang-native

The loop is defined in /home/eoseret/llm-attention/attention_v2.cpp:43-61.

Analyzed code is defined in /home/eoseret/llm-attention/attention_v2.cpp:43-44,47,52,55,58-61.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Failed to get the number of paths
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 20.38 to 7.50 cycles (2.72x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is poorly vectorized. Only 60% of vector register length is used (average across all VPU instructions). By fully vectorizing your loop, you can lower the cost of an iteration from 20.38 to 16.83 cycles (1.21x speedup).

Details

20% of VPU instructions are used in vector version (process two or more data elements in vector registers):

7% of VPU loads are used in vector version.
16% of VPU stores are used in vector version.
35% of VPU addition or subtraction instructions are used in vector version.
20% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ffast-math (included in Ofast) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

unknown: 1 occurrences►
- /home/eoseret/llm-attention/attention_v2.cpp:59

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 22 FP arithmetical operations:

22: addition or subtraction

The binary loop is storing 3 bytes.

Arithmetic intensity

Arithmetic intensity is 7.33 FP operations per loaded or stored byte.

General properties

nb instructions	178
nb uops	163
loop length	712
used w registers	6
used x registers	16
used b registers	0
used h registers	0
used s registers	3
used d registers	1
used q registers	2
used v registers	12
used z registers	0
nb stack references	43

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	20.38 cycles
front end	20.38 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	13.00	13.00	10.25	10.25	10.17	10.17	10.08	10.08	9.00	9.00	9.00	9.00	14.67	14.67	14.67	4.50	4.50
cycles	13.00	13.00	10.25	10.25	10.17	10.17	10.08	10.08	9.00	9.00	9.00	9.00	14.67	14.67	14.67	4.50	4.50

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	20.38
Dispatch	14.67
Overall L1	20.38

Vectorization ratios

INT

all	11%
load	7%
store	16%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	13%

all	71%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	71%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	71%

INT+FP

all	20%
load	7%
store	16%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	35%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	20%

Vector efficiency ratios

INT

all	56%
load	76%
store	56%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	50%
fma	NA (no fma vectorizable/vectorized instructions)
other	52%

all	82%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	85%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	78%

INT+FP

all	60%
load	76%
store	56%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	67%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	55%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 20.38 cycles. At this rate:

0% of peak store performance is reached (0.15 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 20.38 to 14.67 cycles (1.39x speedup).

ASM code

In the binary file, the address of the loop is: 12d58

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
LDR X8, [SP, #400]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X9, [SP, #504]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
MOVZ W27, #45279	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
ADD X13, X13, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
STR X21, [SP, #464]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
MOVK W27, #39176	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
STR S22, [X8, X28,LSL #2]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (25.0%)
LDP X8, X12, [SP, #472]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDR X28, [SP, #392]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X9, X9, X8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X12, X12, X8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
STR X9, [SP, #504]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X9, [SP, #488]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X9, X9, X8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STR X9, [SP, #488]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X9, [SP, #496]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X9, X9, X8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR X8, [SP, #656]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X21, X8	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
LDR X21, [SP, #448]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
B.EQ 13180 <main+0x1f60>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
AND X14, X13, #0x0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
AND X8, X13, #0x0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STR X9, [SP, #496]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X8, [SP, #424]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
CMP X13, #4	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.CS 12d84 <main+0x1b64>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVN W9, #128	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR X28, [SP, #504]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ORR X8, XZR, XZR	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
FMOV S12, W9	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
B 12e24 <main+0x1c04>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X28, [SP, #504]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X13, #16	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.CS 12da0 <main+0x1b80>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVN W9, #128	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ORR X8, XZR, XZR	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
FMOV S12, W9	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
B 12dfc <main+0x1bdc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MVNI V0.4S, #128	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
MVNI V1.4S, #128	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
MVNI V2.4S, #128	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
MVNI V3.4S, #128	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
AND X9, X13, #0x0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
AND X8, X13, #0x0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
AND X11, X13, #0x0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ORR X10, XZR, X12	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
FMAXNM V0.4S, V0.4S, V1.4S	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
FMAXNM V0.4S, V0.4S, V2.4S	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
FMAXNM V0.4S, V0.4S, V3.4S	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
FMAXNMV S12, V0.4S	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.50	vect (100.0%)
CMP X13, X8	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 12e38 <main+0x1c18>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CBZ X9, 12e24 <main+0x1c04>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
DUP V0.4S, V12.S[0]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
SUB X9, X8, X14	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X10, X28, X8,LSL #2	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
AND X8, X13, #0x0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
FMAXNMV S12, V0.4S	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.50	vect (100.0%)
B 12e30 <main+0x1c10>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STR X13, [SP, #616]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR Q12, [SP, #592]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
STR X12, [SP, #480]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X14, [SP, #440]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
CMP X13, #4	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.CS 12e60 <main+0x1c40>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVI D22, #0	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
ORR X21, XZR, XZR	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
B 12fa0 <main+0x1d80>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X13, #16	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.CS 12e80 <main+0x1c60>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X21, XZR, XZR	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
MOVI D22, #0	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
B 12f34 <main+0x1d14>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
DUP V21.4S, V12.S[0]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
AND X8, X13, #0x0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
AND X21, X13, #0x0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
AND X22, X13, #0x0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
MOVI V20.2D, #0	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
ORR X25, XZR, X12	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
STR X8, [SP, #624]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
MOVI V22.2D, #0	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
MOVI V23.2D, #0	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
MOVI V11.2D, #0	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
FADD V0.4S, V22.4S, V20.4S	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
LDR X13, [SP, #616]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
FADD V0.4S, V23.4S, V0.4S	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
FADD V0.4S, V11.4S, V0.4S	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
FADDP V0.4S, V0.4S, V0.4S	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
FADDP S22, V0.2S	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
CMP X13, X21	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.NE 12f28 <main+0x1d08>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X25, X22, [SP, #408]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
B 12fcc <main+0x1dac>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X25, X22, [SP, #408]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDR X8, [SP, #624]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CBZ X8, 12fa0 <main+0x1d80>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X8, [SP, #440]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
MOVI V16.2D, #0	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
MOV V16.S[0], V22.S[0]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
DUP V17.4S, V12.S[0]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
UBFM X25, X21, #62, #61	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
SUB X22, X21, X8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
AND X21, X13, #0x0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
FADDP V0.4S, V16.4S, V16.4S	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
LDR X13, [SP, #616]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDP X25, X22, [SP, #408]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
FADDP S22, V0.2S	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
CMP X13, X21	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 12fcc <main+0x1dac>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
STR Q22, [SP, #624]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
CMP X13, #4	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.CS 12fe8 <main+0x1dc8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X9, XZR, X28	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR X28, [SP, #496]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ORR X21, XZR, XZR	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
B 13100 <main+0x1ee0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X13, #16	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.CS 13000 <main+0x1de0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X9, XZR, X28	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR X28, [SP, #496]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ORR X21, XZR, XZR	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
B 13098 <main+0x1e78>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X25, X22, [SP, #480]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDR X28, [SP, #424]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
DUP V20.4S, V22.S[0]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
DUP V21.4S, V12.S[0]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
AND X27, X13, #0x0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
AND X21, X13, #0x0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
HINT #0																					N/A
HINT #0																					N/A
LDR X13, [SP, #616]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDP X25, X22, [SP, #408]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X28, X9, [SP, #496]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
CMP X13, X21	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 13134 <main+0x1f14>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CBZ X27, 13100 <main+0x1ee0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X8, [SP, #440]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
DUP V16.4S, V22.S[0]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
DUP V17.4S, V12.S[0]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
UBFM X25, X21, #62, #61	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
SUB X22, X21, X8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
AND X21, X13, #0x0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
LDR X13, [SP, #616]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDP X25, X22, [SP, #408]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
CMP X13, X21	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 13134 <main+0x1f14>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																					N/A
HINT #0																					N/A
LDR X28, [SP, #464]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X8, [SP, #656]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X21, X28, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
CMP X21, X8	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.CS 12d04 <main+0x1ae4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X9, X8, [SP, #328]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
MOVZ X10, #4	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ORR W1, WZR, WZR	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
MADD X9, X9, X28, X10	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
SUB W8, W8, W28	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
UBFM X8, X8, #62, #31	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
AND X9, X9, #0x0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X2, X8, #4	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ADD X0, X23, X9	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
BL 100c0 <@plt_start@+0xa0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR Q22, [SP, #624]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
LDR X13, [SP, #616]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
B 12d04 <main+0x1ae4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Function	main
Source file and lines	attention_v2.cpp:43-61
Module	attention-armclang-native

The loop is defined in /home/eoseret/llm-attention/attention_v2.cpp:43-61.

Analyzed code is defined in /home/eoseret/llm-attention/attention_v2.cpp:43-44,47,52,55,58-61.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Failed to get the number of paths
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 20.38 to 7.50 cycles (2.72x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

20% of VPU instructions are used in vector version (process two or more data elements in vector registers):

7% of VPU loads are used in vector version.
16% of VPU stores are used in vector version.
35% of VPU addition or subtraction instructions are used in vector version.
20% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ffast-math (included in Ofast) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

CALL instructions

Detected function call instructions.

Details

unknown: 1 occurrences►
- /home/eoseret/llm-attention/attention_v2.cpp:59

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 22 FP arithmetical operations:

22: addition or subtraction

The binary loop is storing 3 bytes.

Arithmetic intensity

Arithmetic intensity is 7.33 FP operations per loaded or stored byte.

General properties

nb instructions	178
nb uops	163
loop length	712
used w registers	6
used x registers	16
used b registers	0
used h registers	0
used s registers	3
used d registers	1
used q registers	2
used v registers	12
used z registers	0
nb stack references	43

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	20.38 cycles
front end	20.38 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	13.00	13.00	10.25	10.25	10.17	10.17	10.08	10.08	9.00	9.00	9.00	9.00	14.67	14.67	14.67	4.50	4.50
cycles	13.00	13.00	10.25	10.25	10.17	10.17	10.08	10.08	9.00	9.00	9.00	9.00	14.67	14.67	14.67	4.50	4.50

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	20.38
Dispatch	14.67
Overall L1	20.38

Vectorization ratios

INT

all	11%
load	7%
store	16%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	13%

all	71%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	71%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	71%

INT+FP

all	20%
load	7%
store	16%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	35%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	20%

Vector efficiency ratios

INT

all	56%
load	76%
store	56%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	50%
fma	NA (no fma vectorizable/vectorized instructions)
other	52%

all	82%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	85%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	78%

INT+FP

all	60%
load	76%
store	56%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	67%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	55%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 20.38 cycles. At this rate:

0% of peak store performance is reached (0.15 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the loop is: 12d58

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
LDR X8, [SP, #400]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X9, [SP, #504]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
MOVZ W27, #45279	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
ADD X13, X13, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
STR X21, [SP, #464]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
MOVK W27, #39176	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
STR S22, [X8, X28,LSL #2]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (25.0%)
LDP X8, X12, [SP, #472]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDR X28, [SP, #392]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X9, X9, X8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X12, X12, X8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
STR X9, [SP, #504]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X9, [SP, #488]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X9, X9, X8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STR X9, [SP, #488]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X9, [SP, #496]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X9, X9, X8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR X8, [SP, #656]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X21, X8	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
LDR X21, [SP, #448]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
B.EQ 13180 <main+0x1f60>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
AND X14, X13, #0x0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
AND X8, X13, #0x0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STR X9, [SP, #496]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X8, [SP, #424]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
CMP X13, #4	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.CS 12d84 <main+0x1b64>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVN W9, #128	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR X28, [SP, #504]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ORR X8, XZR, XZR	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
FMOV S12, W9	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
B 12e24 <main+0x1c04>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X28, [SP, #504]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X13, #16	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.CS 12da0 <main+0x1b80>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVN W9, #128	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ORR X8, XZR, XZR	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
FMOV S12, W9	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
B 12dfc <main+0x1bdc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MVNI V0.4S, #128	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
MVNI V1.4S, #128	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
MVNI V2.4S, #128	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
MVNI V3.4S, #128	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
AND X9, X13, #0x0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
AND X8, X13, #0x0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
AND X11, X13, #0x0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ORR X10, XZR, X12	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
FMAXNM V0.4S, V0.4S, V1.4S	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
FMAXNM V0.4S, V0.4S, V2.4S	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
FMAXNM V0.4S, V0.4S, V3.4S	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
FMAXNMV S12, V0.4S	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.50	vect (100.0%)
CMP X13, X8	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 12e38 <main+0x1c18>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CBZ X9, 12e24 <main+0x1c04>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
DUP V0.4S, V12.S[0]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
SUB X9, X8, X14	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X10, X28, X8,LSL #2	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
AND X8, X13, #0x0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
FMAXNMV S12, V0.4S	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.50	vect (100.0%)
B 12e30 <main+0x1c10>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STR X13, [SP, #616]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR Q12, [SP, #592]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
STR X12, [SP, #480]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X14, [SP, #440]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
CMP X13, #4	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.CS 12e60 <main+0x1c40>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVI D22, #0	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
ORR X21, XZR, XZR	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
B 12fa0 <main+0x1d80>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X13, #16	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.CS 12e80 <main+0x1c60>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X21, XZR, XZR	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
MOVI D22, #0	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
B 12f34 <main+0x1d14>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
DUP V21.4S, V12.S[0]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
AND X8, X13, #0x0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
AND X21, X13, #0x0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
AND X22, X13, #0x0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
MOVI V20.2D, #0	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
ORR X25, XZR, X12	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
STR X8, [SP, #624]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
MOVI V22.2D, #0	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
MOVI V23.2D, #0	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
MOVI V11.2D, #0	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
FADD V0.4S, V22.4S, V20.4S	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
LDR X13, [SP, #616]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
FADD V0.4S, V23.4S, V0.4S	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
FADD V0.4S, V11.4S, V0.4S	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
FADDP V0.4S, V0.4S, V0.4S	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
FADDP S22, V0.2S	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
CMP X13, X21	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.NE 12f28 <main+0x1d08>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X25, X22, [SP, #408]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
B 12fcc <main+0x1dac>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X25, X22, [SP, #408]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDR X8, [SP, #624]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CBZ X8, 12fa0 <main+0x1d80>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X8, [SP, #440]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
MOVI V16.2D, #0	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
MOV V16.S[0], V22.S[0]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
DUP V17.4S, V12.S[0]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
UBFM X25, X21, #62, #61	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
SUB X22, X21, X8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
AND X21, X13, #0x0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
FADDP V0.4S, V16.4S, V16.4S	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
LDR X13, [SP, #616]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDP X25, X22, [SP, #408]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
FADDP S22, V0.2S	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
CMP X13, X21	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 12fcc <main+0x1dac>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
STR Q22, [SP, #624]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
CMP X13, #4	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.CS 12fe8 <main+0x1dc8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X9, XZR, X28	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR X28, [SP, #496]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ORR X21, XZR, XZR	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
B 13100 <main+0x1ee0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X13, #16	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.CS 13000 <main+0x1de0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X9, XZR, X28	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR X28, [SP, #496]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ORR X21, XZR, XZR	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
B 13098 <main+0x1e78>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X25, X22, [SP, #480]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDR X28, [SP, #424]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
DUP V20.4S, V22.S[0]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
DUP V21.4S, V12.S[0]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
AND X27, X13, #0x0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
AND X21, X13, #0x0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
HINT #0																					N/A
HINT #0																					N/A
LDR X13, [SP, #616]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDP X25, X22, [SP, #408]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X28, X9, [SP, #496]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
CMP X13, X21	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 13134 <main+0x1f14>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CBZ X27, 13100 <main+0x1ee0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X8, [SP, #440]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
DUP V16.4S, V22.S[0]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
DUP V17.4S, V12.S[0]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
UBFM X25, X21, #62, #61	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
SUB X22, X21, X8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
AND X21, X13, #0x0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
LDR X13, [SP, #616]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDP X25, X22, [SP, #408]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
CMP X13, X21	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 13134 <main+0x1f14>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																					N/A
HINT #0																					N/A
LDR X28, [SP, #464]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X8, [SP, #656]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X21, X28, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
CMP X21, X8	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.CS 12d04 <main+0x1ae4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X9, X8, [SP, #328]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
MOVZ X10, #4	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ORR W1, WZR, WZR	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
MADD X9, X9, X28, X10	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
SUB W8, W8, W28	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
UBFM X8, X8, #62, #31	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
AND X9, X9, #0x0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X2, X8, #4	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ADD X0, X23, X9	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
BL 100c0 <@plt_start@+0xa0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR Q22, [SP, #624]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
LDR X13, [SP, #616]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
B 12d04 <main+0x1ae4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

CALL instructions

Details

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

CALL instructions

Details

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code