OV - attention-native - Loop 46

0x12900 LDR	X18, [SP, #272]

0x12904 ADD	W15, W15, #1

0x12908 ADD	X14, X14, X25

0x1290c CMP	W15, W18

0x12910 B.EQ	128e4

0x12914 MUL	W17, W15, W25

0x12918 MUL	W18, W15, W18

0x1291c ORR	X16, XZR, XZR

0x12920 CMN	W17, W9

0x12924 CSINC	W0, W11, WZR, #3

0x12928 B	12950

  (47) 0x1292c FCVT	S1, D1

  (47) 0x12930 LDR	X2, [SP, #256]

  (47) 0x12934 ADD	W1, W18, W16

  (47) 0x12938 ADD	X16, X16, #1

  (47) 0x1293c FDIV	S1, S1, S0

  (47) 0x12940 STR	S1, [X2, W1,UXTW #2]

  (47) 0x12944 LDR	X1, [SP, #280]

  (47) 0x12948 CMP	X16, X1

  (47) 0x1294c B.EQ	12900

  (47) 0x12950 MOVI	D1, #0

  (47) 0x12954 CMP	X6, X10

  (47) 0x12958 B.CC	12968

  (47) 0x1295c CMN	W16, W9

  (47) 0x12960 CSINC	W1, W0, WZR, #3

  (47) 0x12964 TBZ	W1, #0, 12a04

  (47) 0x12968 ORR	X2, XZR, XZR

  (47) 0x1296c SUB	W3, W25, W2

  (47) 0x12970 ADD	X1, X2, #1

  (47) 0x12974 TBZ	W3, #0, 1299c

  (47) 0x12978 ADD	W3, W17, W2

  (47) 0x1297c LDR	S2, [X26, W3,UXTW #2]

  (47) 0x12980 LDR	X3, [SP, #272]

  (47) 0x12984 MADD	W2, W2, W3, W16

  (47) 0x12988 LDR	S3, [X28, W2,UXTW #2]

  (47) 0x1298c FCVT	D2, S2

  (47) 0x12990 ORR	X2, XZR, X1

  (47) 0x12994 FCVT	D3, S3

  (47) 0x12998 FMADD	D1, D2, D3, D1

  (47) 0x1299c CMP	X6, X1

  (47) 0x129a0 B.EQ	1292c

  (47) 0x129a4 LDR	X5, [SP, #272]

  (47) 0x129a8 SUB	X1, X6, X2

  (47) 0x129ac MUL	X4, X5, X2

  (47) 0x129b0 ADD	X5, X16, X5

  (47) 0x129b4 ADD	W2, W14, W2

  (47) 0x129b8 ADD	X3, X16, X4

  (47) 0x129bc ADD	X4, X5, X4

    (48) 0x129c0 LDR	S2, [X26, W2,UXTW #2]

    (48) 0x129c4 LDR	S3, [X28, W3,UXTW #2]

    (48) 0x129c8 ADD	W5, W2, #1

    (48) 0x129cc SUBS	X1, X1, #2

    (48) 0x129d0 ADD	X3, X3, X13

    (48) 0x129d4 ADD	W2, W2, #2

    (48) 0x129d8 FCVT	D2, S2

    (48) 0x129dc FCVT	D3, S3

    (48) 0x129e0 FMADD	D1, D2, D3, D1

    (48) 0x129e4 LDR	S2, [X26, W5,UXTW #2]

    (48) 0x129e8 LDR	S3, [X28, W4,UXTW #2]

    (48) 0x129ec ADD	X4, X4, X13

    (48) 0x129f0 FCVT	D2, S2

    (48) 0x129f4 FCVT	D3, S3

    (48) 0x129f8 FMADD	D1, D2, D3, D1

    (48) 0x129fc B.NE	129c0

  (47) 0x12a00 B	1292c

  (47) 0x12a04 MOVI	V1.2D, #0

  (47) 0x12a08 MOVI	V2.2D, #0

  (47) 0x12a0c ORR	X1, XZR, XZR

  (47) 0x12a10 HINT	#0

  (47) 0x12a14 HINT	#0

  (47) 0x12a18 HINT	#0

  (47) 0x12a1c HINT	#0

    (49) 0x12a20 ADD	W2, W14, W1

    (49) 0x12a24 ADD	X3, X26, W2,UXTW #2

    (49) 0x12a28 LD1W	{Z3.D}, P0/Z, [X26, X2,LSL #2]

    (49) 0x12a2c ADD	W2, W16, W1

    (49) 0x12a30 ADD	X1, X1, X10

    (49) 0x12a34 LD1W	{Z5.D}, P0/Z, [X28, X2,LSL #2]

    (49) 0x12a38 CMP	X12, X1

    (49) 0x12a3c LD1W	{Z4.D}, P0/Z, [X3, #1, MUL VL]

    (49) 0x12a40 ADD	X3, X28, W2,UXTW #2

    (49) 0x12a44 LD1W	{Z6.D}, P0/Z, [X3, #1, MUL VL]

    (49) 0x12a48 FCVT	Z3.D, P0/M, Z3.S

    (49) 0x12a4c FCVT	Z5.D, P0/M, Z5.S

    (49) 0x12a50 FCVT	Z4.D, P0/M, Z4.S

    (49) 0x12a54 FCVT	Z6.D, P0/M, Z6.S

    (49) 0x12a58 FMLA	Z1.D, P0/M, Z3.D, Z5.D

    (49) 0x12a5c FMLA	Z2.D, P0/M, Z4.D, Z6.D

    (49) 0x12a60 B.NE	12a20

  (47) 0x12a64 FADD	Z1.D, Z2.D, Z1.D

  (47) 0x12a68 CMP	X6, X12

  (47) 0x12a6c ORR	X2, XZR, X12

  (47) 0x12a70 FADDV	D1, P0, Z1.D

  (47) 0x12a74 B.EQ	1292c

  (47) 0x12a78 B	1296c

/home/eoseret/llm-attention/attention.cpp: 26 - 267

--------------------------------------------------------------------------------

26:    for (unsigned int i = 0; i < M; ++i) {

27:       for (unsigned int j = 0; j < N; ++j) {  //vectorized

28:          double sum = 0.0;

29: #pragma clang loop vectorize(enable)

30:          for (unsigned int k = 0; k < K; ++k) { //vectorized

31:             sum += (double)A[i * K + k] * (double)B[k * N + j];

32:          }

33:          C[i * N + j] = alpha * static_cast<float>(sum);

[...]

267:    for (size_t r = 0; r < rept; r++)

Coverage (%)	Name	Module
►100.00+	__libc_start_call_main	libc.so.6
○	__libc_start_main	libc.so.6
○	_start	attention-native

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	6.40
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.45
Bottlenecks	P2, P3, P4, P5,
Function	main
Source	attention.cpp:26-26,attention.cpp:267-267
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	2.00
CQA cycles if no scalar integer	2.00
CQA cycles if FP arith vectorized	2.00
CQA cycles if fully vectorized	0.31
Front-end cycles	1.38
P0 cycles	1.00
P1 cycles	1.00
P2 cycles	2.00
P3 cycles	2.00
P4 cycles	2.00
P5 cycles	2.00
P6 cycles	0.00
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	0.00
P10 cycles	0.33
P11 cycles	0.33
P12 cycles	0.33
P13 cycles	0.00
P14 cycles	0.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	11.00
Nb uops	11.00
Nb loads	NA
Nb stores	0.00
Nb stack references	1.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	0.00
Bytes prefetched	0.00
Bytes loaded	0.00
Bytes stored	0.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	NA
Vectorization ratio mul	0.00
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	17.86
Vector-efficiency ratio load	25.00
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	12.50
Vector-efficiency ratio add_sub	18.75
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	16.67

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	6.40
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.45
Bottlenecks	P2, P3, P4, P5,
Function	main
Source	attention.cpp:26-26,attention.cpp:267-267
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	2.00
CQA cycles if no scalar integer	2.00
CQA cycles if FP arith vectorized	2.00
CQA cycles if fully vectorized	0.31
Front-end cycles	1.38
P0 cycles	1.00
P1 cycles	1.00
P2 cycles	2.00
P3 cycles	2.00
P4 cycles	2.00
P5 cycles	2.00
P6 cycles	0.00
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	0.00
P10 cycles	0.33
P11 cycles	0.33
P12 cycles	0.33
P13 cycles	0.00
P14 cycles	0.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	11.00
Nb uops	11.00
Nb loads	NA
Nb stores	0.00
Nb stack references	1.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	0.00
Bytes prefetched	0.00
Bytes loaded	0.00
Bytes stored	0.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	NA
Vectorization ratio mul	0.00
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	17.86
Vector-efficiency ratio load	25.00
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	12.50
Vector-efficiency ratio add_sub	18.75
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	16.67

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	main
Source file and lines	attention.cpp:26-267
Module	attention-native

The loop is defined in /home/eoseret/llm-attention/attention.cpp:26-33,267.

Analyzed code is defined in /home/eoseret/llm-attention/attention.cpp:26,267.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Too many paths. Rerun with max-paths=13
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

Try to simplify control and/or increase the maximum number of paths per function/loop through the 'max-paths-nb' option.

This loop has 13 execution paths.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. Only 17% of vector register length is used (average across all VPU instructions). By vectorizing your loop, you can lower the cost of an iteration from 2.00 to 0.31 cycles (6.40x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ffast-math (included in Ofast) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop does not load or store any data.

General properties

nb instructions	11
nb uops	11
loop length	44
used w registers	8
used x registers	5
used b registers	0
used h registers	0
used s registers	1
used d registers	0
used q registers	0
used v registers	0
used z registers	0
nb stack references	1

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	1.38 cycles
front end	1.38 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	1.00	1.00	2.00	2.00	2.00	2.00	0.00	0.00	0.00	0.00	0.33	0.33	0.33	0.00	0.00
cycles	1.00	1.00	2.00	2.00	2.00	2.00	0.00	0.00	0.00	0.00	0.33	0.33	0.33	0.00	0.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

NA

Cycles summary

Front-end	1.38
Dispatch	2.00
Overall L1	2.00

Vectorization ratios

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	17%
load	25%
store	NA (no store vectorizable/vectorized instructions)
mul	12%
add-sub	18%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	16%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 2.00 cycles.

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 12914

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P10	P11	P12	Latency	Recip. throughput	Vectorization
LDR X18, [SP, #272]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	scal (25.0%)
ADD W15, W15, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25	scal (12.5%)
ADD X14, X14, X25	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25	scal (25.0%)
CMP W15, W18	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.33	scal (12.5%)
B.EQ 128e4 <main+0x18e4>	1	0.50	0.50	0	0	0	0	0	0	0	1	0.50	N/A
MUL W17, W15, W25	1	0	0	0	0	0.50	0.50	0	0	0	2	0.50	N/A
MUL W18, W15, W18	1	0	0	0	0	0.50	0.50	0	0	0	2	0.50	scal (12.5%)
ORR X16, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25	scal (25.0%)
CMN W17, W9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.33	N/A
CSINC W0, W11, WZR, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25	scal (12.5%)
B 12950 <main+0x1950>	1	0.50	0.50	0	0	0	0	0	0	0	1	0.50	N/A

Function	main
Source file and lines	attention.cpp:26-267
Module	attention-native

The loop is defined in /home/eoseret/llm-attention/attention.cpp:26-33,267.

Analyzed code is defined in /home/eoseret/llm-attention/attention.cpp:26,267.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Too many paths. Rerun with max-paths=13
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

Try to simplify control and/or increase the maximum number of paths per function/loop through the 'max-paths-nb' option.

This loop has 13 execution paths.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. Only 17% of vector register length is used (average across all VPU instructions). By vectorizing your loop, you can lower the cost of an iteration from 2.00 to 0.31 cycles (6.40x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ffast-math (included in Ofast) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop does not load or store any data.

General properties

nb instructions	11
nb uops	11
loop length	44
used w registers	8
used x registers	5
used b registers	0
used h registers	0
used s registers	1
used d registers	0
used q registers	0
used v registers	0
used z registers	0
nb stack references	1

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	1.38 cycles
front end	1.38 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	1.00	1.00	2.00	2.00	2.00	2.00	0.00	0.00	0.00	0.00	0.33	0.33	0.33	0.00	0.00
cycles	1.00	1.00	2.00	2.00	2.00	2.00	0.00	0.00	0.00	0.00	0.33	0.33	0.33	0.00	0.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

NA

Cycles summary

Front-end	1.38
Dispatch	2.00
Overall L1	2.00

Vectorization ratios

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	17%
load	25%
store	NA (no store vectorizable/vectorized instructions)
mul	12%
add-sub	18%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	16%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 2.00 cycles.

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 12914

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P10	P11	P12	Latency	Recip. throughput	Vectorization
LDR X18, [SP, #272]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	scal (25.0%)
ADD W15, W15, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25	scal (12.5%)
ADD X14, X14, X25	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25	scal (25.0%)
CMP W15, W18	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.33	scal (12.5%)
B.EQ 128e4 <main+0x18e4>	1	0.50	0.50	0	0	0	0	0	0	0	1	0.50	N/A
MUL W17, W15, W25	1	0	0	0	0	0.50	0.50	0	0	0	2	0.50	N/A
MUL W18, W15, W18	1	0	0	0	0	0.50	0.50	0	0	0	2	0.50	scal (12.5%)
ORR X16, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25	scal (25.0%)
CMN W17, W9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.33	N/A
CSINC W0, W11, WZR, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25	scal (12.5%)
B 12950 <main+0x1950>	1	0.50	0.50	0	0	0	0	0	0	0	1	0.50	N/A

Report Configuration

Vectorization

Details

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code