OV - attention-armclang-native - Loop 84 - attention-armclang-native

0x11920 ADD	X10, X21, X9,LSL #3

0x11924 ORR	Z3.D, Z2.D, Z2.D

0x11928 LD1D	{Z2.D}, P1/Z, [X10, X16,LSL #3]    [1]

0x1192c SPLICE	Z3.D, P2, Z3.D, Z2.D

0x11930 ORR	Z4.D, Z2.D, Z2.D

0x11934 AND	Z4.D, Z4.D, #0x7ffffffe

0x11938 AND	Z3.D, Z3.D, #0x80000000

0x1193c ORR	Z3.D, Z4.D, Z3.D

0x11940 ORR	Z4.D, Z2.D, Z2.D

0x11944 AND	Z4.D, Z4.D, #0x1

0x11948 LSR	Z3.D, Z3.D, #63

0x1194c CMPEQ	P0.D, P1/Z, Z4.D, #0

0x11950 LD1D	{Z4.D}, P1/Z, [X21, X9,LSL #3]    [2]

0x11954 ADD	X9, X9, X11

0x11958 CMP	X14, X9

0x1195c EOR	Z3.D, Z3.D, Z4.D

0x11960 DUP	Z4.D, X20

0x11964 EOR	Z4.D, Z3.D, Z4.D

0x11968 SEL	Z3.D, P0, Z3.D, Z4.D

0x1196c ST1D	{Z3.D}, P1, [X10, X15,LSL #3]    [1]

0x11970 B.NE	11920

/usr/lib/gcc/aarch64-amazon-linux/14/../../../../include/c++/14/bits/random.tcc: 412 - 417

--------------------------------------------------------------------------------

412:       for (size_t __k = (__n - __m); __k < (__n - 1); ++__k)

413: 	{

414: 	  _UIntType __y = ((_M_x[__k] & __upper_mask)

415: 			   | (_M_x[__k + 1] & __lower_mask));

416: 	  _M_x[__k] = (_M_x[__k + (__m - __n)] ^ (__y >> 1)

417: 		       ^ ((__y & 0x01) ? __a : 0));

Coverage (%)	Name	Module
►100.00+	__libc_start_call_main	libc.so.6
○	__libc_start_main	libc.so.6
○	_start	attention-armclang-native

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	2.10
Bottlenecks	P6, P7,
Function	main
Source	random.tcc:412-417
Source loop unroll info	multi-versionned
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	5.50
CQA cycles if no scalar integer	5.50
CQA cycles if FP arith vectorized	5.50
CQA cycles if fully vectorized	5.50
Front-end cycles	2.63
P0 cycles	0.50
P1 cycles	0.50
P2 cycles	1.00
P3 cycles	1.00
P4 cycles	2.00
P5 cycles	1.00
P6 cycles	5.50
P7 cycles	5.50
P8 cycles	1.50
P9 cycles	1.50
P10 cycles	1.50
P11 cycles	1.50
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	0.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	21.00
Nb uops	21.00
Nb loads	NA
Nb stores	1.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	17.45
Bytes prefetched	0.00
Bytes loaded	64.00
Bytes stored	32.00
Stride 0	0.00
Stride 1	0.00
Stride n	0.00
Stride unknown	2.00
Stride indirect	0.00
Vectorization ratio all	94.12
Vectorization ratio load	100.00
Vectorization ratio store	100.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	92.86
Vector-efficiency ratio all	95.59
Vector-efficiency ratio load	100.00
Vector-efficiency ratio store	100.00
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	94.64

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	2.10
Bottlenecks	P6, P7,
Function	main
Source	random.tcc:412-417
Source loop unroll info	multi-versionned
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	5.50
CQA cycles if no scalar integer	5.50
CQA cycles if FP arith vectorized	5.50
CQA cycles if fully vectorized	5.50
Front-end cycles	2.63
P0 cycles	0.50
P1 cycles	0.50
P2 cycles	1.00
P3 cycles	1.00
P4 cycles	2.00
P5 cycles	1.00
P6 cycles	5.50
P7 cycles	5.50
P8 cycles	1.50
P9 cycles	1.50
P10 cycles	1.50
P11 cycles	1.50
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	0.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	21.00
Nb uops	21.00
Nb loads	NA
Nb stores	1.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	17.45
Bytes prefetched	0.00
Bytes loaded	64.00
Bytes stored	32.00
Stride 0	0.00
Stride 1	0.00
Stride n	0.00
Stride unknown	2.00
Stride indirect	0.00
Vectorization ratio all	94.12
Vectorization ratio load	100.00
Vectorization ratio store	100.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	92.86
Vector-efficiency ratio all	95.59
Vector-efficiency ratio load	100.00
Vector-efficiency ratio store	100.00
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	94.64

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	main
Source file and lines	random.tcc:412-417
Module	attention-armclang-native

The loop is defined in /usr/lib/gcc/aarch64-amazon-linux/14/../../../../include/c++/14/bits/random.tcc:412-417.

The related source loop is multi-versionned.

gain
potential
hint
expert

Vectorization

Your loop is highly vectorized. 95% of vector register length is used (average across all VPU instructions).

Details

94% of VPU instructions are used in vector version (process two or more data elements in vector registers):

92% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

No data for this section

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant unknown stride: 2 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 64 bytes. The binary loop is storing 32 bytes.

General properties

nb instructions	21
nb uops	21
loop length	84
used w registers	0
used x registers	8
used b registers	0
used h registers	0
used s registers	0
used d registers	0
used q registers	0
used v registers	0
used z registers	3
nb stack references	0

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	2.63 cycles
front end	2.63 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	0.50	0.50	1.00	1.00	2.00	1.00	5.50	5.50	1.50	1.50	1.50	1.50	0.00	0.00	0.00
cycles	0.50	0.50	1.00	1.00	2.00	1.00	5.50	5.50	1.50	1.50	1.50	1.50	0.00	0.00	0.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	2.63
Dispatch	5.50
Data deps.	1.00
Overall L1	5.50

Vectorization ratios

all	94%
load	100%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	92%

Vector efficiency ratios

all	95%
load	100%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	94%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 5.50 cycles. At this rate:

12% of peak load performance is reached (11.64 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
12% of peak store performance is reached (5.82 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 11920

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
ADD X10, X21, X9,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
ORR Z3.D, Z2.D, Z2.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
LD1D {Z2.D}, P1/Z, [X10, X16,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
SPLICE Z3.D, P2, Z3.D, Z2.D	1	0	0	0	0	0	0	0	1	0	0	0	0	3	1	vect (100.0%)
ORR Z4.D, Z2.D, Z2.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
AND Z4.D, Z4.D, #0x7ffffffe	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
AND Z3.D, Z3.D, #0x80000000	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
ORR Z3.D, Z4.D, Z3.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
ORR Z4.D, Z2.D, Z2.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
AND Z4.D, Z4.D, #0x1	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
LSR Z3.D, Z3.D, #63	1	0	0	0	0	0	0	0	1	0	0	0	0	2	1	vect (100.0%)
CMPEQ P0.D, P1/Z, Z4.D, #0	1	0	0	0	0	1	0	1	0	0	0	0	0	4	1	vect (100.0%)
LD1D {Z4.D}, P1/Z, [X21, X9,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
ADD X9, X9, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
CMP X14, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.33	N/A
EOR Z3.D, Z3.D, Z4.D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	2	0.25	vect (100.0%)
DUP Z4.D, X20	1	0	0	0	0	1	0	0	0	0	0	0	0	3	1	scal (25.0%)
EOR Z4.D, Z3.D, Z4.D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	2	0.25	vect (100.0%)
SEL Z3.D, P0, Z3.D, Z4.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
ST1D {Z3.D}, P1, [X10, X15,LSL #3]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	2	0.50	vect (100.0%)
B.NE 11920 <main+0x960>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Function	main
Source file and lines	random.tcc:412-417
Module	attention-armclang-native

The loop is defined in /usr/lib/gcc/aarch64-amazon-linux/14/../../../../include/c++/14/bits/random.tcc:412-417.

The related source loop is multi-versionned.

gain
potential
hint
expert

Vectorization

Your loop is highly vectorized. 95% of vector register length is used (average across all VPU instructions).

Details

94% of VPU instructions are used in vector version (process two or more data elements in vector registers):

92% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

No data for this section

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant unknown stride: 2 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 64 bytes. The binary loop is storing 32 bytes.

General properties

nb instructions	21
nb uops	21
loop length	84
used w registers	0
used x registers	8
used b registers	0
used h registers	0
used s registers	0
used d registers	0
used q registers	0
used v registers	0
used z registers	3
nb stack references	0

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	2.63 cycles
front end	2.63 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	0.50	0.50	1.00	1.00	2.00	1.00	5.50	5.50	1.50	1.50	1.50	1.50	0.00	0.00	0.00
cycles	0.50	0.50	1.00	1.00	2.00	1.00	5.50	5.50	1.50	1.50	1.50	1.50	0.00	0.00	0.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	2.63
Dispatch	5.50
Data deps.	1.00
Overall L1	5.50

Vectorization ratios

all	94%
load	100%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	92%

Vector efficiency ratios

all	95%
load	100%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	94%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 5.50 cycles. At this rate:

12% of peak load performance is reached (11.64 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
12% of peak store performance is reached (5.82 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 11920

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
ADD X10, X21, X9,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
ORR Z3.D, Z2.D, Z2.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
LD1D {Z2.D}, P1/Z, [X10, X16,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
SPLICE Z3.D, P2, Z3.D, Z2.D	1	0	0	0	0	0	0	0	1	0	0	0	0	3	1	vect (100.0%)
ORR Z4.D, Z2.D, Z2.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
AND Z4.D, Z4.D, #0x7ffffffe	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
AND Z3.D, Z3.D, #0x80000000	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
ORR Z3.D, Z4.D, Z3.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
ORR Z4.D, Z2.D, Z2.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
AND Z4.D, Z4.D, #0x1	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
LSR Z3.D, Z3.D, #63	1	0	0	0	0	0	0	0	1	0	0	0	0	2	1	vect (100.0%)
CMPEQ P0.D, P1/Z, Z4.D, #0	1	0	0	0	0	1	0	1	0	0	0	0	0	4	1	vect (100.0%)
LD1D {Z4.D}, P1/Z, [X21, X9,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
ADD X9, X9, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
CMP X14, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.33	N/A
EOR Z3.D, Z3.D, Z4.D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	2	0.25	vect (100.0%)
DUP Z4.D, X20	1	0	0	0	0	1	0	0	0	0	0	0	0	3	1	scal (25.0%)
EOR Z4.D, Z3.D, Z4.D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	2	0.25	vect (100.0%)
SEL Z3.D, P0, Z3.D, Z4.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
ST1D {Z3.D}, P1, [X10, X15,LSL #3]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	2	0.50	vect (100.0%)
B.NE 11920 <main+0x960>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Report Configuration

Vectorization

Details

Slow data structures access

Details

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Slow data structures access

Details

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code