OV - attention-armclang-native - Loop 82 - attention-armclang-native

	Loop Id: 82	Module: attention-armclang-native	Source: random.tcc:404-409	Coverage: 0.15%

0x11820 LD1D	{Z3.D}, P2/Z, [X9, X14,LSL #3]    [1]

0x11824 ADD	X11, X9, X15

0x11828 LD1D	{Z7.D}, P2/Z, [X11, X16,LSL #3]    [2]

0x1182c SPLICE	Z2.D, P3, Z2.D, Z3.D

0x11830 ORR	Z4.D, Z3.D, Z3.D

0x11834 ORR	Z5.D, Z3.D, Z3.D

0x11838 AND	Z3.D, Z3.D, #0x1

0x1183c AND	Z4.D, Z4.D, #0x7ffffffe

0x11840 CMPEQ	P0.D, P2/Z, Z3.D, #0

0x11844 DUP	Z3.D, X20

0x11848 AND	Z2.D, Z2.D, #0x80000000

0x1184c ORR	Z4.D, Z4.D, Z2.D

0x11850 LD1D	{Z2.D}, P2/Z, [X11, X14,LSL #3]    [2]

0x11854 LSR	Z4.D, Z4.D, #63

0x11858 SPLICE	Z5.D, P3, Z5.D, Z2.D

0x1185c ORR	Z6.D, Z2.D, Z2.D

0x11860 AND	Z6.D, Z6.D, #0x7ffffffe

0x11864 AND	Z5.D, Z5.D, #0x80000000

0x11868 ORR	Z5.D, Z6.D, Z5.D

0x1186c LD1D	{Z6.D}, P2/Z, [X9, X16,LSL #3]    [1]

0x11870 LSR	Z5.D, Z5.D, #63

0x11874 EOR	Z5.D, Z5.D, Z7.D

0x11878 EOR	Z4.D, Z4.D, Z6.D

0x1187c ORR	Z6.D, Z2.D, Z2.D

0x11880 AND	Z6.D, Z6.D, #0x1

0x11884 CMPEQ	P1.D, P2/Z, Z6.D, #0

0x11888 EOR	Z6.D, Z4.D, Z3.D

0x1188c EOR	Z3.D, Z5.D, Z3.D

0x11890 SUBS	X10, X10, X12

0x11894 SEL	Z4.D, P0, Z4.D, Z6.D

0x11898 SEL	Z3.D, P1, Z5.D, Z3.D

0x1189c STR	Z4, [X9, MUL VL]    [1]

0x118a0 STR	Z3, [X9, #1, MUL VL]    [1]

0x118a4 ADD	X9, X9, X13

0x118a8 B.NE	11820

/usr/lib/gcc/aarch64-amazon-linux/14/../../../../include/c++/14/bits/random.tcc: 404 - 409

--------------------------------------------------------------------------------

404:       for (size_t __k = 0; __k < (__n - __m); ++__k)

405:         {

406: 	  _UIntType __y = ((_M_x[__k] & __upper_mask)

407: 			   | (_M_x[__k + 1] & __lower_mask));

408: 	  _M_x[__k] = (_M_x[__k + __m] ^ (__y >> 1)

409: 		       ^ ((__y & 0x01) ? __a : 0));

Coverage (%)	Name	Module
►100.00+	__libc_start_call_main	libc.so.6
○	__libc_start_main	libc.so.6
○	_start	attention-armclang-native

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	2.29
Bottlenecks	P6, P7,
Function	main
Source	random.tcc:404-409
Source loop unroll info	multi-versionned
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	10.00
CQA cycles if no scalar integer	10.00
CQA cycles if FP arith vectorized	10.00
CQA cycles if fully vectorized	10.00
Front-end cycles	4.38
P0 cycles	0.50
P1 cycles	0.50
P2 cycles	1.00
P3 cycles	1.00
P4 cycles	3.00
P5 cycles	1.00
P6 cycles	10.00
P7 cycles	10.00
P8 cycles	3.00
P9 cycles	3.00
P10 cycles	3.00
P11 cycles	3.00
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	0.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	35.00
Nb uops	35.00
Nb loads	NA
Nb stores	2.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	19.20
Bytes prefetched	0.00
Bytes loaded	128.00
Bytes stored	64.00
Stride 0	0.00
Stride 1	0.00
Stride n	0.00
Stride unknown	2.00
Stride indirect	0.00
Vectorization ratio all	93.75
Vectorization ratio load	100.00
Vectorization ratio store	100.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	96.00
Vector-efficiency ratio all	95.31
Vector-efficiency ratio load	100.00
Vector-efficiency ratio store	100.00
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	25.00
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	97.00

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	2.29
Bottlenecks	P6, P7,
Function	main
Source	random.tcc:404-409
Source loop unroll info	multi-versionned
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	10.00
CQA cycles if no scalar integer	10.00
CQA cycles if FP arith vectorized	10.00
CQA cycles if fully vectorized	10.00
Front-end cycles	4.38
P0 cycles	0.50
P1 cycles	0.50
P2 cycles	1.00
P3 cycles	1.00
P4 cycles	3.00
P5 cycles	1.00
P6 cycles	10.00
P7 cycles	10.00
P8 cycles	3.00
P9 cycles	3.00
P10 cycles	3.00
P11 cycles	3.00
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	0.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	35.00
Nb uops	35.00
Nb loads	NA
Nb stores	2.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	19.20
Bytes prefetched	0.00
Bytes loaded	128.00
Bytes stored	64.00
Stride 0	0.00
Stride 1	0.00
Stride n	0.00
Stride unknown	2.00
Stride indirect	0.00
Vectorization ratio all	93.75
Vectorization ratio load	100.00
Vectorization ratio store	100.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	96.00
Vector-efficiency ratio all	95.31
Vector-efficiency ratio load	100.00
Vector-efficiency ratio store	100.00
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	25.00
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	97.00

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	main
Source file and lines	random.tcc:404-409
Module	attention-armclang-native

The loop is defined in /usr/lib/gcc/aarch64-amazon-linux/14/../../../../include/c++/14/bits/random.tcc:404-409.

The related source loop is multi-versionned.

gain
potential
hint
expert

Vectorization

Your loop is highly vectorized. 95% of vector register length is used (average across all VPU instructions).

Details

93% of VPU instructions are used in vector version (process two or more data elements in vector registers):

0% of VPU addition or subtraction instructions are used in vector version.
96% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

No data for this section

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant unknown stride: 2 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 128 bytes. The binary loop is storing 64 bytes.

General properties

nb instructions	35
nb uops	35
loop length	140
used w registers	0
used x registers	9
used b registers	0
used h registers	0
used s registers	0
used d registers	0
used q registers	0
used v registers	0
used z registers	6
nb stack references	0

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	4.38 cycles
front end	4.38 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	0.50	0.50	1.00	1.00	3.00	1.00	10.00	10.00	3.00	3.00	3.00	3.00	0.00	0.00	0.00
cycles	0.50	0.50	1.00	1.00	3.00	1.00	10.00	10.00	3.00	3.00	3.00	3.00	0.00	0.00	0.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	4.38
Dispatch	10.00
Data deps.	1.00
Overall L1	10.00

Vectorization ratios

all	93%
load	100%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	96%

Vector efficiency ratios

all	95%
load	100%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	25%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	97%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 10.00 cycles. At this rate:

13% of peak load performance is reached (12.80 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
13% of peak store performance is reached (6.40 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 11820

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
LD1D {Z3.D}, P2/Z, [X9, X14,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
ADD X11, X9, X15	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
LD1D {Z7.D}, P2/Z, [X11, X16,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
SPLICE Z2.D, P3, Z2.D, Z3.D	1	0	0	0	0	0	0	0	1	0	0	0	0	3	1	vect (100.0%)
ORR Z4.D, Z3.D, Z3.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
ORR Z5.D, Z3.D, Z3.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
AND Z3.D, Z3.D, #0x1	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
AND Z4.D, Z4.D, #0x7ffffffe	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
CMPEQ P0.D, P2/Z, Z3.D, #0	1	0	0	0	0	1	0	1	0	0	0	0	0	4	1	vect (100.0%)
DUP Z3.D, X20	1	0	0	0	0	1	0	0	0	0	0	0	0	3	1	scal (25.0%)
AND Z2.D, Z2.D, #0x80000000	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
ORR Z4.D, Z4.D, Z2.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
LD1D {Z2.D}, P2/Z, [X11, X14,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
LSR Z4.D, Z4.D, #63	1	0	0	0	0	0	0	0	1	0	0	0	0	2	1	vect (100.0%)
SPLICE Z5.D, P3, Z5.D, Z2.D	1	0	0	0	0	0	0	0	1	0	0	0	0	3	1	vect (100.0%)
ORR Z6.D, Z2.D, Z2.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
AND Z6.D, Z6.D, #0x7ffffffe	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
AND Z5.D, Z5.D, #0x80000000	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
ORR Z5.D, Z6.D, Z5.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
LD1D {Z6.D}, P2/Z, [X9, X16,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
LSR Z5.D, Z5.D, #63	1	0	0	0	0	0	0	0	1	0	0	0	0	2	1	vect (100.0%)
EOR Z5.D, Z5.D, Z7.D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	2	0.25	vect (100.0%)
EOR Z4.D, Z4.D, Z6.D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	2	0.25	vect (100.0%)
ORR Z6.D, Z2.D, Z2.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
AND Z6.D, Z6.D, #0x1	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
CMPEQ P1.D, P2/Z, Z6.D, #0	1	0	0	0	0	1	0	1	0	0	0	0	0	4	1	vect (100.0%)
EOR Z6.D, Z4.D, Z3.D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	2	0.25	vect (100.0%)
EOR Z3.D, Z5.D, Z3.D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	2	0.25	vect (100.0%)
SUBS X10, X10, X12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.33	scal (25.0%)
SEL Z4.D, P0, Z4.D, Z6.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
SEL Z3.D, P1, Z5.D, Z3.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
STR Z4, [X9, MUL VL]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	2	0.50	vect (100.0%)
STR Z3, [X9, #1, MUL VL]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	2	0.50	vect (100.0%)
ADD X9, X9, X13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
B.NE 11820 <main+0x860>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Function	main
Source file and lines	random.tcc:404-409
Module	attention-armclang-native

The loop is defined in /usr/lib/gcc/aarch64-amazon-linux/14/../../../../include/c++/14/bits/random.tcc:404-409.

The related source loop is multi-versionned.

gain
potential
hint
expert

Vectorization

Your loop is highly vectorized. 95% of vector register length is used (average across all VPU instructions).

Details

93% of VPU instructions are used in vector version (process two or more data elements in vector registers):

0% of VPU addition or subtraction instructions are used in vector version.
96% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

No data for this section

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant unknown stride: 2 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 128 bytes. The binary loop is storing 64 bytes.

General properties

nb instructions	35
nb uops	35
loop length	140
used w registers	0
used x registers	9
used b registers	0
used h registers	0
used s registers	0
used d registers	0
used q registers	0
used v registers	0
used z registers	6
nb stack references	0

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	4.38 cycles
front end	4.38 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	0.50	0.50	1.00	1.00	3.00	1.00	10.00	10.00	3.00	3.00	3.00	3.00	0.00	0.00	0.00
cycles	0.50	0.50	1.00	1.00	3.00	1.00	10.00	10.00	3.00	3.00	3.00	3.00	0.00	0.00	0.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	4.38
Dispatch	10.00
Data deps.	1.00
Overall L1	10.00

Vectorization ratios

all	93%
load	100%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	96%

Vector efficiency ratios

all	95%
load	100%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	25%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	97%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 10.00 cycles. At this rate:

13% of peak load performance is reached (12.80 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
13% of peak store performance is reached (6.40 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 11820

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
LD1D {Z3.D}, P2/Z, [X9, X14,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
ADD X11, X9, X15	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
LD1D {Z7.D}, P2/Z, [X11, X16,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
SPLICE Z2.D, P3, Z2.D, Z3.D	1	0	0	0	0	0	0	0	1	0	0	0	0	3	1	vect (100.0%)
ORR Z4.D, Z3.D, Z3.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
ORR Z5.D, Z3.D, Z3.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
AND Z3.D, Z3.D, #0x1	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
AND Z4.D, Z4.D, #0x7ffffffe	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
CMPEQ P0.D, P2/Z, Z3.D, #0	1	0	0	0	0	1	0	1	0	0	0	0	0	4	1	vect (100.0%)
DUP Z3.D, X20	1	0	0	0	0	1	0	0	0	0	0	0	0	3	1	scal (25.0%)
AND Z2.D, Z2.D, #0x80000000	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
ORR Z4.D, Z4.D, Z2.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
LD1D {Z2.D}, P2/Z, [X11, X14,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
LSR Z4.D, Z4.D, #63	1	0	0	0	0	0	0	0	1	0	0	0	0	2	1	vect (100.0%)
SPLICE Z5.D, P3, Z5.D, Z2.D	1	0	0	0	0	0	0	0	1	0	0	0	0	3	1	vect (100.0%)
ORR Z6.D, Z2.D, Z2.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
AND Z6.D, Z6.D, #0x7ffffffe	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
AND Z5.D, Z5.D, #0x80000000	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
ORR Z5.D, Z6.D, Z5.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
LD1D {Z6.D}, P2/Z, [X9, X16,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
LSR Z5.D, Z5.D, #63	1	0	0	0	0	0	0	0	1	0	0	0	0	2	1	vect (100.0%)
EOR Z5.D, Z5.D, Z7.D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	2	0.25	vect (100.0%)
EOR Z4.D, Z4.D, Z6.D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	2	0.25	vect (100.0%)
ORR Z6.D, Z2.D, Z2.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
AND Z6.D, Z6.D, #0x1	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
CMPEQ P1.D, P2/Z, Z6.D, #0	1	0	0	0	0	1	0	1	0	0	0	0	0	4	1	vect (100.0%)
EOR Z6.D, Z4.D, Z3.D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	2	0.25	vect (100.0%)
EOR Z3.D, Z5.D, Z3.D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	2	0.25	vect (100.0%)
SUBS X10, X10, X12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.33	scal (25.0%)
SEL Z4.D, P0, Z4.D, Z6.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
SEL Z3.D, P1, Z5.D, Z3.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
STR Z4, [X9, MUL VL]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	2	0.50	vect (100.0%)
STR Z3, [X9, #1, MUL VL]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	2	0.50	vect (100.0%)
ADD X9, X9, X13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
B.NE 11820 <main+0x860>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Report Configuration

Vectorization

Details

Slow data structures access

Details

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Slow data structures access

Details

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code