OV - attention-armclang-native - Loop 81 - attention-armclang-native

	Loop Id: 81	Module: attention-armclang-native	Source: random.tcc:404-3368 [...]	Coverage: 0.10%

0x11760 LDR	X9, [SP, #5608]

0x11764 LDR	X10, [SP, #624]

0x11768 LDR	X11, [SP, #3792]

0x1176c ORR	X27, XZR, XZR

0x11770 AND	X9, X9, #0x0

0x11774 AND	X12, X10, #0x0

0x11778 SBFM	X10, X10, #0, #0

0x1177c ORR	X9, X12, X9

0x11780 AND	X10, X10, X20

0x11784 EOR	X9, X11, X9,LSR #1

0x11788 EOR	X9, X9, X10

0x1178c STR	X9, [SP, #5608]

0x11790 ORR	X9, XZR, X27

0x11794 ADD	X27, X27, #1

0x11798 SUBS	X8, X8, #1

0x1179c STR	X27, [SP, #5616]

0x117a0 LDR	X9, [X21, X9,LSL #3]

0x117a4 UBFM	X10, X9, #11, #42

0x117a8 EOR	X9, X10, X9

0x117ac MOVZ	W10, #22144

0x117b0 MOVK	W10, #40236

0x117b4 AND	X10, X10, X9,LSL #7

0x117b8 EOR	X9, X10, X9

0x117bc MOVZ	W10, #61382

0x117c0 AND	X10, X10, X9,LSL #15

0x117c4 EOR	X9, X10, X9

0x117c8 EOR	X9, X9, X9,LSR #18

0x117cc UCVTF	S2, X9

0x117d0 MOVZ	W9, #20352

0x117d4 FMADD	S0, S2, S1, S0

0x117d8 FMOV	S2, W9

0x117dc FMUL	S1, S1, S2

0x117e0 B.EQ	119e0

0x117e4 CMP	X27, #624

0x117e8 B.CC	11790

0x117ec PTRUE	P2.D, ALL

0x117f0 ADD	X9, SP, #120

0x117f4 SUB	X11, X29, #32

0x117f8 LDR	X10, [SP, #560]

0x117fc MOVZ	X14, #1

0x11800 MOVZ	X16, #397

0x11804 LD1RD	{Z2.D}, P2/Z, [X9, #63]

0x11808 CNTW	X12, ALL

0x1180c LDR	P3, [X11, #511, MUL VL]

0x11810 RDVL	X13, #2

0x11814 ADD	X9, SP, #624

0x11818 RDVL	X15, #1

0x1181c HINT	#0

  (82) 0x11820 LD1D	{Z3.D}, P2/Z, [X9, X14,LSL #3]

  (82) 0x11824 ADD	X11, X9, X15

  (82) 0x11828 LD1D	{Z7.D}, P2/Z, [X11, X16,LSL #3]

  (82) 0x1182c SPLICE	Z2.D, P3, Z2.D, Z3.D

  (82) 0x11830 ORR	Z4.D, Z3.D, Z3.D

  (82) 0x11834 ORR	Z5.D, Z3.D, Z3.D

  (82) 0x11838 AND	Z3.D, Z3.D, #0x1

  (82) 0x1183c AND	Z4.D, Z4.D, #0x7ffffffe

  (82) 0x11840 CMPEQ	P0.D, P2/Z, Z3.D, #0

  (82) 0x11844 DUP	Z3.D, X20

  (82) 0x11848 AND	Z2.D, Z2.D, #0x80000000

  (82) 0x1184c ORR	Z4.D, Z4.D, Z2.D

  (82) 0x11850 LD1D	{Z2.D}, P2/Z, [X11, X14,LSL #3]

  (82) 0x11854 LSR	Z4.D, Z4.D, #63

  (82) 0x11858 SPLICE	Z5.D, P3, Z5.D, Z2.D

  (82) 0x1185c ORR	Z6.D, Z2.D, Z2.D

  (82) 0x11860 AND	Z6.D, Z6.D, #0x7ffffffe

  (82) 0x11864 AND	Z5.D, Z5.D, #0x80000000

  (82) 0x11868 ORR	Z5.D, Z6.D, Z5.D

  (82) 0x1186c LD1D	{Z6.D}, P2/Z, [X9, X16,LSL #3]

  (82) 0x11870 LSR	Z5.D, Z5.D, #63

  (82) 0x11874 EOR	Z5.D, Z5.D, Z7.D

  (82) 0x11878 EOR	Z4.D, Z4.D, Z6.D

  (82) 0x1187c ORR	Z6.D, Z2.D, Z2.D

  (82) 0x11880 AND	Z6.D, Z6.D, #0x1

  (82) 0x11884 CMPEQ	P1.D, P2/Z, Z6.D, #0

  (82) 0x11888 EOR	Z6.D, Z4.D, Z3.D

  (82) 0x1188c EOR	Z3.D, Z5.D, Z3.D

  (82) 0x11890 SUBS	X10, X10, X12

  (82) 0x11894 SEL	Z4.D, P0, Z4.D, Z6.D

  (82) 0x11898 SEL	Z3.D, P1, Z5.D, Z3.D

  (82) 0x1189c STR	Z4, [X9, MUL VL]

  (82) 0x118a0 STR	Z3, [X9, #1, MUL VL]

  (82) 0x118a4 ADD	X9, X9, X13

  (82) 0x118a8 B.NE	11820

0x118ac LDR	X9, [SP, #504]

0x118b0 LDR	X10, [SP, #552]

0x118b4 LDR	X14, [SP, #568]

0x118b8 MOVZ	X15, #227

0x118bc MOVZ	X16, #228

0x118c0 WHILELS	P0.D, XZR, X9

0x118c4 LASTB	X9, P0, Z2.D

  (83) 0x118c8 ADD	X11, X21, X10

  (83) 0x118cc AND	X12, X9, #0x0

  (83) 0x118d0 ADD	X10, X10, #8

  (83) 0x118d4 LDR	X9, [X11, #8]

  (83) 0x118d8 CMP	X10, #1816

  (83) 0x118dc AND	X13, X9, #0x0

  (83) 0x118e0 ORR	X12, X13, X12

  (83) 0x118e4 LDR	X13, [X11, #3176]

  (83) 0x118e8 EOR	X12, X13, X12,LSR #1

  (83) 0x118ec SBFM	X13, X9, #0, #0

  (83) 0x118f0 AND	X13, X13, X20

  (83) 0x118f4 EOR	X12, X12, X13

  (83) 0x118f8 STR	X12, [X11]

  (83) 0x118fc B.NE	118c8

0x11900 PTRUE	P1.D, ALL

0x11904 ADD	X10, X21, #1816

0x11908 ORR	X9, XZR, XZR

0x1190c LD1RD	{Z2.D}, P1/Z, [X10]

0x11910 SUB	X10, X29, #32

0x11914 CNTD	X11, ALL

0x11918 LDR	P2, [X10, #511, MUL VL]

0x1191c HINT	#0

  (84) 0x11920 ADD	X10, X21, X9,LSL #3

  (84) 0x11924 ORR	Z3.D, Z2.D, Z2.D

  (84) 0x11928 LD1D	{Z2.D}, P1/Z, [X10, X16,LSL #3]

  (84) 0x1192c SPLICE	Z3.D, P2, Z3.D, Z2.D

  (84) 0x11930 ORR	Z4.D, Z2.D, Z2.D

  (84) 0x11934 AND	Z4.D, Z4.D, #0x7ffffffe

  (84) 0x11938 AND	Z3.D, Z3.D, #0x80000000

  (84) 0x1193c ORR	Z3.D, Z4.D, Z3.D

  (84) 0x11940 ORR	Z4.D, Z2.D, Z2.D

  (84) 0x11944 AND	Z4.D, Z4.D, #0x1

  (84) 0x11948 LSR	Z3.D, Z3.D, #63

  (84) 0x1194c CMPEQ	P0.D, P1/Z, Z4.D, #0

  (84) 0x11950 LD1D	{Z4.D}, P1/Z, [X21, X9,LSL #3]

  (84) 0x11954 ADD	X9, X9, X11

  (84) 0x11958 CMP	X14, X9

  (84) 0x1195c EOR	Z3.D, Z3.D, Z4.D

  (84) 0x11960 DUP	Z4.D, X20

  (84) 0x11964 EOR	Z4.D, Z3.D, Z4.D

  (84) 0x11968 SEL	Z3.D, P0, Z3.D, Z4.D

  (84) 0x1196c ST1D	{Z3.D}, P1, [X10, X15,LSL #3]

  (84) 0x11970 B.NE	11920

0x11974 CMP	X14, #396

0x11978 B.EQ	11760

0x1197c LDR	X9, [SP, #504]

0x11980 ADD	X10, X21, X14,LSL #3

0x11984 SUB	X11, X14, #396

0x11988 WHILELS	P0.D, XZR, X9

0x1198c LASTB	X9, P0, Z2.D

0x11990 HINT	#0

0x11994 HINT	#0

0x11998 HINT	#0

0x1199c HINT	#0

  (85) 0x119a0 AND	X12, X9, #0x0

  (85) 0x119a4 LDR	X9, [X10, #1824]

  (85) 0x119a8 ADDS	X11, X11, #1

  (85) 0x119ac AND	X13, X9, #0x0

  (85) 0x119b0 ORR	X12, X13, X12

  (85) 0x119b4 LDR	X13, [X10]

  (85) 0x119b8 EOR	X12, X13, X12,LSR #1

  (85) 0x119bc SBFM	X13, X9, #0, #0

  (85) 0x119c0 AND	X13, X13, X20

  (85) 0x119c4 EOR	X12, X12, X13

  (85) 0x119c8 STR	X12, [X10, #1816]

  (85) 0x119cc ADD	X10, X10, #8

  (85) 0x119d0 B.CC	119a0

0x119d4 B	11760

/usr/lib/gcc/aarch64-amazon-linux/14/../../../../include/c++/14/bits/random.tcc: 404 - 3368

--------------------------------------------------------------------------------

404:       for (size_t __k = 0; __k < (__n - __m); ++__k)

405:         {

406: 	  _UIntType __y = ((_M_x[__k] & __upper_mask)

407: 			   | (_M_x[__k + 1] & __lower_mask));

408: 	  _M_x[__k] = (_M_x[__k + __m] ^ (__y >> 1)

409: 		       ^ ((__y & 0x01) ? __a : 0));

410:         }

411:

412:       for (size_t __k = (__n - __m); __k < (__n - 1); ++__k)

413: 	{

414: 	  _UIntType __y = ((_M_x[__k] & __upper_mask)

415: 			   | (_M_x[__k + 1] & __lower_mask));

416: 	  _M_x[__k] = (_M_x[__k + (__m - __n)] ^ (__y >> 1)

417: 		       ^ ((__y & 0x01) ? __a : 0));

418: 	}

419:

420:       _UIntType __y = ((_M_x[__n - 1] & __upper_mask)

421: 		       | (_M_x[0] & __lower_mask));

422:       _M_x[__n - 1] = (_M_x[__m - 1] ^ (__y >> 1)

423: 		       ^ ((__y & 0x01) ? __a : 0));

[...]

458:       if (_M_p >= state_size)

459: 	_M_gen_rand();

460:

461:       // Calculate o(x(i)).

462:       result_type __z = _M_x[_M_p++];

463:       __z ^= (__z >> __u) & __d;

464:       __z ^= (__z << __s) & __b;

465:       __z ^= (__z << __t) & __c;

466:       __z ^= (__z >> __l);

[...]

3365:       for (size_t __k = __m; __k != 0; --__k)

3366: 	{

3367: 	  __sum += _RealType(__urng() - __urng.min()) * __tmp;

3368: 	  __tmp *= __r;

Coverage (%)	Name	Module
►100.00+	__libc_start_call_main	libc.so.6
○	__libc_start_main	libc.so.6
○	_start	attention-armclang-native

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	2.04
CQA speedup if FP arith vectorized	2.51
CQA speedup if fully vectorized	1.23
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.42
Bottlenecks	P2, P3, P4, P5,
Function	main
Source	random.tcc:404-404,random.tcc:412-414,random.tcc:420-423,random.tcc:458-458,random.tcc:462-466,random.tcc:3365-3368
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	12.25
CQA cycles if no scalar integer	6.00
CQA cycles if FP arith vectorized	4.88
CQA cycles if fully vectorized	10.00
Front-end cycles	8.63
P0 cycles	2.00
P1 cycles	2.00
P2 cycles	12.25
P3 cycles	12.25
P4 cycles	12.25
P5 cycles	12.25
P6 cycles	1.00
P7 cycles	2.00
P8 cycles	1.00
P9 cycles	1.00
P10 cycles	5.00
P11 cycles	5.00
P12 cycles	5.00
P13 cycles	1.00
P14 cycles	1.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	75.00
Nb uops	69.00
Nb loads	NA
Nb stores	2.00
Nb stack references	10.00
FLOP/cycle	0.24
Nb FLOP add-sub	0.00
Nb FLOP mul	1.00
Nb FLOP fma	1.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	0.65
Bytes prefetched	0.00
Bytes loaded	8.00
Bytes stored	0.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	0.00
Vectorization ratio add_sub	0.00
Vectorization ratio fma	0.00
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	28.37
Vector-efficiency ratio load	20.00
Vector-efficiency ratio store	25.00
Vector-efficiency ratio mul	12.50
Vector-efficiency ratio add_sub	25.00
Vector-efficiency ratio fma	12.50
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	34.17

Metric	Value
CQA speedup if no scalar integer	2.04
CQA speedup if FP arith vectorized	2.51
CQA speedup if fully vectorized	1.23
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.42
Bottlenecks	P2, P3, P4, P5,
Function	main
Source	random.tcc:404-404,random.tcc:412-414,random.tcc:420-423,random.tcc:458-458,random.tcc:462-466,random.tcc:3365-3368
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	12.25
CQA cycles if no scalar integer	6.00
CQA cycles if FP arith vectorized	4.88
CQA cycles if fully vectorized	10.00
Front-end cycles	8.63
P0 cycles	2.00
P1 cycles	2.00
P2 cycles	12.25
P3 cycles	12.25
P4 cycles	12.25
P5 cycles	12.25
P6 cycles	1.00
P7 cycles	2.00
P8 cycles	1.00
P9 cycles	1.00
P10 cycles	5.00
P11 cycles	5.00
P12 cycles	5.00
P13 cycles	1.00
P14 cycles	1.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	75.00
Nb uops	69.00
Nb loads	NA
Nb stores	2.00
Nb stack references	10.00
FLOP/cycle	0.24
Nb FLOP add-sub	0.00
Nb FLOP mul	1.00
Nb FLOP fma	1.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	0.65
Bytes prefetched	0.00
Bytes loaded	8.00
Bytes stored	0.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	0.00
Vectorization ratio add_sub	0.00
Vectorization ratio fma	0.00
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	28.37
Vector-efficiency ratio load	20.00
Vector-efficiency ratio store	25.00
Vector-efficiency ratio mul	12.50
Vector-efficiency ratio add_sub	25.00
Vector-efficiency ratio fma	12.50
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	34.17

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	main
Source file and lines	random.tcc:404-3368
Module	attention-armclang-native

The loop is defined in /usr/lib/gcc/aarch64-amazon-linux/14/../../../../include/c++/14/bits/random.tcc:404-423,458-466,3365-3368.

Analyzed code is defined in /usr/lib/gcc/aarch64-amazon-linux/14/../../../../include/c++/14/bits/random.tcc:404,412-414,420-423,458,462-466,3365-3368.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Failed to get the number of paths
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 12.25 to 6.00 cycles (2.04x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is not vectorized. Only 28% of vector register length is used (average across all VPU instructions). By vectorizing your loop, you can lower the cost of an iteration from 12.25 to 10.00 cycles (1.23x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ffast-math (included in Ofast) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

FMA

Detected 1 FMA (fused multiply-add) operations.

Conversion instructions

Detected expensive conversion instructions.

Details

UCVTF: 1 occurrences►
- /usr/lib/gcc/aarch64-amazon-linux/14/../../../../include/c++/14/bits/random.tcc:3367

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 3 FP arithmetical operations:

1: addition or subtraction (all inside FMA instructions)
2: multiply (1 inside FMA instructions)

The binary loop is loading 8 bytes.

Arithmetic intensity

Arithmetic intensity is 0.37 FP operations per loaded or stored byte.

General properties

nb instructions	75
nb uops	69
loop length	300
used w registers	2
used x registers	14
used b registers	0
used h registers	0
used s registers	4
used d registers	0
used q registers	0
used v registers	0
used z registers	1
nb stack references	10

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	8.63 cycles
front end	8.63 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	2.00	2.00	12.25	12.25	12.25	12.25	1.00	2.00	1.00	1.00	5.00	5.00	5.00	1.00	1.00
cycles	2.00	2.00	12.25	12.25	12.25	12.25	1.00	2.00	1.00	1.00	5.00	5.00	5.00	1.00	1.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	8.63
Dispatch	12.25
Overall L1	12.25

Vectorization ratios

INT

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	0%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

INT+FP

all	0%
load	0%
store	0%
mul	0%
add-sub	0%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

INT

all	30%
load	20%
store	25%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	25%
fma	NA (no fma vectorizable/vectorized instructions)
other	35%

all	12%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	12%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	12%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	12%

INT+FP

all	28%
load	20%
store	25%
mul	12%
add-sub	25%
fma	12%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	34%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 12.25 cycles. At this rate:

0% of peak load performance is reached (0.65 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 117e4

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput	Vectorization
LDR X9, [SP, #5608]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X10, [SP, #624]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X11, [SP, #3792]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ORR X27, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
AND X9, X9, #0x0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
AND X12, X10, #0x0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
SBFM X10, X10, #0, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR X9, X12, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
AND X10, X10, X20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
EOR X9, X11, X9,LSR #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
EOR X9, X9, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR X9, [SP, #5608]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ORR X9, XZR, X27	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X27, X27, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
SUBS X8, X8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
STR X27, [SP, #5616]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X9, [X21, X9,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
UBFM X10, X9, #11, #42	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
EOR X9, X10, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVZ W10, #22144	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVK W10, #40236	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
AND X10, X10, X9,LSL #7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
EOR X9, X10, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVZ W10, #61382	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
AND X10, X10, X9,LSL #15	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
EOR X9, X10, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
EOR X9, X9, X9,LSR #18	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
UCVTF S2, X9	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (25.0%)
MOVZ W9, #20352	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
FMADD S0, S2, S1, S0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25	scal (12.5%)
FMOV S2, W9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (12.5%)
FMUL S1, S1, S2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	scal (12.5%)
B.EQ 119e0 <main+0xa20>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X27, #624	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.CC 11790 <main+0x7d0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PTRUE P2.D, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (100.0%)
ADD X9, SP, #120	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SUB X11, X29, #32	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X10, [SP, #560]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
MOVZ X14, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
MOVZ X16, #397	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
LD1RD {Z2.D}, P2/Z, [X9, #63]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	6	0.50	scal (25.0%)
CNTW X12, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
LDR P3, [X11, #511, MUL VL]	1	0	0	0	0	0.50	0.50	0	0	0	0	0.50	0.50	0	0	0	6	0.50	scal (12.5%)
RDVL X13, #2	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
ADD X9, SP, #624	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
RDVL X15, #1	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
HINT #0																			N/A
LDR X9, [SP, #504]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X10, [SP, #552]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X14, [SP, #568]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
MOVZ X15, #227	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
MOVZ X16, #228	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
WHILELS P0.D, XZR, X9	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	2	N/A
LASTB X9, P0, Z2.D	1	0	0	0	0	1	0	0	1	0	0	0	0	0	0	0	6	1	N/A
PTRUE P1.D, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (100.0%)
ADD X10, X21, #1816	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR X9, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LD1RD {Z2.D}, P1/Z, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	6	0.50	scal (25.0%)
SUB X10, X29, #32	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CNTD X11, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
LDR P2, [X10, #511, MUL VL]	1	0	0	0	0	0.50	0.50	0	0	0	0	0.50	0.50	0	0	0	6	0.50	scal (12.5%)
HINT #0																			N/A
CMP X14, #396	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 11760 <main+0x7a0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X9, [SP, #504]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X10, X21, X14,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SUB X11, X14, #396	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
WHILELS P0.D, XZR, X9	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	2	N/A
LASTB X9, P0, Z2.D	1	0	0	0	0	1	0	0	1	0	0	0	0	0	0	0	6	1	N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
B 11760 <main+0x7a0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Function	main
Source file and lines	random.tcc:404-3368
Module	attention-armclang-native

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Failed to get the number of paths
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 12.25 to 6.00 cycles (2.04x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ffast-math (included in Ofast) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

FMA

Detected 1 FMA (fused multiply-add) operations.

Conversion instructions

Detected expensive conversion instructions.

Details

UCVTF: 1 occurrences►
- /usr/lib/gcc/aarch64-amazon-linux/14/../../../../include/c++/14/bits/random.tcc:3367

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 3 FP arithmetical operations:

1: addition or subtraction (all inside FMA instructions)
2: multiply (1 inside FMA instructions)

The binary loop is loading 8 bytes.

Arithmetic intensity

Arithmetic intensity is 0.37 FP operations per loaded or stored byte.

General properties

nb instructions	75
nb uops	69
loop length	300
used w registers	2
used x registers	14
used b registers	0
used h registers	0
used s registers	4
used d registers	0
used q registers	0
used v registers	0
used z registers	1
nb stack references	10

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	8.63 cycles
front end	8.63 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	2.00	2.00	12.25	12.25	12.25	12.25	1.00	2.00	1.00	1.00	5.00	5.00	5.00	1.00	1.00
cycles	2.00	2.00	12.25	12.25	12.25	12.25	1.00	2.00	1.00	1.00	5.00	5.00	5.00	1.00	1.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	8.63
Dispatch	12.25
Overall L1	12.25

Vectorization ratios

INT

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	0%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

INT+FP

all	0%
load	0%
store	0%
mul	0%
add-sub	0%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

INT

all	30%
load	20%
store	25%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	25%
fma	NA (no fma vectorizable/vectorized instructions)
other	35%

all	12%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	12%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	12%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	12%

INT+FP

all	28%
load	20%
store	25%
mul	12%
add-sub	25%
fma	12%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	34%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 12.25 cycles. At this rate:

0% of peak load performance is reached (0.65 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 117e4

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput	Vectorization
LDR X9, [SP, #5608]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X10, [SP, #624]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X11, [SP, #3792]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ORR X27, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
AND X9, X9, #0x0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
AND X12, X10, #0x0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
SBFM X10, X10, #0, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR X9, X12, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
AND X10, X10, X20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
EOR X9, X11, X9,LSR #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
EOR X9, X9, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR X9, [SP, #5608]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ORR X9, XZR, X27	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X27, X27, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
SUBS X8, X8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
STR X27, [SP, #5616]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X9, [X21, X9,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
UBFM X10, X9, #11, #42	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
EOR X9, X10, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVZ W10, #22144	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVK W10, #40236	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
AND X10, X10, X9,LSL #7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
EOR X9, X10, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVZ W10, #61382	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
AND X10, X10, X9,LSL #15	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
EOR X9, X10, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
EOR X9, X9, X9,LSR #18	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
UCVTF S2, X9	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (25.0%)
MOVZ W9, #20352	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
FMADD S0, S2, S1, S0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25	scal (12.5%)
FMOV S2, W9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (12.5%)
FMUL S1, S1, S2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	scal (12.5%)
B.EQ 119e0 <main+0xa20>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X27, #624	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.CC 11790 <main+0x7d0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PTRUE P2.D, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (100.0%)
ADD X9, SP, #120	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SUB X11, X29, #32	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X10, [SP, #560]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
MOVZ X14, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
MOVZ X16, #397	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
LD1RD {Z2.D}, P2/Z, [X9, #63]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	6	0.50	scal (25.0%)
CNTW X12, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
LDR P3, [X11, #511, MUL VL]	1	0	0	0	0	0.50	0.50	0	0	0	0	0.50	0.50	0	0	0	6	0.50	scal (12.5%)
RDVL X13, #2	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
ADD X9, SP, #624	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
RDVL X15, #1	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
HINT #0																			N/A
LDR X9, [SP, #504]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X10, [SP, #552]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X14, [SP, #568]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
MOVZ X15, #227	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
MOVZ X16, #228	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
WHILELS P0.D, XZR, X9	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	2	N/A
LASTB X9, P0, Z2.D	1	0	0	0	0	1	0	0	1	0	0	0	0	0	0	0	6	1	N/A
PTRUE P1.D, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (100.0%)
ADD X10, X21, #1816	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR X9, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LD1RD {Z2.D}, P1/Z, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	6	0.50	scal (25.0%)
SUB X10, X29, #32	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CNTD X11, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
LDR P2, [X10, #511, MUL VL]	1	0	0	0	0	0.50	0.50	0	0	0	0	0.50	0.50	0	0	0	6	0.50	scal (12.5%)
HINT #0																			N/A
CMP X14, #396	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 11760 <main+0x7a0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X9, [SP, #504]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X10, X21, X14,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SUB X11, X14, #396	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
WHILELS P0.D, XZR, X9	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	2	N/A
LASTB X9, P0, Z2.D	1	0	0	0	0	1	0	0	1	0	0	0	0	0	0	0	6	1	N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
B 11760 <main+0x7a0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

FMA

Conversion instructions

Details

Workaround

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

FMA

Conversion instructions

Details

Workaround

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code