OV - attention-armclang-native - Loop 80 - attention-armclang-native

	Loop Id: 80	Module: attention-armclang-native	Source: attention_v2.cpp:163-163 [...]	Coverage: 0.65%

0x11740 MOVI	D0, #0

0x11744 FMOV	S1, #1.0000000

0x11748 ORR	X8, XZR, X0

0x1174c B	117e4

  (81) 0x11760 LDR	X9, [SP, #5608]

  (81) 0x11764 LDR	X10, [SP, #624]

  (81) 0x11768 LDR	X11, [SP, #3792]

  (81) 0x1176c ORR	X27, XZR, XZR

  (81) 0x11770 AND	X9, X9, #0x0

  (81) 0x11774 AND	X12, X10, #0x0

  (81) 0x11778 SBFM	X10, X10, #0, #0

  (81) 0x1177c ORR	X9, X12, X9

  (81) 0x11780 AND	X10, X10, X20

  (81) 0x11784 EOR	X9, X11, X9,LSR #1

  (81) 0x11788 EOR	X9, X9, X10

  (81) 0x1178c STR	X9, [SP, #5608]

  (81) 0x11790 ORR	X9, XZR, X27

  (81) 0x11794 ADD	X27, X27, #1

  (81) 0x11798 SUBS	X8, X8, #1

  (81) 0x1179c STR	X27, [SP, #5616]

  (81) 0x117a0 LDR	X9, [X21, X9,LSL #3]

  (81) 0x117a4 UBFM	X10, X9, #11, #42

  (81) 0x117a8 EOR	X9, X10, X9

  (81) 0x117ac MOVZ	W10, #22144

  (81) 0x117b0 MOVK	W10, #40236

  (81) 0x117b4 AND	X10, X10, X9,LSL #7

  (81) 0x117b8 EOR	X9, X10, X9

  (81) 0x117bc MOVZ	W10, #61382

  (81) 0x117c0 AND	X10, X10, X9,LSL #15

  (81) 0x117c4 EOR	X9, X10, X9

  (81) 0x117c8 EOR	X9, X9, X9,LSR #18

  (81) 0x117cc UCVTF	S2, X9

  (81) 0x117d0 MOVZ	W9, #20352

  (81) 0x117d4 FMADD	S0, S2, S1, S0

  (81) 0x117d8 FMOV	S2, W9

  (81) 0x117dc FMUL	S1, S1, S2

  (81) 0x117e0 B.EQ	119e0

  (81) 0x117e4 CMP	X27, #624

  (81) 0x117e8 B.CC	11790

  (81) 0x117ec PTRUE	P2.D, ALL

  (81) 0x117f0 ADD	X9, SP, #120

  (81) 0x117f4 SUB	X11, X29, #32

  (81) 0x117f8 LDR	X10, [SP, #560]

  (81) 0x117fc MOVZ	X14, #1

  (81) 0x11800 MOVZ	X16, #397

  (81) 0x11804 LD1RD	{Z2.D}, P2/Z, [X9, #63]

  (81) 0x11808 CNTW	X12, ALL

  (81) 0x1180c LDR	P3, [X11, #511, MUL VL]

  (81) 0x11810 RDVL	X13, #2

  (81) 0x11814 ADD	X9, SP, #624

  (81) 0x11818 RDVL	X15, #1

  (81) 0x1181c HINT	#0

    (82) 0x11820 LD1D	{Z3.D}, P2/Z, [X9, X14,LSL #3]

    (82) 0x11824 ADD	X11, X9, X15

    (82) 0x11828 LD1D	{Z7.D}, P2/Z, [X11, X16,LSL #3]

    (82) 0x1182c SPLICE	Z2.D, P3, Z2.D, Z3.D

    (82) 0x11830 ORR	Z4.D, Z3.D, Z3.D

    (82) 0x11834 ORR	Z5.D, Z3.D, Z3.D

    (82) 0x11838 AND	Z3.D, Z3.D, #0x1

    (82) 0x1183c AND	Z4.D, Z4.D, #0x7ffffffe

    (82) 0x11840 CMPEQ	P0.D, P2/Z, Z3.D, #0

    (82) 0x11844 DUP	Z3.D, X20

    (82) 0x11848 AND	Z2.D, Z2.D, #0x80000000

    (82) 0x1184c ORR	Z4.D, Z4.D, Z2.D

    (82) 0x11850 LD1D	{Z2.D}, P2/Z, [X11, X14,LSL #3]

    (82) 0x11854 LSR	Z4.D, Z4.D, #63

    (82) 0x11858 SPLICE	Z5.D, P3, Z5.D, Z2.D

    (82) 0x1185c ORR	Z6.D, Z2.D, Z2.D

    (82) 0x11860 AND	Z6.D, Z6.D, #0x7ffffffe

    (82) 0x11864 AND	Z5.D, Z5.D, #0x80000000

    (82) 0x11868 ORR	Z5.D, Z6.D, Z5.D

    (82) 0x1186c LD1D	{Z6.D}, P2/Z, [X9, X16,LSL #3]

    (82) 0x11870 LSR	Z5.D, Z5.D, #63

    (82) 0x11874 EOR	Z5.D, Z5.D, Z7.D

    (82) 0x11878 EOR	Z4.D, Z4.D, Z6.D

    (82) 0x1187c ORR	Z6.D, Z2.D, Z2.D

    (82) 0x11880 AND	Z6.D, Z6.D, #0x1

    (82) 0x11884 CMPEQ	P1.D, P2/Z, Z6.D, #0

    (82) 0x11888 EOR	Z6.D, Z4.D, Z3.D

    (82) 0x1188c EOR	Z3.D, Z5.D, Z3.D

    (82) 0x11890 SUBS	X10, X10, X12

    (82) 0x11894 SEL	Z4.D, P0, Z4.D, Z6.D

    (82) 0x11898 SEL	Z3.D, P1, Z5.D, Z3.D

    (82) 0x1189c STR	Z4, [X9, MUL VL]

    (82) 0x118a0 STR	Z3, [X9, #1, MUL VL]

    (82) 0x118a4 ADD	X9, X9, X13

    (82) 0x118a8 B.NE	11820

  (81) 0x118ac LDR	X9, [SP, #504]

  (81) 0x118b0 LDR	X10, [SP, #552]

  (81) 0x118b4 LDR	X14, [SP, #568]

  (81) 0x118b8 MOVZ	X15, #227

  (81) 0x118bc MOVZ	X16, #228

  (81) 0x118c0 WHILELS	P0.D, XZR, X9

  (81) 0x118c4 LASTB	X9, P0, Z2.D

    (83) 0x118c8 ADD	X11, X21, X10

    (83) 0x118cc AND	X12, X9, #0x0

    (83) 0x118d0 ADD	X10, X10, #8

    (83) 0x118d4 LDR	X9, [X11, #8]

    (83) 0x118d8 CMP	X10, #1816

    (83) 0x118dc AND	X13, X9, #0x0

    (83) 0x118e0 ORR	X12, X13, X12

    (83) 0x118e4 LDR	X13, [X11, #3176]

    (83) 0x118e8 EOR	X12, X13, X12,LSR #1

    (83) 0x118ec SBFM	X13, X9, #0, #0

    (83) 0x118f0 AND	X13, X13, X20

    (83) 0x118f4 EOR	X12, X12, X13

    (83) 0x118f8 STR	X12, [X11]

    (83) 0x118fc B.NE	118c8

  (81) 0x11900 PTRUE	P1.D, ALL

  (81) 0x11904 ADD	X10, X21, #1816

  (81) 0x11908 ORR	X9, XZR, XZR

  (81) 0x1190c LD1RD	{Z2.D}, P1/Z, [X10]

  (81) 0x11910 SUB	X10, X29, #32

  (81) 0x11914 CNTD	X11, ALL

  (81) 0x11918 LDR	P2, [X10, #511, MUL VL]

  (81) 0x1191c HINT	#0

    (84) 0x11920 ADD	X10, X21, X9,LSL #3

    (84) 0x11924 ORR	Z3.D, Z2.D, Z2.D

    (84) 0x11928 LD1D	{Z2.D}, P1/Z, [X10, X16,LSL #3]

    (84) 0x1192c SPLICE	Z3.D, P2, Z3.D, Z2.D

    (84) 0x11930 ORR	Z4.D, Z2.D, Z2.D

    (84) 0x11934 AND	Z4.D, Z4.D, #0x7ffffffe

    (84) 0x11938 AND	Z3.D, Z3.D, #0x80000000

    (84) 0x1193c ORR	Z3.D, Z4.D, Z3.D

    (84) 0x11940 ORR	Z4.D, Z2.D, Z2.D

    (84) 0x11944 AND	Z4.D, Z4.D, #0x1

    (84) 0x11948 LSR	Z3.D, Z3.D, #63

    (84) 0x1194c CMPEQ	P0.D, P1/Z, Z4.D, #0

    (84) 0x11950 LD1D	{Z4.D}, P1/Z, [X21, X9,LSL #3]

    (84) 0x11954 ADD	X9, X9, X11

    (84) 0x11958 CMP	X14, X9

    (84) 0x1195c EOR	Z3.D, Z3.D, Z4.D

    (84) 0x11960 DUP	Z4.D, X20

    (84) 0x11964 EOR	Z4.D, Z3.D, Z4.D

    (84) 0x11968 SEL	Z3.D, P0, Z3.D, Z4.D

    (84) 0x1196c ST1D	{Z3.D}, P1, [X10, X15,LSL #3]

    (84) 0x11970 B.NE	11920

  (81) 0x11974 CMP	X14, #396

  (81) 0x11978 B.EQ	11760

  (81) 0x1197c LDR	X9, [SP, #504]

  (81) 0x11980 ADD	X10, X21, X14,LSL #3

  (81) 0x11984 SUB	X11, X14, #396

  (81) 0x11988 WHILELS	P0.D, XZR, X9

  (81) 0x1198c LASTB	X9, P0, Z2.D

  (81) 0x11990 HINT	#0

  (81) 0x11994 HINT	#0

  (81) 0x11998 HINT	#0

  (81) 0x1199c HINT	#0

    (85) 0x119a0 AND	X12, X9, #0x0

    (85) 0x119a4 LDR	X9, [X10, #1824]

    (85) 0x119a8 ADDS	X11, X11, #1

    (85) 0x119ac AND	X13, X9, #0x0

    (85) 0x119b0 ORR	X12, X13, X12

    (85) 0x119b4 LDR	X13, [X10]

    (85) 0x119b8 EOR	X12, X13, X12,LSR #1

    (85) 0x119bc SBFM	X13, X9, #0, #0

    (85) 0x119c0 AND	X13, X13, X20

    (85) 0x119c4 EOR	X12, X12, X13

    (85) 0x119c8 STR	X12, [X10, #1816]

    (85) 0x119cc ADD	X10, X10, #8

    (85) 0x119d0 B.CC	119a0

  (81) 0x119d4 B	11760

0x119e0 FDIV	S0, S0, S1

0x119e4 FCMP	S0, S10

0x119e8 B.GE	11a04

0x119ec LDR	X8, [SP, #352]

0x119f0 STR	S0, [X19, X18,LSL #2]

0x119f4 ADD	X18, X18, #1

0x119f8 CMP	X18, X8

0x119fc B.NE	11740

0x11a04 FMOV	S0, #1.0000000

0x11a08 MOVI	D1, #0

0x11a0c STR	X17, [SP, #576]

0x11a10 STR	X18, [SP, #512]

0x11a14 STR	X0, [SP, #464]

0x11a18 BL	10140

0x11a1c LDR	X0, [SP, #464]

0x11a20 LDR	X18, [SP, #512]

0x11a24 LDR	X17, [SP, #576]

0x11a28 LDR	X8, [SP, #352]

0x11a2c STR	S0, [X19, X18,LSL #2]

0x11a30 ADD	X18, X18, #1

0x11a34 CMP	X18, X8

0x11a38 B.NE	11740

/usr/lib/gcc/aarch64-amazon-linux/14/../../../../include/c++/14/cmath: 2622 - 2622

--------------------------------------------------------------------------------

2622:   { return __builtin_nextafterf(__x, __y); }

/home/eoseret/llm-attention/attention_v2.cpp: 163 - 163

--------------------------------------------------------------------------------

163:       for (size_t i = 0; i < elemsX; ++i) h_X[i] = dist(rng);

/usr/lib/gcc/aarch64-amazon-linux/14/../../../../include/c++/14/bits/random.tcc: 404 - 3371

--------------------------------------------------------------------------------

404:       for (size_t __k = 0; __k < (__n - __m); ++__k)

405:         {

406: 	  _UIntType __y = ((_M_x[__k] & __upper_mask)

407: 			   | (_M_x[__k + 1] & __lower_mask));

408: 	  _M_x[__k] = (_M_x[__k + __m] ^ (__y >> 1)

409: 		       ^ ((__y & 0x01) ? __a : 0));

410:         }

411:

412:       for (size_t __k = (__n - __m); __k < (__n - 1); ++__k)

413: 	{

414: 	  _UIntType __y = ((_M_x[__k] & __upper_mask)

415: 			   | (_M_x[__k + 1] & __lower_mask));

416: 	  _M_x[__k] = (_M_x[__k + (__m - __n)] ^ (__y >> 1)

417: 		       ^ ((__y & 0x01) ? __a : 0));

418: 	}

419:

420:       _UIntType __y = ((_M_x[__n - 1] & __upper_mask)

421: 		       | (_M_x[0] & __lower_mask));

422:       _M_x[__n - 1] = (_M_x[__m - 1] ^ (__y >> 1)

423: 		       ^ ((__y & 0x01) ? __a : 0));

[...]

458:       if (_M_p >= state_size)

459: 	_M_gen_rand();

460:

461:       // Calculate o(x(i)).

462:       result_type __z = _M_x[_M_p++];

463:       __z ^= (__z >> __u) & __d;

464:       __z ^= (__z << __s) & __b;

465:       __z ^= (__z << __t) & __c;

466:       __z ^= (__z >> __l);

[...]

3365:       for (size_t __k = __m; __k != 0; --__k)

3366: 	{

3367: 	  __sum += _RealType(__urng() - __urng.min()) * __tmp;

3368: 	  __tmp *= __r;

3369: 	}

3370:       __ret = __sum / __tmp;

3371:       if (__builtin_expect(__ret >= _RealType(1), 0))

Coverage (%)	Name	Module
►100.00+	__libc_start_call_main	libc.so.6
○	__libc_start_main	libc.so.6
○	_start	attention-armclang-native

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	2.10
CQA speedup if FP arith vectorized	1.40
CQA speedup if fully vectorized	5.60
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.05
Bottlenecks	P10,
Function	main
Source	cmath:2622-2622,attention_v2.cpp:163-163,random.tcc:3370-3371
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	3.50
CQA cycles if no scalar integer	1.67
CQA cycles if FP arith vectorized	2.50
CQA cycles if fully vectorized	0.63
Front-end cycles	3.25
P0 cycles	2.50
P1 cycles	2.50
P2 cycles	1.50
P3 cycles	1.50
P4 cycles	1.50
P5 cycles	1.50
P6 cycles	2.00
P7 cycles	2.00
P8 cycles	2.00
P9 cycles	2.00
P10 cycles	3.50
P11 cycles	3.17
P12 cycles	3.33
P13 cycles	1.50
P14 cycles	1.50
DIV/SQRT cycles	0.87 - 1.13
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	26.00
Nb uops	26.00
Nb loads	NA
Nb stores	5.00
Nb stack references	8.00
FLOP/cycle	0.29
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	1.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	1.71
Bytes prefetched	0.00
Bytes loaded	0.00
Bytes stored	6.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	0.00
Vectorization ratio other	0.00
Vector-efficiency ratio all	19.64
Vector-efficiency ratio load	25.00
Vector-efficiency ratio store	20.00
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	12.50
Vector-efficiency ratio other	18.75

Metric	Value
CQA speedup if no scalar integer	2.10
CQA speedup if FP arith vectorized	1.40
CQA speedup if fully vectorized	5.60
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.05
Bottlenecks	P10,
Function	main
Source	cmath:2622-2622,attention_v2.cpp:163-163,random.tcc:3370-3371
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	3.50
CQA cycles if no scalar integer	1.67
CQA cycles if FP arith vectorized	2.50
CQA cycles if fully vectorized	0.63
Front-end cycles	3.25
P0 cycles	2.50
P1 cycles	2.50
P2 cycles	1.50
P3 cycles	1.50
P4 cycles	1.50
P5 cycles	1.50
P6 cycles	2.00
P7 cycles	2.00
P8 cycles	2.00
P9 cycles	2.00
P10 cycles	3.50
P11 cycles	3.17
P12 cycles	3.33
P13 cycles	1.50
P14 cycles	1.50
DIV/SQRT cycles	0.87 - 1.13
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	26.00
Nb uops	26.00
Nb loads	NA
Nb stores	5.00
Nb stack references	8.00
FLOP/cycle	0.29
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	1.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	1.71
Bytes prefetched	0.00
Bytes loaded	0.00
Bytes stored	6.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	0.00
Vectorization ratio other	0.00
Vector-efficiency ratio all	19.64
Vector-efficiency ratio load	25.00
Vector-efficiency ratio store	20.00
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	12.50
Vector-efficiency ratio other	18.75

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	main
Source file and lines	attention_v2.cpp:163-163
Module	attention-armclang-native

The loop is defined in:

/usr/lib/gcc/aarch64-amazon-linux/14/../../../../include/c++/14/cmath:2622
/home/eoseret/llm-attention/attention_v2.cpp:163
/usr/lib/gcc/aarch64-amazon-linux/14/../../../../include/c++/14/bits/random.tcc:404-423,458-466,3365-3371

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Failed to get the number of paths
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 3.50 to 1.67 cycles (2.10x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is not vectorized. Only 19% of vector register length is used (average across all VPU instructions). By vectorizing your loop, you can lower the cost of an iteration from 3.50 to 0.62 cycles (5.60x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ffast-math (included in Ofast) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

unknown: 1 occurrences►
- /usr/lib/gcc/aarch64-amazon-linux/14/../../../../include/c++/14/cmath:2622

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 1 FP arithmetical operations:

1: divide

The binary loop is storing 6 bytes.

Arithmetic intensity

Arithmetic intensity is 0.17 FP operations per loaded or stored byte.

General properties

nb instructions	26
nb uops	26
loop length	104
used w registers	0
used x registers	6
used b registers	0
used h registers	0
used s registers	4
used d registers	2
used q registers	0
used v registers	0
used z registers	0
nb stack references	8

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	3.25 cycles
front end	3.25 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	2.50	2.50	1.50	1.50	1.50	1.50	2.00	2.00	2.00	2.00	3.50	3.17	3.33	1.50	1.50
cycles	2.50	2.50	1.50	1.50	1.50	1.50	2.00	2.00	2.00	2.00	3.50	3.17	3.33	1.50	1.50

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

0.87-1.13

Cycles summary

Front-end	3.25
Dispatch	3.50
DIV/SQRT	0.87-1.13
Overall L1	3.50

Vectorization ratios

INT

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	0%

INT+FP

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	0%

Vector efficiency ratios

INT

all	22%
load	25%
store	20%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	25%

all	12%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	12%
other	12%

INT+FP

all	19%
load	25%
store	20%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	12%
other	18%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 3.50 cycles. At this rate:

3% of peak store performance is reached (1.71 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 11740

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput	Vectorization
MOVI D0, #0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
FMOV S1, #1.0000000	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (12.5%)
ORR X8, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
B 117e4 <main+0x824>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
FDIV S0, S0, S1	1	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	0	0	7-10	0.87-1.13	scal (12.5%)
FCMP S0, S10	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (12.5%)
B.GE 11a04 <main+0xa44>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X8, [SP, #352]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR S0, [X19, X18,LSL #2]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (12.5%)
ADD X18, X18, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP X18, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.NE 11740 <main+0x780>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
FMOV S0, #1.0000000	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (12.5%)
MOVI D1, #0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
STR X17, [SP, #576]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X18, [SP, #512]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X0, [SP, #464]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
BL 10140 <@plt_start@+0x120>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X0, [SP, #464]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X18, [SP, #512]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X17, [SP, #576]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X8, [SP, #352]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR S0, [X19, X18,LSL #2]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (12.5%)
ADD X18, X18, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP X18, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	N/A
B.NE 11740 <main+0x780>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Function	main
Source file and lines	attention_v2.cpp:163-163
Module	attention-armclang-native

The loop is defined in:

/usr/lib/gcc/aarch64-amazon-linux/14/../../../../include/c++/14/cmath:2622
/home/eoseret/llm-attention/attention_v2.cpp:163
/usr/lib/gcc/aarch64-amazon-linux/14/../../../../include/c++/14/bits/random.tcc:404-423,458-466,3365-3371

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Failed to get the number of paths
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 3.50 to 1.67 cycles (2.10x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ffast-math (included in Ofast) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

CALL instructions

Detected function call instructions.

Details

unknown: 1 occurrences►
- /usr/lib/gcc/aarch64-amazon-linux/14/../../../../include/c++/14/cmath:2622

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 1 FP arithmetical operations:

1: divide

The binary loop is storing 6 bytes.

Arithmetic intensity

Arithmetic intensity is 0.17 FP operations per loaded or stored byte.

General properties

nb instructions	26
nb uops	26
loop length	104
used w registers	0
used x registers	6
used b registers	0
used h registers	0
used s registers	4
used d registers	2
used q registers	0
used v registers	0
used z registers	0
nb stack references	8

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	3.25 cycles
front end	3.25 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	2.50	2.50	1.50	1.50	1.50	1.50	2.00	2.00	2.00	2.00	3.50	3.17	3.33	1.50	1.50
cycles	2.50	2.50	1.50	1.50	1.50	1.50	2.00	2.00	2.00	2.00	3.50	3.17	3.33	1.50	1.50

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

0.87-1.13

Cycles summary

Front-end	3.25
Dispatch	3.50
DIV/SQRT	0.87-1.13
Overall L1	3.50

Vectorization ratios

INT

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	0%

INT+FP

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	0%

Vector efficiency ratios

INT

all	22%
load	25%
store	20%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	25%

all	12%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	12%
other	12%

INT+FP

all	19%
load	25%
store	20%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	12%
other	18%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 3.50 cycles. At this rate:

3% of peak store performance is reached (1.71 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 11740

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput	Vectorization
MOVI D0, #0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
FMOV S1, #1.0000000	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (12.5%)
ORR X8, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
B 117e4 <main+0x824>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
FDIV S0, S0, S1	1	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	0	0	7-10	0.87-1.13	scal (12.5%)
FCMP S0, S10	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (12.5%)
B.GE 11a04 <main+0xa44>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X8, [SP, #352]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR S0, [X19, X18,LSL #2]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (12.5%)
ADD X18, X18, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP X18, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.NE 11740 <main+0x780>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
FMOV S0, #1.0000000	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (12.5%)
MOVI D1, #0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
STR X17, [SP, #576]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X18, [SP, #512]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X0, [SP, #464]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
BL 10140 <@plt_start@+0x120>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X0, [SP, #464]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X18, [SP, #512]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X17, [SP, #576]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X8, [SP, #352]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR S0, [X19, X18,LSL #2]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (12.5%)
ADD X18, X18, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP X18, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	N/A
B.NE 11740 <main+0x780>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

CALL instructions

Details

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

CALL instructions

Details

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code