OV - attention-armclang-native - Loop 70 - attention-armclang-native

	Loop Id: 70	Module: attention-armclang-native	Source: random.tcc:404-3368 [...]	Coverage: 0.10%

0x11d20 LDR	X9, [SP, #5608]

0x11d24 LDR	X10, [SP, #624]

0x11d28 LDR	X11, [SP, #3792]

0x11d2c ORR	X27, XZR, XZR

0x11d30 AND	X9, X9, #0x0

0x11d34 AND	X12, X10, #0x0

0x11d38 SBFM	X10, X10, #0, #0

0x11d3c ORR	X9, X12, X9

0x11d40 AND	X10, X10, X20

0x11d44 EOR	X9, X11, X9,LSR #1

0x11d48 EOR	X9, X9, X10

0x11d4c STR	X9, [SP, #5608]

0x11d50 ORR	X9, XZR, X27

0x11d54 ADD	X27, X27, #1

0x11d58 SUBS	X8, X8, #1

0x11d5c STR	X27, [SP, #5616]

0x11d60 LDR	X9, [X21, X9,LSL #3]

0x11d64 UBFM	X10, X9, #11, #42

0x11d68 EOR	X9, X10, X9

0x11d6c MOVZ	W10, #22144

0x11d70 MOVK	W10, #40236

0x11d74 AND	X10, X10, X9,LSL #7

0x11d78 EOR	X9, X10, X9

0x11d7c MOVZ	W10, #61382

0x11d80 AND	X10, X10, X9,LSL #15

0x11d84 EOR	X9, X10, X9

0x11d88 EOR	X9, X9, X9,LSR #18

0x11d8c UCVTF	S2, X9

0x11d90 MOVZ	W9, #20352

0x11d94 FMADD	S0, S2, S1, S0

0x11d98 FMOV	S2, W9

0x11d9c FMUL	S1, S1, S2

0x11da0 B.EQ	11fa0

0x11da4 CMP	X27, #624

0x11da8 B.CC	11d50

0x11dac PTRUE	P2.D, ALL

0x11db0 ADD	X9, SP, #120

0x11db4 SUB	X11, X29, #32

0x11db8 LDR	X10, [SP, #560]

0x11dbc MOVZ	X14, #1

0x11dc0 MOVZ	X16, #397

0x11dc4 LD1RD	{Z2.D}, P2/Z, [X9, #63]

0x11dc8 CNTW	X12, ALL

0x11dcc LDR	P3, [X11, #511, MUL VL]

0x11dd0 RDVL	X13, #2

0x11dd4 ADD	X9, SP, #624

0x11dd8 RDVL	X15, #1

0x11ddc HINT	#0

  (71) 0x11de0 LD1D	{Z3.D}, P2/Z, [X9, X14,LSL #3]

  (71) 0x11de4 ADD	X11, X9, X15

  (71) 0x11de8 LD1D	{Z7.D}, P2/Z, [X11, X16,LSL #3]

  (71) 0x11dec SPLICE	Z2.D, P3, Z2.D, Z3.D

  (71) 0x11df0 ORR	Z4.D, Z3.D, Z3.D

  (71) 0x11df4 ORR	Z5.D, Z3.D, Z3.D

  (71) 0x11df8 AND	Z3.D, Z3.D, #0x1

  (71) 0x11dfc AND	Z4.D, Z4.D, #0x7ffffffe

  (71) 0x11e00 CMPEQ	P0.D, P2/Z, Z3.D, #0

  (71) 0x11e04 DUP	Z3.D, X20

  (71) 0x11e08 AND	Z2.D, Z2.D, #0x80000000

  (71) 0x11e0c ORR	Z4.D, Z4.D, Z2.D

  (71) 0x11e10 LD1D	{Z2.D}, P2/Z, [X11, X14,LSL #3]

  (71) 0x11e14 LSR	Z4.D, Z4.D, #63

  (71) 0x11e18 SPLICE	Z5.D, P3, Z5.D, Z2.D

  (71) 0x11e1c ORR	Z6.D, Z2.D, Z2.D

  (71) 0x11e20 AND	Z6.D, Z6.D, #0x7ffffffe

  (71) 0x11e24 AND	Z5.D, Z5.D, #0x80000000

  (71) 0x11e28 ORR	Z5.D, Z6.D, Z5.D

  (71) 0x11e2c LD1D	{Z6.D}, P2/Z, [X9, X16,LSL #3]

  (71) 0x11e30 LSR	Z5.D, Z5.D, #63

  (71) 0x11e34 EOR	Z5.D, Z5.D, Z7.D

  (71) 0x11e38 EOR	Z4.D, Z4.D, Z6.D

  (71) 0x11e3c ORR	Z6.D, Z2.D, Z2.D

  (71) 0x11e40 AND	Z6.D, Z6.D, #0x1

  (71) 0x11e44 CMPEQ	P1.D, P2/Z, Z6.D, #0

  (71) 0x11e48 EOR	Z6.D, Z4.D, Z3.D

  (71) 0x11e4c EOR	Z3.D, Z5.D, Z3.D

  (71) 0x11e50 SUBS	X10, X10, X12

  (71) 0x11e54 SEL	Z4.D, P0, Z4.D, Z6.D

  (71) 0x11e58 SEL	Z3.D, P1, Z5.D, Z3.D

  (71) 0x11e5c STR	Z4, [X9, MUL VL]

  (71) 0x11e60 STR	Z3, [X9, #1, MUL VL]

  (71) 0x11e64 ADD	X9, X9, X13

  (71) 0x11e68 B.NE	11de0

0x11e6c SUB	X9, X29, #32

0x11e70 LDR	X10, [SP, #552]

0x11e74 LDR	X14, [SP, #568]

0x11e78 MOVZ	X15, #227

0x11e7c MOVZ	X16, #228

0x11e80 LDR	P0, [X9, #509, MUL VL]

0x11e84 LASTB	X9, P0, Z2.D

  (72) 0x11e88 ADD	X11, X21, X10

  (72) 0x11e8c AND	X12, X9, #0x0

  (72) 0x11e90 ADD	X10, X10, #8

  (72) 0x11e94 LDR	X9, [X11, #8]

  (72) 0x11e98 CMP	X10, #1816

  (72) 0x11e9c AND	X13, X9, #0x0

  (72) 0x11ea0 ORR	X12, X13, X12

  (72) 0x11ea4 LDR	X13, [X11, #3176]

  (72) 0x11ea8 EOR	X12, X13, X12,LSR #1

  (72) 0x11eac SBFM	X13, X9, #0, #0

  (72) 0x11eb0 AND	X13, X13, X20

  (72) 0x11eb4 EOR	X12, X12, X13

  (72) 0x11eb8 STR	X12, [X11]

  (72) 0x11ebc B.NE	11e88

0x11ec0 PTRUE	P1.D, ALL

0x11ec4 ADD	X10, X21, #1816

0x11ec8 ORR	X9, XZR, XZR

0x11ecc LD1RD	{Z2.D}, P1/Z, [X10]

0x11ed0 SUB	X10, X29, #32

0x11ed4 CNTD	X11, ALL

0x11ed8 LDR	P2, [X10, #511, MUL VL]

0x11edc HINT	#0

  (73) 0x11ee0 ADD	X10, X21, X9,LSL #3

  (73) 0x11ee4 ORR	Z3.D, Z2.D, Z2.D

  (73) 0x11ee8 LD1D	{Z2.D}, P1/Z, [X10, X16,LSL #3]

  (73) 0x11eec SPLICE	Z3.D, P2, Z3.D, Z2.D

  (73) 0x11ef0 ORR	Z4.D, Z2.D, Z2.D

  (73) 0x11ef4 AND	Z4.D, Z4.D, #0x7ffffffe

  (73) 0x11ef8 AND	Z3.D, Z3.D, #0x80000000

  (73) 0x11efc ORR	Z3.D, Z4.D, Z3.D

  (73) 0x11f00 ORR	Z4.D, Z2.D, Z2.D

  (73) 0x11f04 AND	Z4.D, Z4.D, #0x1

  (73) 0x11f08 LSR	Z3.D, Z3.D, #63

  (73) 0x11f0c CMPEQ	P0.D, P1/Z, Z4.D, #0

  (73) 0x11f10 LD1D	{Z4.D}, P1/Z, [X21, X9,LSL #3]

  (73) 0x11f14 ADD	X9, X9, X11

  (73) 0x11f18 CMP	X14, X9

  (73) 0x11f1c EOR	Z3.D, Z3.D, Z4.D

  (73) 0x11f20 DUP	Z4.D, X20

  (73) 0x11f24 EOR	Z4.D, Z3.D, Z4.D

  (73) 0x11f28 SEL	Z3.D, P0, Z3.D, Z4.D

  (73) 0x11f2c ST1D	{Z3.D}, P1, [X10, X15,LSL #3]

  (73) 0x11f30 B.NE	11ee0

0x11f34 CMP	X14, #396

0x11f38 B.EQ	11d20

0x11f3c SUB	X9, X29, #32

0x11f40 ADD	X10, X21, X14,LSL #3

0x11f44 SUB	X11, X14, #396

0x11f48 LDR	P0, [X9, #506, MUL VL]

0x11f4c LASTB	X9, P0, Z2.D

0x11f50 HINT	#0

0x11f54 HINT	#0

0x11f58 HINT	#0

0x11f5c HINT	#0

  (74) 0x11f60 AND	X12, X9, #0x0

  (74) 0x11f64 LDR	X9, [X10, #1824]

  (74) 0x11f68 ADDS	X11, X11, #1

  (74) 0x11f6c AND	X13, X9, #0x0

  (74) 0x11f70 ORR	X12, X13, X12

  (74) 0x11f74 LDR	X13, [X10]

  (74) 0x11f78 EOR	X12, X13, X12,LSR #1

  (74) 0x11f7c SBFM	X13, X9, #0, #0

  (74) 0x11f80 AND	X13, X13, X20

  (74) 0x11f84 EOR	X12, X12, X13

  (74) 0x11f88 STR	X12, [X10, #1816]

  (74) 0x11f8c ADD	X10, X10, #8

  (74) 0x11f90 B.CC	11f60

0x11f94 B	11d20

/usr/lib/gcc/aarch64-amazon-linux/14/../../../../include/c++/14/bits/random.tcc: 404 - 3368

--------------------------------------------------------------------------------

404:       for (size_t __k = 0; __k < (__n - __m); ++__k)

405:         {

406: 	  _UIntType __y = ((_M_x[__k] & __upper_mask)

407: 			   | (_M_x[__k + 1] & __lower_mask));

408: 	  _M_x[__k] = (_M_x[__k + __m] ^ (__y >> 1)

409: 		       ^ ((__y & 0x01) ? __a : 0));

410:         }

411:

412:       for (size_t __k = (__n - __m); __k < (__n - 1); ++__k)

413: 	{

414: 	  _UIntType __y = ((_M_x[__k] & __upper_mask)

415: 			   | (_M_x[__k + 1] & __lower_mask));

416: 	  _M_x[__k] = (_M_x[__k + (__m - __n)] ^ (__y >> 1)

417: 		       ^ ((__y & 0x01) ? __a : 0));

418: 	}

419:

420:       _UIntType __y = ((_M_x[__n - 1] & __upper_mask)

421: 		       | (_M_x[0] & __lower_mask));

422:       _M_x[__n - 1] = (_M_x[__m - 1] ^ (__y >> 1)

423: 		       ^ ((__y & 0x01) ? __a : 0));

[...]

458:       if (_M_p >= state_size)

459: 	_M_gen_rand();

460:

461:       // Calculate o(x(i)).

462:       result_type __z = _M_x[_M_p++];

463:       __z ^= (__z >> __u) & __d;

464:       __z ^= (__z << __s) & __b;

465:       __z ^= (__z << __t) & __c;

466:       __z ^= (__z >> __l);

[...]

3365:       for (size_t __k = __m; __k != 0; --__k)

3366: 	{

3367: 	  __sum += _RealType(__urng() - __urng.min()) * __tmp;

3368: 	  __tmp *= __r;

Coverage (%)	Name	Module
►100.00+	__libc_start_call_main	libc.so.6
○	__libc_start_main	libc.so.6
○	_start	attention-armclang-native

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	2.69
CQA speedup if FP arith vectorized	2.62
CQA speedup if fully vectorized	1.42
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.46
Bottlenecks
Function	main
Source	random.tcc:404-404,random.tcc:412-414,random.tcc:420-423,random.tcc:458-458,random.tcc:462-466,random.tcc:3365-3368
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	9.42
CQA cycles if no scalar integer	3.50
CQA cycles if FP arith vectorized	3.59
CQA cycles if fully vectorized	6.64
Front-end cycles	6.46
P0 cycles	1.50
P1 cycles	1.50
P2 cycles	9.42
P3 cycles	9.42
P4 cycles	9.42
P5 cycles	9.42
P6 cycles	0.92
P7 cycles	1.25
P8 cycles	0.92
P9 cycles	0.92
P10 cycles	3.56
P11 cycles	3.33
P12 cycles	3.44
P13 cycles	0.83
P14 cycles	0.83
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	3
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	54.33
Nb uops	51.67
Nb loads	NA
Nb stores	1.67
Nb stack references	5.67
FLOP/cycle	0.32
Nb FLOP add-sub	0.00
Nb FLOP mul	1.00
Nb FLOP fma	1.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	0.77
Bytes prefetched	0.00
Bytes loaded	9.33
Bytes stored	0.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	0.00
Vectorization ratio add_sub	0.00
Vectorization ratio fma	0.00
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	24.76
Vector-efficiency ratio load	17.08
Vector-efficiency ratio store	25.00
Vector-efficiency ratio mul	12.50
Vector-efficiency ratio add_sub	25.00
Vector-efficiency ratio fma	12.50
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	29.72

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	2.51
CQA speedup if fully vectorized	6.10
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.39
Bottlenecks	P2, P3, P4, P5,
Function	main
Source	random.tcc:404-404,random.tcc:412-414,random.tcc:420-423,random.tcc:458-458,random.tcc:462-466,random.tcc:3365-3368
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	4.00
CQA cycles if no scalar integer	4.00
CQA cycles if FP arith vectorized	1.59
CQA cycles if fully vectorized	0.66
Front-end cycles	2.88
P0 cycles	1.00
P1 cycles	1.00
P2 cycles	4.00
P3 cycles	4.00
P4 cycles	4.00
P5 cycles	4.00
P6 cycles	0.75
P7 cycles	0.75
P8 cycles	0.75
P9 cycles	0.75
P10 cycles	0.83
P11 cycles	0.50
P12 cycles	0.67
P13 cycles	0.50
P14 cycles	0.50
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	3
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	23.00
Nb uops	23.00
Nb loads	NA
Nb stores	1.00
Nb stack references	1.00
FLOP/cycle	0.75
Nb FLOP add-sub	0.00
Nb FLOP mul	1.00
Nb FLOP fma	1.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	0.00
Bytes prefetched	0.00
Bytes loaded	0.00
Bytes stored	0.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	NA
Vectorization ratio store	0.00
Vectorization ratio mul	0.00
Vectorization ratio add_sub	0.00
Vectorization ratio fma	0.00
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	18.75
Vector-efficiency ratio load	NA
Vector-efficiency ratio store	25.00
Vector-efficiency ratio mul	12.50
Vector-efficiency ratio add_sub	25.00
Vector-efficiency ratio fma	12.50
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	18.75

Metric	Value
CQA speedup if no scalar integer	3.64
CQA speedup if FP arith vectorized	2.72
CQA speedup if fully vectorized	1.27
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.48
Bottlenecks	P2, P3, P4, P5,
Function	main
Source	random.tcc:404-404,random.tcc:412-414,random.tcc:420-423,random.tcc:458-458,random.tcc:462-466,random.tcc:3365-3368
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	12.75
CQA cycles if no scalar integer	3.50
CQA cycles if FP arith vectorized	4.69
CQA cycles if fully vectorized	10.00
Front-end cycles	8.63
P0 cycles	2.00
P1 cycles	2.00
P2 cycles	12.75
P3 cycles	12.75
P4 cycles	12.75
P5 cycles	12.75
P6 cycles	1.00
P7 cycles	2.00
P8 cycles	1.00
P9 cycles	1.00
P10 cycles	5.00
P11 cycles	5.00
P12 cycles	5.00
P13 cycles	1.00
P14 cycles	1.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	3
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	75.00
Nb uops	69.00
Nb loads	NA
Nb stores	2.00
Nb stack references	8.00
FLOP/cycle	0.24
Nb FLOP add-sub	0.00
Nb FLOP mul	1.00
Nb FLOP fma	1.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	1.25
Bytes prefetched	0.00
Bytes loaded	16.00
Bytes stored	0.00
Stride 0	0.00
Stride 1	0.00
Stride n	0.00
Stride unknown	3.00
Stride indirect	3.00
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	0.00
Vectorization ratio add_sub	0.00
Vectorization ratio fma	0.00
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	27.40
Vector-efficiency ratio load	16.67
Vector-efficiency ratio store	25.00
Vector-efficiency ratio mul	12.50
Vector-efficiency ratio add_sub	25.00
Vector-efficiency ratio fma	12.50
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	34.82

Metric	Value
CQA speedup if no scalar integer	3.83
CQA speedup if FP arith vectorized	2.56
CQA speedup if fully vectorized	1.24
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.46
Bottlenecks	P2, P3, P4, P5,
Function	main
Source	random.tcc:404-404,random.tcc:412-414,random.tcc:420-423,random.tcc:458-458,random.tcc:462-466,random.tcc:3365-3368
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	11.50
CQA cycles if no scalar integer	3.00
CQA cycles if FP arith vectorized	4.50
CQA cycles if fully vectorized	9.25
Front-end cycles	7.88
P0 cycles	1.50
P1 cycles	1.50
P2 cycles	11.50
P3 cycles	11.50
P4 cycles	11.50
P5 cycles	11.50
P6 cycles	1.00
P7 cycles	1.00
P8 cycles	1.00
P9 cycles	1.00
P10 cycles	4.83
P11 cycles	4.50
P12 cycles	4.67
P13 cycles	1.00
P14 cycles	1.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	3
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	65.00
Nb uops	63.00
Nb loads	NA
Nb stores	2.00
Nb stack references	8.00
FLOP/cycle	0.26
Nb FLOP add-sub	0.00
Nb FLOP mul	1.00
Nb FLOP fma	1.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	1.04
Bytes prefetched	0.00
Bytes loaded	12.00
Bytes stored	0.00
Stride 0	0.00
Stride 1	0.00
Stride n	0.00
Stride unknown	2.00
Stride indirect	3.00
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	0.00
Vectorization ratio add_sub	0.00
Vectorization ratio fma	0.00
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	28.13
Vector-efficiency ratio load	17.50
Vector-efficiency ratio store	25.00
Vector-efficiency ratio mul	12.50
Vector-efficiency ratio add_sub	25.00
Vector-efficiency ratio fma	12.50
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	35.58

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	main
Source file and lines	random.tcc:404-3368
Module	attention-armclang-native

The loop is defined in /usr/lib/gcc/aarch64-amazon-linux/14/../../../../include/c++/14/bits/random.tcc:404-423,458-466,3365-3368.

Analyzed code is defined in /usr/lib/gcc/aarch64-amazon-linux/14/../../../../include/c++/14/bits/random.tcc:404,412-414,420-423,458,462-466,3365-3368.

Warnings:
Non-innermost loop: analyzing only self part (ignoring child loops).
This loop has 3 execution paths.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. Only 24% of vector register length is used (average across all VPU instructions). By vectorizing your loop, you can lower the cost of an iteration from 9.42 to 6.64 cycles (1.42x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ffast-math (included in Ofast) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

FMA

Detected 1 FMA (fused multiply-add) operations.

Conversion instructions

Detected expensive conversion instructions.

Details

UCVTF: 0 occurrences

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 3 FP arithmetical operations:

1: addition or subtraction (all inside FMA instructions)
2: multiply (1 inside FMA instructions)

The binary loop is loading 9 bytes.

Arithmetic intensity

Arithmetic intensity is 0.32 FP operations per loaded or stored byte.

General properties

nb instructions	54.33
nb uops	51.67
loop length	217.33
used w registers	2
used x registers	11.33
used b registers	0
used h registers	0
used s registers	4
used d registers	0
used q registers	0
used v registers	0
used z registers	0.67
nb stack references	5.67

Front-end

MACRO FUSION NOT POSSIBLE

micro-operation queue	6.46 cycles
front end	6.46 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	1.50	1.50	9.42	9.42	9.42	9.42	0.92	1.25	0.92	0.92	3.56	3.33	3.44	0.83	0.83
cycles	1.50	1.50	9.42	9.42	9.42	9.42	0.92	1.25	0.92	0.92	3.56	3.33	3.44	0.83	0.83

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	3.00

Cycles summary

Front-end	6.46
Dispatch	9.42
Data deps.	3.00
Overall L1	9.42

Vectorization ratios

INT

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	0%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

INT+FP

all	0%
load	0%
store	0%
mul	0%
add-sub	0%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

INT

all	26%
load	17%
store	25%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	25%
fma	NA (no fma vectorizable/vectorized instructions)
other	31%

all	12%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	12%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	12%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	12%

INT+FP

all	24%
load	17%
store	25%
mul	12%
add-sub	25%
fma	12%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	29%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 9.42 cycles. At this rate:

0% of peak load performance is reached (0.77 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))

Function	main
Source file and lines	random.tcc:404-3368
Module	attention-armclang-native

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. Only 18% of vector register length is used (average across all VPU instructions). By vectorizing your loop, you can lower the cost of an iteration from 4.00 to 0.66 cycles (6.10x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ffast-math (included in Ofast) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

FMA

Detected 1 FMA (fused multiply-add) operations.

Conversion instructions

Detected expensive conversion instructions.

Details

UCVTF: 1 occurrences►
- /usr/lib/gcc/aarch64-amazon-linux/14/../../../../include/c++/14/bits/random.tcc:3367

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 3 FP arithmetical operations:

1: addition or subtraction (all inside FMA instructions)
2: multiply (1 inside FMA instructions)

The binary loop does not load or store any data.

General properties

nb instructions	23
nb uops	23
loop length	92
used w registers	2
used x registers	6
used b registers	0
used h registers	0
used s registers	4
used d registers	0
used q registers	0
used v registers	0
used z registers	0
nb stack references	1

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	2.88 cycles
front end	2.88 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	1.00	1.00	4.00	4.00	4.00	4.00	0.75	0.75	0.75	0.75	0.83	0.50	0.67	0.50	0.50
cycles	1.00	1.00	4.00	4.00	4.00	4.00	0.75	0.75	0.75	0.75	0.83	0.50	0.67	0.50	0.50

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	3.00

Cycles summary

Front-end	2.88
Dispatch	4.00
Data deps.	3.00
Overall L1	4.00

Vectorization ratios

INT

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	0%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

INT+FP

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	0%
mul	0%
add-sub	0%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

INT

all	20%
load	NA (no load vectorizable/vectorized instructions)
store	25%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	25%
fma	NA (no fma vectorizable/vectorized instructions)
other	19%

all	12%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	12%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	12%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	12%

INT+FP

all	18%
load	NA (no load vectorizable/vectorized instructions)
store	25%
mul	12%
add-sub	25%
fma	12%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	18%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 4.00 cycles.

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 11da4

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput	Vectorization
ORR X9, XZR, X27	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X27, X27, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SUBS X8, X8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
STR X27, [SP, #5616]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X9, [X21, X9,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
UBFM X10, X9, #11, #42	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
EOR X9, X10, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVZ W10, #22144	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
MOVK W10, #40236	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
AND X10, X10, X9,LSL #7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
EOR X9, X10, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVZ W10, #61382	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
AND X10, X10, X9,LSL #15	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
EOR X9, X10, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
EOR X9, X9, X9,LSR #18	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
UCVTF S2, X9	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (25.0%)
MOVZ W9, #20352	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
FMADD S0, S2, S1, S0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25	scal (12.5%)
FMOV S2, W9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (12.5%)
FMUL S1, S1, S2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	scal (12.5%)
B.EQ 11fa0 <main+0xfe0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X27, #624	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	N/A
B.CC 11d50 <main+0xd90>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Function	main
Source file and lines	random.tcc:404-3368
Module	attention-armclang-native

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 12.75 to 3.50 cycles (3.64x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is not vectorized. Only 27% of vector register length is used (average across all VPU instructions). By vectorizing your loop, you can lower the cost of an iteration from 12.75 to 10.00 cycles (1.27x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ffast-math (included in Ofast) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

FMA

Detected 1 FMA (fused multiply-add) operations.

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant unknown stride: 3 occurrence(s)
Irregular (variable stride) or indirect: 3 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)
Try to remove indirect accesses. If applicable, precompute elements out of the innermost loop.

Conversion instructions

Detected expensive conversion instructions.

Details

UCVTF: 1 occurrences►
- /usr/lib/gcc/aarch64-amazon-linux/14/../../../../include/c++/14/bits/random.tcc:3367

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 3 FP arithmetical operations:

1: addition or subtraction (all inside FMA instructions)
2: multiply (1 inside FMA instructions)

The binary loop is loading 16 bytes.

Arithmetic intensity

Arithmetic intensity is 0.19 FP operations per loaded or stored byte.

General properties

nb instructions	75
nb uops	69
loop length	300
used w registers	2
used x registers	14
used b registers	0
used h registers	0
used s registers	4
used d registers	0
used q registers	0
used v registers	0
used z registers	1
nb stack references	8

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	8.63 cycles
front end	8.63 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	2.00	2.00	12.75	12.75	12.75	12.75	1.00	2.00	1.00	1.00	5.00	5.00	5.00	1.00	1.00
cycles	2.00	2.00	12.75	12.75	12.75	12.75	1.00	2.00	1.00	1.00	5.00	5.00	5.00	1.00	1.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	3.00

Cycles summary

Front-end	8.63
Dispatch	12.75
Data deps.	3.00
Overall L1	12.75

Vectorization ratios

INT

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	0%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

INT+FP

all	0%
load	0%
store	0%
mul	0%
add-sub	0%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

INT

all	29%
load	16%
store	25%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	25%
fma	NA (no fma vectorizable/vectorized instructions)
other	36%

all	12%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	12%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	12%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	12%

INT+FP

all	27%
load	16%
store	25%
mul	12%
add-sub	25%
fma	12%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	34%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 12.75 cycles. At this rate:

1% of peak load performance is reached (1.25 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 11da4

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput	Vectorization
LDR X9, [SP, #5608]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X10, [SP, #624]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X11, [SP, #3792]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ORR X27, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
AND X9, X9, #0x0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
AND X12, X10, #0x0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
SBFM X10, X10, #0, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR X9, X12, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
AND X10, X10, X20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
EOR X9, X11, X9,LSR #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
EOR X9, X9, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR X9, [SP, #5608]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ORR X9, XZR, X27	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X27, X27, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
SUBS X8, X8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
STR X27, [SP, #5616]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X9, [X21, X9,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
UBFM X10, X9, #11, #42	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
EOR X9, X10, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVZ W10, #22144	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVK W10, #40236	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
AND X10, X10, X9,LSL #7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
EOR X9, X10, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVZ W10, #61382	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
AND X10, X10, X9,LSL #15	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
EOR X9, X10, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
EOR X9, X9, X9,LSR #18	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
UCVTF S2, X9	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (25.0%)
MOVZ W9, #20352	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
FMADD S0, S2, S1, S0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25	scal (12.5%)
FMOV S2, W9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (12.5%)
FMUL S1, S1, S2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	scal (12.5%)
B.EQ 11fa0 <main+0xfe0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X27, #624	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.CC 11d50 <main+0xd90>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PTRUE P2.D, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (100.0%)
ADD X9, SP, #120	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SUB X11, X29, #32	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X10, [SP, #560]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
MOVZ X14, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVZ X16, #397	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
LD1RD {Z2.D}, P2/Z, [X9, #63]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	6	0.50	scal (25.0%)
CNTW X12, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
LDR P3, [X11, #511, MUL VL]	1	0	0	0	0	0.50	0.50	0	0	0	0	0.50	0.50	0	0	0	6	0.50	scal (12.5%)
RDVL X13, #2	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
ADD X9, SP, #624	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
RDVL X15, #1	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
HINT #0																			N/A
SUB X9, X29, #32	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X10, [SP, #552]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X14, [SP, #568]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
MOVZ X15, #227	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
MOVZ X16, #228	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
LDR P0, [X9, #509, MUL VL]	1	0	0	0	0	0.50	0.50	0	0	0	0	0.50	0.50	0	0	0	6	0.50	scal (12.5%)
LASTB X9, P0, Z2.D	1	0	0	0	0	1	0	0	1	0	0	0	0	0	0	0	6	1	N/A
PTRUE P1.D, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (100.0%)
ADD X10, X21, #1816	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR X9, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LD1RD {Z2.D}, P1/Z, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	6	0.50	scal (25.0%)
SUB X10, X29, #32	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CNTD X11, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
LDR P2, [X10, #511, MUL VL]	1	0	0	0	0	0.50	0.50	0	0	0	0	0.50	0.50	0	0	0	6	0.50	scal (12.5%)
HINT #0																			N/A
CMP X14, #396	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 11d20 <main+0xd60>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB X9, X29, #32	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X10, X21, X14,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SUB X11, X14, #396	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR P0, [X9, #506, MUL VL]	1	0	0	0	0	0.50	0.50	0	0	0	0	0.50	0.50	0	0	0	6	0.50	scal (12.5%)
LASTB X9, P0, Z2.D	1	0	0	0	0	1	0	0	1	0	0	0	0	0	0	0	6	1	N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
B 11d20 <main+0xd60>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Function	main
Source file and lines	random.tcc:404-3368
Module	attention-armclang-native

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 11.50 to 3.00 cycles (3.83x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is not vectorized. Only 28% of vector register length is used (average across all VPU instructions). By vectorizing your loop, you can lower the cost of an iteration from 11.50 to 9.25 cycles (1.24x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ffast-math (included in Ofast) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

FMA

Detected 1 FMA (fused multiply-add) operations.

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant unknown stride: 2 occurrence(s)
Irregular (variable stride) or indirect: 3 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)
Try to remove indirect accesses. If applicable, precompute elements out of the innermost loop.

Conversion instructions

Detected expensive conversion instructions.

Details

UCVTF: 1 occurrences►
- /usr/lib/gcc/aarch64-amazon-linux/14/../../../../include/c++/14/bits/random.tcc:3367

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 3 FP arithmetical operations:

1: addition or subtraction (all inside FMA instructions)
2: multiply (1 inside FMA instructions)

The binary loop is loading 12 bytes.

Arithmetic intensity

Arithmetic intensity is 0.25 FP operations per loaded or stored byte.

General properties

nb instructions	65
nb uops	63
loop length	260
used w registers	2
used x registers	14
used b registers	0
used h registers	0
used s registers	4
used d registers	0
used q registers	0
used v registers	0
used z registers	1
nb stack references	8

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	7.88 cycles
front end	7.88 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	1.50	1.50	11.50	11.50	11.50	11.50	1.00	1.00	1.00	1.00	4.83	4.50	4.67	1.00	1.00
cycles	1.50	1.50	11.50	11.50	11.50	11.50	1.00	1.00	1.00	1.00	4.83	4.50	4.67	1.00	1.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	3.00

Cycles summary

Front-end	7.88
Dispatch	11.50
Data deps.	3.00
Overall L1	11.50

Vectorization ratios

INT

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	0%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

INT+FP

all	0%
load	0%
store	0%
mul	0%
add-sub	0%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

INT

all	30%
load	17%
store	25%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	25%
fma	NA (no fma vectorizable/vectorized instructions)
other	37%

all	12%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	12%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	12%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	12%

INT+FP

all	28%
load	17%
store	25%
mul	12%
add-sub	25%
fma	12%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	35%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 11.50 cycles. At this rate:

1% of peak load performance is reached (1.04 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 11da4

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput	Vectorization
LDR X9, [SP, #5608]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X10, [SP, #624]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X11, [SP, #3792]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ORR X27, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
AND X9, X9, #0x0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
AND X12, X10, #0x0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
SBFM X10, X10, #0, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR X9, X12, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
AND X10, X10, X20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
EOR X9, X11, X9,LSR #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
EOR X9, X9, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR X9, [SP, #5608]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ORR X9, XZR, X27	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X27, X27, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
SUBS X8, X8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
STR X27, [SP, #5616]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X9, [X21, X9,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
UBFM X10, X9, #11, #42	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
EOR X9, X10, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVZ W10, #22144	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVK W10, #40236	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
AND X10, X10, X9,LSL #7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
EOR X9, X10, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVZ W10, #61382	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
AND X10, X10, X9,LSL #15	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
EOR X9, X10, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
EOR X9, X9, X9,LSR #18	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
UCVTF S2, X9	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (25.0%)
MOVZ W9, #20352	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
FMADD S0, S2, S1, S0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25	scal (12.5%)
FMOV S2, W9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (12.5%)
FMUL S1, S1, S2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	scal (12.5%)
B.EQ 11fa0 <main+0xfe0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X27, #624	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.CC 11d50 <main+0xd90>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PTRUE P2.D, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (100.0%)
ADD X9, SP, #120	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SUB X11, X29, #32	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X10, [SP, #560]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
MOVZ X14, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVZ X16, #397	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
LD1RD {Z2.D}, P2/Z, [X9, #63]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	6	0.50	scal (25.0%)
CNTW X12, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
LDR P3, [X11, #511, MUL VL]	1	0	0	0	0	0.50	0.50	0	0	0	0	0.50	0.50	0	0	0	6	0.50	scal (12.5%)
RDVL X13, #2	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
ADD X9, SP, #624	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
RDVL X15, #1	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
HINT #0																			N/A
SUB X9, X29, #32	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X10, [SP, #552]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X14, [SP, #568]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
MOVZ X15, #227	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
MOVZ X16, #228	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
LDR P0, [X9, #509, MUL VL]	1	0	0	0	0	0.50	0.50	0	0	0	0	0.50	0.50	0	0	0	6	0.50	scal (12.5%)
LASTB X9, P0, Z2.D	1	0	0	0	0	1	0	0	1	0	0	0	0	0	0	0	6	1	N/A
PTRUE P1.D, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (100.0%)
ADD X10, X21, #1816	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR X9, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LD1RD {Z2.D}, P1/Z, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	6	0.50	scal (25.0%)
SUB X10, X29, #32	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CNTD X11, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
LDR P2, [X10, #511, MUL VL]	1	0	0	0	0	0.50	0.50	0	0	0	0	0.50	0.50	0	0	0	6	0.50	scal (12.5%)
HINT #0																			N/A
CMP X14, #396	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	N/A
B.EQ 11d20 <main+0xd60>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Report Configuration

Vectorization

Details

Workaround

FMA

Conversion instructions

Details

Workaround

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Vectorization

Details

Workaround

FMA

Conversion instructions

Details

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

FMA

Slow data structures access

Details

Workaround

Conversion instructions

Details

Workaround

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

FMA

Slow data structures access

Details

Workaround

Conversion instructions

Details

Workaround

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code