OV - attention-armclang-native - Loop 64 - attention-armclang-native

	Loop Id: 64	Module: attention-armclang-native	Source: attention_v2.cpp:164-167 [...]	Coverage: 0.40%

0x11a60 MOVI	D0, #0

0x11a64 FMOV	S1, #1.0000000

0x11a68 ORR	X8, XZR, X0

0x11a6c B	11b04

  (75) 0x11a80 LDR	X9, [SP, #5608]

  (75) 0x11a84 LDR	X10, [SP, #624]

  (75) 0x11a88 LDR	X11, [SP, #3792]

  (75) 0x11a8c ORR	X27, XZR, XZR

  (75) 0x11a90 AND	X9, X9, #0x0

  (75) 0x11a94 AND	X12, X10, #0x0

  (75) 0x11a98 SBFM	X10, X10, #0, #0

  (75) 0x11a9c ORR	X9, X12, X9

  (75) 0x11aa0 AND	X10, X10, X20

  (75) 0x11aa4 EOR	X9, X11, X9,LSR #1

  (75) 0x11aa8 EOR	X9, X9, X10

  (75) 0x11aac STR	X9, [SP, #5608]

  (75) 0x11ab0 ORR	X9, XZR, X27

  (75) 0x11ab4 ADD	X27, X27, #1

  (75) 0x11ab8 SUBS	X8, X8, #1

  (75) 0x11abc STR	X27, [SP, #5616]

  (75) 0x11ac0 LDR	X9, [X21, X9,LSL #3]

  (75) 0x11ac4 UBFM	X10, X9, #11, #42

  (75) 0x11ac8 EOR	X9, X10, X9

  (75) 0x11acc MOVZ	W10, #22144

  (75) 0x11ad0 MOVK	W10, #40236

  (75) 0x11ad4 AND	X10, X10, X9,LSL #7

  (75) 0x11ad8 EOR	X9, X10, X9

  (75) 0x11adc MOVZ	W10, #61382

  (75) 0x11ae0 AND	X10, X10, X9,LSL #15

  (75) 0x11ae4 EOR	X9, X10, X9

  (75) 0x11ae8 EOR	X9, X9, X9,LSR #18

  (75) 0x11aec UCVTF	S2, X9

  (75) 0x11af0 MOVZ	W9, #20352

  (75) 0x11af4 FMADD	S0, S2, S1, S0

  (75) 0x11af8 FMOV	S2, W9

  (75) 0x11afc FMUL	S1, S1, S2

  (75) 0x11b00 B.EQ	11d00

  (75) 0x11b04 CMP	X27, #624

  (75) 0x11b08 B.CC	11ab0

  (75) 0x11b0c PTRUE	P2.D, ALL

  (75) 0x11b10 ADD	X9, SP, #120

  (75) 0x11b14 SUB	X11, X29, #32

  (75) 0x11b18 LDR	X10, [SP, #560]

  (75) 0x11b1c MOVZ	X14, #1

  (75) 0x11b20 MOVZ	X16, #397

  (75) 0x11b24 LD1RD	{Z2.D}, P2/Z, [X9, #63]

  (75) 0x11b28 CNTW	X12, ALL

  (75) 0x11b2c LDR	P3, [X11, #511, MUL VL]

  (75) 0x11b30 RDVL	X13, #2

  (75) 0x11b34 ADD	X9, SP, #624

  (75) 0x11b38 RDVL	X15, #1

  (75) 0x11b3c HINT	#0

    (76) 0x11b40 LD1D	{Z3.D}, P2/Z, [X9, X14,LSL #3]

    (76) 0x11b44 ADD	X11, X9, X15

    (76) 0x11b48 LD1D	{Z7.D}, P2/Z, [X11, X16,LSL #3]

    (76) 0x11b4c SPLICE	Z2.D, P3, Z2.D, Z3.D

    (76) 0x11b50 ORR	Z4.D, Z3.D, Z3.D

    (76) 0x11b54 ORR	Z5.D, Z3.D, Z3.D

    (76) 0x11b58 AND	Z3.D, Z3.D, #0x1

    (76) 0x11b5c AND	Z4.D, Z4.D, #0x7ffffffe

    (76) 0x11b60 CMPEQ	P0.D, P2/Z, Z3.D, #0

    (76) 0x11b64 DUP	Z3.D, X20

    (76) 0x11b68 AND	Z2.D, Z2.D, #0x80000000

    (76) 0x11b6c ORR	Z4.D, Z4.D, Z2.D

    (76) 0x11b70 LD1D	{Z2.D}, P2/Z, [X11, X14,LSL #3]

    (76) 0x11b74 LSR	Z4.D, Z4.D, #63

    (76) 0x11b78 SPLICE	Z5.D, P3, Z5.D, Z2.D

    (76) 0x11b7c ORR	Z6.D, Z2.D, Z2.D

    (76) 0x11b80 AND	Z6.D, Z6.D, #0x7ffffffe

    (76) 0x11b84 AND	Z5.D, Z5.D, #0x80000000

    (76) 0x11b88 ORR	Z5.D, Z6.D, Z5.D

    (76) 0x11b8c LD1D	{Z6.D}, P2/Z, [X9, X16,LSL #3]

    (76) 0x11b90 LSR	Z5.D, Z5.D, #63

    (76) 0x11b94 EOR	Z5.D, Z5.D, Z7.D

    (76) 0x11b98 EOR	Z4.D, Z4.D, Z6.D

    (76) 0x11b9c ORR	Z6.D, Z2.D, Z2.D

    (76) 0x11ba0 AND	Z6.D, Z6.D, #0x1

    (76) 0x11ba4 CMPEQ	P1.D, P2/Z, Z6.D, #0

    (76) 0x11ba8 EOR	Z6.D, Z4.D, Z3.D

    (76) 0x11bac EOR	Z3.D, Z5.D, Z3.D

    (76) 0x11bb0 SUBS	X10, X10, X12

    (76) 0x11bb4 SEL	Z4.D, P0, Z4.D, Z6.D

    (76) 0x11bb8 SEL	Z3.D, P1, Z5.D, Z3.D

    (76) 0x11bbc STR	Z4, [X9, MUL VL]

    (76) 0x11bc0 STR	Z3, [X9, #1, MUL VL]

    (76) 0x11bc4 ADD	X9, X9, X13

    (76) 0x11bc8 B.NE	11b40

  (75) 0x11bcc SUB	X9, X29, #32

  (75) 0x11bd0 LDR	X10, [SP, #552]

  (75) 0x11bd4 LDR	X14, [SP, #568]

  (75) 0x11bd8 MOVZ	X15, #227

  (75) 0x11bdc MOVZ	X16, #228

  (75) 0x11be0 LDR	P0, [X9, #510, MUL VL]

  (75) 0x11be4 LASTB	X9, P0, Z2.D

    (77) 0x11be8 ADD	X11, X21, X10

    (77) 0x11bec AND	X12, X9, #0x0

    (77) 0x11bf0 ADD	X10, X10, #8

    (77) 0x11bf4 LDR	X9, [X11, #8]

    (77) 0x11bf8 CMP	X10, #1816

    (77) 0x11bfc AND	X13, X9, #0x0

    (77) 0x11c00 ORR	X12, X13, X12

    (77) 0x11c04 LDR	X13, [X11, #3176]

    (77) 0x11c08 EOR	X12, X13, X12,LSR #1

    (77) 0x11c0c SBFM	X13, X9, #0, #0

    (77) 0x11c10 AND	X13, X13, X20

    (77) 0x11c14 EOR	X12, X12, X13

    (77) 0x11c18 STR	X12, [X11]

    (77) 0x11c1c B.NE	11be8

  (75) 0x11c20 PTRUE	P1.D, ALL

  (75) 0x11c24 ADD	X10, X21, #1816

  (75) 0x11c28 ORR	X9, XZR, XZR

  (75) 0x11c2c LD1RD	{Z2.D}, P1/Z, [X10]

  (75) 0x11c30 SUB	X10, X29, #32

  (75) 0x11c34 CNTD	X11, ALL

  (75) 0x11c38 LDR	P2, [X10, #511, MUL VL]

  (75) 0x11c3c HINT	#0

    (78) 0x11c40 ADD	X10, X21, X9,LSL #3

    (78) 0x11c44 ORR	Z3.D, Z2.D, Z2.D

    (78) 0x11c48 LD1D	{Z2.D}, P1/Z, [X10, X16,LSL #3]

    (78) 0x11c4c SPLICE	Z3.D, P2, Z3.D, Z2.D

    (78) 0x11c50 ORR	Z4.D, Z2.D, Z2.D

    (78) 0x11c54 AND	Z4.D, Z4.D, #0x7ffffffe

    (78) 0x11c58 AND	Z3.D, Z3.D, #0x80000000

    (78) 0x11c5c ORR	Z3.D, Z4.D, Z3.D

    (78) 0x11c60 ORR	Z4.D, Z2.D, Z2.D

    (78) 0x11c64 AND	Z4.D, Z4.D, #0x1

    (78) 0x11c68 LSR	Z3.D, Z3.D, #63

    (78) 0x11c6c CMPEQ	P0.D, P1/Z, Z4.D, #0

    (78) 0x11c70 LD1D	{Z4.D}, P1/Z, [X21, X9,LSL #3]

    (78) 0x11c74 ADD	X9, X9, X11

    (78) 0x11c78 CMP	X14, X9

    (78) 0x11c7c EOR	Z3.D, Z3.D, Z4.D

    (78) 0x11c80 DUP	Z4.D, X20

    (78) 0x11c84 EOR	Z4.D, Z3.D, Z4.D

    (78) 0x11c88 SEL	Z3.D, P0, Z3.D, Z4.D

    (78) 0x11c8c ST1D	{Z3.D}, P1, [X10, X15,LSL #3]

    (78) 0x11c90 B.NE	11c40

  (75) 0x11c94 CMP	X14, #396

  (75) 0x11c98 B.EQ	11a80

  (75) 0x11c9c SUB	X9, X29, #32

  (75) 0x11ca0 ADD	X10, X21, X14,LSL #3

  (75) 0x11ca4 SUB	X11, X14, #396

  (75) 0x11ca8 LDR	P0, [X9, #507, MUL VL]

  (75) 0x11cac LASTB	X9, P0, Z2.D

  (75) 0x11cb0 HINT	#0

  (75) 0x11cb4 HINT	#0

  (75) 0x11cb8 HINT	#0

  (75) 0x11cbc HINT	#0

    (79) 0x11cc0 AND	X12, X9, #0x0

    (79) 0x11cc4 LDR	X9, [X10, #1824]

    (79) 0x11cc8 ADDS	X11, X11, #1

    (79) 0x11ccc AND	X13, X9, #0x0

    (79) 0x11cd0 ORR	X12, X13, X12

    (79) 0x11cd4 LDR	X13, [X10]

    (79) 0x11cd8 EOR	X12, X13, X12,LSR #1

    (79) 0x11cdc SBFM	X13, X9, #0, #0

    (79) 0x11ce0 AND	X13, X13, X20

    (79) 0x11ce4 EOR	X12, X12, X13

    (79) 0x11ce8 STR	X12, [X10, #1816]

    (79) 0x11cec ADD	X10, X10, #8

    (79) 0x11cf0 B.CC	11cc0

  (75) 0x11cf4 B	11a80

0x11d00 FDIV	S0, S0, S1

0x11d04 FCMP	S0, S10

0x11d08 B.GE	12288

0x11d0c STR	S0, [X28, X18,LSL #2]

0x11d10 MOVI	D0, #0

0x11d14 FMOV	S1, #1.0000000

0x11d18 ORR	X8, XZR, X0

0x11d1c B	11da4

  (70) 0x11d20 LDR	X9, [SP, #5608]

  (70) 0x11d24 LDR	X10, [SP, #624]

  (70) 0x11d28 LDR	X11, [SP, #3792]

  (70) 0x11d2c ORR	X27, XZR, XZR

  (70) 0x11d30 AND	X9, X9, #0x0

  (70) 0x11d34 AND	X12, X10, #0x0

  (70) 0x11d38 SBFM	X10, X10, #0, #0

  (70) 0x11d3c ORR	X9, X12, X9

  (70) 0x11d40 AND	X10, X10, X20

  (70) 0x11d44 EOR	X9, X11, X9,LSR #1

  (70) 0x11d48 EOR	X9, X9, X10

  (70) 0x11d4c STR	X9, [SP, #5608]

  (70) 0x11d50 ORR	X9, XZR, X27

  (70) 0x11d54 ADD	X27, X27, #1

  (70) 0x11d58 SUBS	X8, X8, #1

  (70) 0x11d5c STR	X27, [SP, #5616]

  (70) 0x11d60 LDR	X9, [X21, X9,LSL #3]

  (70) 0x11d64 UBFM	X10, X9, #11, #42

  (70) 0x11d68 EOR	X9, X10, X9

  (70) 0x11d6c MOVZ	W10, #22144

  (70) 0x11d70 MOVK	W10, #40236

  (70) 0x11d74 AND	X10, X10, X9,LSL #7

  (70) 0x11d78 EOR	X9, X10, X9

  (70) 0x11d7c MOVZ	W10, #61382

  (70) 0x11d80 AND	X10, X10, X9,LSL #15

  (70) 0x11d84 EOR	X9, X10, X9

  (70) 0x11d88 EOR	X9, X9, X9,LSR #18

  (70) 0x11d8c UCVTF	S2, X9

  (70) 0x11d90 MOVZ	W9, #20352

  (70) 0x11d94 FMADD	S0, S2, S1, S0

  (70) 0x11d98 FMOV	S2, W9

  (70) 0x11d9c FMUL	S1, S1, S2

  (70) 0x11da0 B.EQ	11fa0

  (70) 0x11da4 CMP	X27, #624

  (70) 0x11da8 B.CC	11d50

  (70) 0x11dac PTRUE	P2.D, ALL

  (70) 0x11db0 ADD	X9, SP, #120

  (70) 0x11db4 SUB	X11, X29, #32

  (70) 0x11db8 LDR	X10, [SP, #560]

  (70) 0x11dbc MOVZ	X14, #1

  (70) 0x11dc0 MOVZ	X16, #397

  (70) 0x11dc4 LD1RD	{Z2.D}, P2/Z, [X9, #63]

  (70) 0x11dc8 CNTW	X12, ALL

  (70) 0x11dcc LDR	P3, [X11, #511, MUL VL]

  (70) 0x11dd0 RDVL	X13, #2

  (70) 0x11dd4 ADD	X9, SP, #624

  (70) 0x11dd8 RDVL	X15, #1

  (70) 0x11ddc HINT	#0

    (71) 0x11de0 LD1D	{Z3.D}, P2/Z, [X9, X14,LSL #3]

    (71) 0x11de4 ADD	X11, X9, X15

    (71) 0x11de8 LD1D	{Z7.D}, P2/Z, [X11, X16,LSL #3]

    (71) 0x11dec SPLICE	Z2.D, P3, Z2.D, Z3.D

    (71) 0x11df0 ORR	Z4.D, Z3.D, Z3.D

    (71) 0x11df4 ORR	Z5.D, Z3.D, Z3.D

    (71) 0x11df8 AND	Z3.D, Z3.D, #0x1

    (71) 0x11dfc AND	Z4.D, Z4.D, #0x7ffffffe

    (71) 0x11e00 CMPEQ	P0.D, P2/Z, Z3.D, #0

    (71) 0x11e04 DUP	Z3.D, X20

    (71) 0x11e08 AND	Z2.D, Z2.D, #0x80000000

    (71) 0x11e0c ORR	Z4.D, Z4.D, Z2.D

    (71) 0x11e10 LD1D	{Z2.D}, P2/Z, [X11, X14,LSL #3]

    (71) 0x11e14 LSR	Z4.D, Z4.D, #63

    (71) 0x11e18 SPLICE	Z5.D, P3, Z5.D, Z2.D

    (71) 0x11e1c ORR	Z6.D, Z2.D, Z2.D

    (71) 0x11e20 AND	Z6.D, Z6.D, #0x7ffffffe

    (71) 0x11e24 AND	Z5.D, Z5.D, #0x80000000

    (71) 0x11e28 ORR	Z5.D, Z6.D, Z5.D

    (71) 0x11e2c LD1D	{Z6.D}, P2/Z, [X9, X16,LSL #3]

    (71) 0x11e30 LSR	Z5.D, Z5.D, #63

    (71) 0x11e34 EOR	Z5.D, Z5.D, Z7.D

    (71) 0x11e38 EOR	Z4.D, Z4.D, Z6.D

    (71) 0x11e3c ORR	Z6.D, Z2.D, Z2.D

    (71) 0x11e40 AND	Z6.D, Z6.D, #0x1

    (71) 0x11e44 CMPEQ	P1.D, P2/Z, Z6.D, #0

    (71) 0x11e48 EOR	Z6.D, Z4.D, Z3.D

    (71) 0x11e4c EOR	Z3.D, Z5.D, Z3.D

    (71) 0x11e50 SUBS	X10, X10, X12

    (71) 0x11e54 SEL	Z4.D, P0, Z4.D, Z6.D

    (71) 0x11e58 SEL	Z3.D, P1, Z5.D, Z3.D

    (71) 0x11e5c STR	Z4, [X9, MUL VL]

    (71) 0x11e60 STR	Z3, [X9, #1, MUL VL]

    (71) 0x11e64 ADD	X9, X9, X13

    (71) 0x11e68 B.NE	11de0

  (70) 0x11e6c SUB	X9, X29, #32

  (70) 0x11e70 LDR	X10, [SP, #552]

  (70) 0x11e74 LDR	X14, [SP, #568]

  (70) 0x11e78 MOVZ	X15, #227

  (70) 0x11e7c MOVZ	X16, #228

  (70) 0x11e80 LDR	P0, [X9, #509, MUL VL]

  (70) 0x11e84 LASTB	X9, P0, Z2.D

    (72) 0x11e88 ADD	X11, X21, X10

    (72) 0x11e8c AND	X12, X9, #0x0

    (72) 0x11e90 ADD	X10, X10, #8

    (72) 0x11e94 LDR	X9, [X11, #8]

    (72) 0x11e98 CMP	X10, #1816

    (72) 0x11e9c AND	X13, X9, #0x0

    (72) 0x11ea0 ORR	X12, X13, X12

    (72) 0x11ea4 LDR	X13, [X11, #3176]

    (72) 0x11ea8 EOR	X12, X13, X12,LSR #1

    (72) 0x11eac SBFM	X13, X9, #0, #0

    (72) 0x11eb0 AND	X13, X13, X20

    (72) 0x11eb4 EOR	X12, X12, X13

    (72) 0x11eb8 STR	X12, [X11]

    (72) 0x11ebc B.NE	11e88

  (70) 0x11ec0 PTRUE	P1.D, ALL

  (70) 0x11ec4 ADD	X10, X21, #1816

  (70) 0x11ec8 ORR	X9, XZR, XZR

  (70) 0x11ecc LD1RD	{Z2.D}, P1/Z, [X10]

  (70) 0x11ed0 SUB	X10, X29, #32

  (70) 0x11ed4 CNTD	X11, ALL

  (70) 0x11ed8 LDR	P2, [X10, #511, MUL VL]

  (70) 0x11edc HINT	#0

    (73) 0x11ee0 ADD	X10, X21, X9,LSL #3

    (73) 0x11ee4 ORR	Z3.D, Z2.D, Z2.D

    (73) 0x11ee8 LD1D	{Z2.D}, P1/Z, [X10, X16,LSL #3]

    (73) 0x11eec SPLICE	Z3.D, P2, Z3.D, Z2.D

    (73) 0x11ef0 ORR	Z4.D, Z2.D, Z2.D

    (73) 0x11ef4 AND	Z4.D, Z4.D, #0x7ffffffe

    (73) 0x11ef8 AND	Z3.D, Z3.D, #0x80000000

    (73) 0x11efc ORR	Z3.D, Z4.D, Z3.D

    (73) 0x11f00 ORR	Z4.D, Z2.D, Z2.D

    (73) 0x11f04 AND	Z4.D, Z4.D, #0x1

    (73) 0x11f08 LSR	Z3.D, Z3.D, #63

    (73) 0x11f0c CMPEQ	P0.D, P1/Z, Z4.D, #0

    (73) 0x11f10 LD1D	{Z4.D}, P1/Z, [X21, X9,LSL #3]

    (73) 0x11f14 ADD	X9, X9, X11

    (73) 0x11f18 CMP	X14, X9

    (73) 0x11f1c EOR	Z3.D, Z3.D, Z4.D

    (73) 0x11f20 DUP	Z4.D, X20

    (73) 0x11f24 EOR	Z4.D, Z3.D, Z4.D

    (73) 0x11f28 SEL	Z3.D, P0, Z3.D, Z4.D

    (73) 0x11f2c ST1D	{Z3.D}, P1, [X10, X15,LSL #3]

    (73) 0x11f30 B.NE	11ee0

  (70) 0x11f34 CMP	X14, #396

  (70) 0x11f38 B.EQ	11d20

  (70) 0x11f3c SUB	X9, X29, #32

  (70) 0x11f40 ADD	X10, X21, X14,LSL #3

  (70) 0x11f44 SUB	X11, X14, #396

  (70) 0x11f48 LDR	P0, [X9, #506, MUL VL]

  (70) 0x11f4c LASTB	X9, P0, Z2.D

  (70) 0x11f50 HINT	#0

  (70) 0x11f54 HINT	#0

  (70) 0x11f58 HINT	#0

  (70) 0x11f5c HINT	#0

    (74) 0x11f60 AND	X12, X9, #0x0

    (74) 0x11f64 LDR	X9, [X10, #1824]

    (74) 0x11f68 ADDS	X11, X11, #1

    (74) 0x11f6c AND	X13, X9, #0x0

    (74) 0x11f70 ORR	X12, X13, X12

    (74) 0x11f74 LDR	X13, [X10]

    (74) 0x11f78 EOR	X12, X13, X12,LSR #1

    (74) 0x11f7c SBFM	X13, X9, #0, #0

    (74) 0x11f80 AND	X13, X13, X20

    (74) 0x11f84 EOR	X12, X12, X13

    (74) 0x11f88 STR	X12, [X10, #1816]

    (74) 0x11f8c ADD	X10, X10, #8

    (74) 0x11f90 B.CC	11f60

  (70) 0x11f94 B	11d20

0x11fa0 FDIV	S0, S0, S1

0x11fa4 FCMP	S0, S10

0x11fa8 B.GE	122a8

0x11fac STR	S0, [X26, X18,LSL #2]

0x11fb0 MOVI	D0, #0

0x11fb4 FMOV	S1, #1.0000000

0x11fb8 ORR	X8, XZR, X0

0x11fbc B	12048

  (65) 0x11fc0 ADD	X10, SP, #624

  (65) 0x11fc4 LDR	X9, [SP, #5608]

  (65) 0x11fc8 ORR	X27, XZR, XZR

  (65) 0x11fcc LDR	X10, [X10]

  (65) 0x11fd0 AND	X9, X9, #0x0

  (65) 0x11fd4 AND	X11, X10, #0x0

  (65) 0x11fd8 SBFM	X10, X10, #0, #0

  (65) 0x11fdc ORR	X9, X11, X9

  (65) 0x11fe0 LDR	X11, [SP, #3792]

  (65) 0x11fe4 AND	X10, X10, X20

  (65) 0x11fe8 EOR	X9, X11, X9,LSR #1

  (65) 0x11fec EOR	X9, X9, X10

  (65) 0x11ff0 STR	X9, [SP, #5608]

  (65) 0x11ff4 ORR	X9, XZR, X27

  (65) 0x11ff8 ADD	X27, X27, #1

  (65) 0x11ffc SUBS	X8, X8, #1

  (65) 0x12000 STR	X27, [SP, #5616]

  (65) 0x12004 LDR	X9, [X21, X9,LSL #3]

  (65) 0x12008 UBFM	X10, X9, #11, #42

  (65) 0x1200c EOR	X9, X10, X9

  (65) 0x12010 MOVZ	W10, #22144

  (65) 0x12014 MOVK	W10, #40236

  (65) 0x12018 AND	X10, X10, X9,LSL #7

  (65) 0x1201c EOR	X9, X10, X9

  (65) 0x12020 MOVZ	W10, #61382

  (65) 0x12024 AND	X10, X10, X9,LSL #15

  (65) 0x12028 EOR	X9, X10, X9

  (65) 0x1202c EOR	X9, X9, X9,LSR #18

  (65) 0x12030 UCVTF	S2, X9

  (65) 0x12034 MOVZ	W9, #20352

  (65) 0x12038 FMADD	S0, S2, S1, S0

  (65) 0x1203c FMOV	S2, W9

  (65) 0x12040 FMUL	S1, S1, S2

  (65) 0x12044 B.EQ	12260

  (65) 0x12048 CMP	X27, #624

  (65) 0x1204c B.CC	11ff4

  (65) 0x12050 PTRUE	P2.D, ALL

  (65) 0x12054 ADD	X9, SP, #120

  (65) 0x12058 SUB	X11, X29, #32

  (65) 0x1205c LDR	X10, [SP, #560]

  (65) 0x12060 MOVZ	X14, #1

  (65) 0x12064 MOVZ	X16, #397

  (65) 0x12068 LD1RD	{Z2.D}, P2/Z, [X9, #63]

  (65) 0x1206c CNTW	X12, ALL

  (65) 0x12070 LDR	P3, [X11, #511, MUL VL]

  (65) 0x12074 RDVL	X13, #2

  (65) 0x12078 ADD	X9, SP, #624

  (65) 0x1207c RDVL	X15, #1

    (66) 0x12080 LD1D	{Z3.D}, P2/Z, [X9, X14,LSL #3]

    (66) 0x12084 ADD	X11, X9, X15

    (66) 0x12088 LD1D	{Z7.D}, P2/Z, [X11, X16,LSL #3]

    (66) 0x1208c SPLICE	Z2.D, P3, Z2.D, Z3.D

    (66) 0x12090 ORR	Z4.D, Z3.D, Z3.D

    (66) 0x12094 ORR	Z5.D, Z3.D, Z3.D

    (66) 0x12098 AND	Z3.D, Z3.D, #0x1

    (66) 0x1209c AND	Z4.D, Z4.D, #0x7ffffffe

    (66) 0x120a0 CMPEQ	P0.D, P2/Z, Z3.D, #0

    (66) 0x120a4 DUP	Z3.D, X20

    (66) 0x120a8 AND	Z2.D, Z2.D, #0x80000000

    (66) 0x120ac ORR	Z4.D, Z4.D, Z2.D

    (66) 0x120b0 LD1D	{Z2.D}, P2/Z, [X11, X14,LSL #3]

    (66) 0x120b4 LSR	Z4.D, Z4.D, #63

    (66) 0x120b8 SPLICE	Z5.D, P3, Z5.D, Z2.D

    (66) 0x120bc ORR	Z6.D, Z2.D, Z2.D

    (66) 0x120c0 AND	Z6.D, Z6.D, #0x7ffffffe

    (66) 0x120c4 AND	Z5.D, Z5.D, #0x80000000

    (66) 0x120c8 ORR	Z5.D, Z6.D, Z5.D

    (66) 0x120cc LD1D	{Z6.D}, P2/Z, [X9, X16,LSL #3]

    (66) 0x120d0 LSR	Z5.D, Z5.D, #63

    (66) 0x120d4 EOR	Z5.D, Z5.D, Z7.D

    (66) 0x120d8 EOR	Z4.D, Z4.D, Z6.D

    (66) 0x120dc ORR	Z6.D, Z2.D, Z2.D

    (66) 0x120e0 AND	Z6.D, Z6.D, #0x1

    (66) 0x120e4 CMPEQ	P1.D, P2/Z, Z6.D, #0

    (66) 0x120e8 EOR	Z6.D, Z4.D, Z3.D

    (66) 0x120ec EOR	Z3.D, Z5.D, Z3.D

    (66) 0x120f0 SUBS	X10, X10, X12

    (66) 0x120f4 SEL	Z4.D, P0, Z4.D, Z6.D

    (66) 0x120f8 SEL	Z3.D, P1, Z5.D, Z3.D

    (66) 0x120fc STR	Z4, [X9, MUL VL]

    (66) 0x12100 STR	Z3, [X9, #1, MUL VL]

    (66) 0x12104 ADD	X9, X9, X13

    (66) 0x12108 B.NE	12080

  (65) 0x1210c SUB	X9, X29, #32

  (65) 0x12110 LDR	X10, [SP, #552]

  (65) 0x12114 LDR	X15, [SP, #568]

  (65) 0x12118 MOVZ	X16, #227

  (65) 0x1211c MOVZ	X17, #228

  (65) 0x12120 LDR	P0, [X9, #508, MUL VL]

  (65) 0x12124 ADD	X12, X21, X10

  (65) 0x12128 LDR	X10, [SP, #488]

  (65) 0x1212c ORR	X11, XZR, X12

  (65) 0x12130 LASTB	X9, P0, Z2.D

  (65) 0x12134 HINT	#0

  (65) 0x12138 HINT	#0

  (65) 0x1213c HINT	#0

    (67) 0x12140 AND	X13, X9, #0x0

    (67) 0x12144 LDR	X9, [X11, #8]!

    (67) 0x12148 SUBS	X10, X10, #1

    (67) 0x1214c AND	X14, X9, #0x0

    (67) 0x12150 ORR	X13, X14, X13

    (67) 0x12154 LDR	X14, [X12, #3176]

    (67) 0x12158 EOR	X13, X14, X13,LSR #1

    (67) 0x1215c SBFM	X14, X9, #0, #0

    (67) 0x12160 AND	X14, X14, X20

    (67) 0x12164 EOR	X13, X13, X14

    (67) 0x12168 STR	X13, [X12]

    (67) 0x1216c ORR	X12, XZR, X11

    (67) 0x12170 B.NE	12140

  (65) 0x12174 PTRUE	P1.D, ALL

  (65) 0x12178 ADD	X10, X21, #1816

  (65) 0x1217c ORR	X9, XZR, XZR

  (65) 0x12180 LD1RD	{Z2.D}, P1/Z, [X10]

  (65) 0x12184 SUB	X10, X29, #32

  (65) 0x12188 CNTD	X11, ALL

  (65) 0x1218c LDR	P2, [X10, #511, MUL VL]

  (65) 0x12190 HINT	#0

  (65) 0x12194 HINT	#0

  (65) 0x12198 HINT	#0

  (65) 0x1219c HINT	#0

    (68) 0x121a0 ADD	X10, X21, X9,LSL #3

    (68) 0x121a4 ORR	Z3.D, Z2.D, Z2.D

    (68) 0x121a8 LD1D	{Z2.D}, P1/Z, [X10, X17,LSL #3]

    (68) 0x121ac SPLICE	Z3.D, P2, Z3.D, Z2.D

    (68) 0x121b0 ORR	Z4.D, Z2.D, Z2.D

    (68) 0x121b4 AND	Z4.D, Z4.D, #0x7ffffffe

    (68) 0x121b8 AND	Z3.D, Z3.D, #0x80000000

    (68) 0x121bc ORR	Z3.D, Z4.D, Z3.D

    (68) 0x121c0 ORR	Z4.D, Z2.D, Z2.D

    (68) 0x121c4 AND	Z4.D, Z4.D, #0x1

    (68) 0x121c8 LSR	Z3.D, Z3.D, #63

    (68) 0x121cc CMPEQ	P0.D, P1/Z, Z4.D, #0

    (68) 0x121d0 LD1D	{Z4.D}, P1/Z, [X21, X9,LSL #3]

    (68) 0x121d4 ADD	X9, X9, X11

    (68) 0x121d8 CMP	X15, X9

    (68) 0x121dc EOR	Z3.D, Z3.D, Z4.D

    (68) 0x121e0 DUP	Z4.D, X20

    (68) 0x121e4 EOR	Z4.D, Z3.D, Z4.D

    (68) 0x121e8 SEL	Z3.D, P0, Z3.D, Z4.D

    (68) 0x121ec ST1D	{Z3.D}, P1, [X10, X16,LSL #3]

    (68) 0x121f0 B.NE	121a0

  (65) 0x121f4 CMP	X15, #396

  (65) 0x121f8 B.EQ	11fc0

  (65) 0x121fc LDR	X9, [SP, #504]

  (65) 0x12200 ADD	X10, X21, X15,LSL #3

  (65) 0x12204 SUB	X11, X15, #396

  (65) 0x12208 WHILELS	P0.D, XZR, X9

  (65) 0x1220c LASTB	X9, P0, Z2.D

  (65) 0x12210 HINT	#0

  (65) 0x12214 HINT	#0

  (65) 0x12218 HINT	#0

  (65) 0x1221c HINT	#0

    (69) 0x12220 AND	X12, X9, #0x0

    (69) 0x12224 LDR	X9, [X10, #1824]

    (69) 0x12228 ADDS	X11, X11, #1

    (69) 0x1222c AND	X13, X9, #0x0

    (69) 0x12230 ORR	X12, X13, X12

    (69) 0x12234 LDR	X13, [X10]

    (69) 0x12238 EOR	X12, X13, X12,LSR #1

    (69) 0x1223c SBFM	X13, X9, #0, #0

    (69) 0x12240 AND	X13, X13, X20

    (69) 0x12244 EOR	X12, X12, X13

    (69) 0x12248 STR	X12, [X10, #1816]

    (69) 0x1224c ADD	X10, X10, #8

    (69) 0x12250 B.CC	12220

  (65) 0x12254 B	11fc0

0x12260 FDIV	S0, S0, S1

0x12264 FCMP	S0, S10

0x12268 B.GE	122c8

0x1226c LDR	X8, [SP, #360]

0x12270 STR	S0, [X8, X18,LSL #2]

0x12274 LDR	X8, [SP, #344]

0x12278 ADD	X18, X18, #1

0x1227c CMP	X18, X8

0x12280 B.NE	11a60

0x12288 FMOV	S0, #1.0000000

0x1228c MOVI	D1, #0

0x12290 STR	X18, [SP, #576]

0x12294 STR	X0, [SP, #512]

0x12298 BL	10140

0x1229c LDR	X0, [SP, #512]

0x122a0 LDR	X18, [SP, #576]

0x122a4 B	11d0c

0x122a8 FMOV	S0, #1.0000000

0x122ac MOVI	D1, #0

0x122b0 STR	X18, [SP, #576]

0x122b4 STR	X0, [SP, #512]

0x122b8 BL	10140

0x122bc LDR	X0, [SP, #512]

0x122c0 LDR	X18, [SP, #576]

0x122c4 B	11fac

0x122c8 FMOV	S0, #1.0000000

0x122cc MOVI	D1, #0

0x122d0 STR	X18, [SP, #576]

0x122d4 STR	X0, [SP, #512]

0x122d8 BL	10140

0x122dc LDR	X0, [SP, #512]

0x122e0 LDR	X18, [SP, #576]

0x122e4 LDR	X8, [SP, #360]

0x122e8 STR	S0, [X8, X18,LSL #2]

0x122ec LDR	X8, [SP, #344]

0x122f0 ADD	X18, X18, #1

0x122f4 CMP	X18, X8

0x122f8 B.NE	11a60

/usr/lib/gcc/aarch64-amazon-linux/14/../../../../include/c++/14/cmath: 2622 - 2622

--------------------------------------------------------------------------------

2622:   { return __builtin_nextafterf(__x, __y); }

/home/eoseret/llm-attention/attention_v2.cpp: 164 - 167

--------------------------------------------------------------------------------

164:       for (size_t i = 0; i < elemsW; ++i) {

165:          h_WQ[i] = dist(rng);

166:          h_WK[i] = dist(rng);

167:          h_WV[i] = dist(rng);

/usr/lib/gcc/aarch64-amazon-linux/14/../../../../include/c++/14/bits/random.tcc: 404 - 3371

--------------------------------------------------------------------------------

404:       for (size_t __k = 0; __k < (__n - __m); ++__k)

405:         {

406: 	  _UIntType __y = ((_M_x[__k] & __upper_mask)

407: 			   | (_M_x[__k + 1] & __lower_mask));

408: 	  _M_x[__k] = (_M_x[__k + __m] ^ (__y >> 1)

409: 		       ^ ((__y & 0x01) ? __a : 0));

410:         }

411:

412:       for (size_t __k = (__n - __m); __k < (__n - 1); ++__k)

413: 	{

414: 	  _UIntType __y = ((_M_x[__k] & __upper_mask)

415: 			   | (_M_x[__k + 1] & __lower_mask));

416: 	  _M_x[__k] = (_M_x[__k + (__m - __n)] ^ (__y >> 1)

417: 		       ^ ((__y & 0x01) ? __a : 0));

418: 	}

419:

420:       _UIntType __y = ((_M_x[__n - 1] & __upper_mask)

421: 		       | (_M_x[0] & __lower_mask));

422:       _M_x[__n - 1] = (_M_x[__m - 1] ^ (__y >> 1)

423: 		       ^ ((__y & 0x01) ? __a : 0));

[...]

458:       if (_M_p >= state_size)

459: 	_M_gen_rand();

460:

461:       // Calculate o(x(i)).

462:       result_type __z = _M_x[_M_p++];

463:       __z ^= (__z >> __u) & __d;

464:       __z ^= (__z << __s) & __b;

465:       __z ^= (__z << __t) & __c;

466:       __z ^= (__z >> __l);

[...]

3365:       for (size_t __k = __m; __k != 0; --__k)

3366: 	{

3367: 	  __sum += _RealType(__urng() - __urng.min()) * __tmp;

3368: 	  __tmp *= __r;

3369: 	}

3370:       __ret = __sum / __tmp;

3371:       if (__builtin_expect(__ret >= _RealType(1), 0))

Coverage (%)	Name	Module
►100.00+	__libc_start_call_main	libc.so.6
○	__libc_start_main	libc.so.6
○	_start	attention-armclang-native

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	1.98
CQA speedup if FP arith vectorized	1.45
CQA speedup if fully vectorized	6.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.09
Bottlenecks	micro-operation queue,
Function	main
Source	cmath:2622-2622,attention_v2.cpp:164-167,random.tcc:3370-3371
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	7.25
CQA cycles if no scalar integer	3.67
CQA cycles if FP arith vectorized	5.00
CQA cycles if fully vectorized	1.21
Front-end cycles	7.25
P0 cycles	6.50
P1 cycles	6.50
P2 cycles	2.50
P3 cycles	2.50
P4 cycles	2.50
P5 cycles	2.50
P6 cycles	5.50
P7 cycles	5.50
P8 cycles	5.50
P9 cycles	5.50
P10 cycles	6.67
P11 cycles	6.67
P12 cycles	6.67
P13 cycles	3.00
P14 cycles	3.00
DIV/SQRT cycles	2.62 - 3.38
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	58.00
Nb uops	58.00
Nb loads	NA
Nb stores	10.00
Nb stack references	16.00
FLOP/cycle	0.41
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	3.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	1.66
Bytes prefetched	0.00
Bytes loaded	0.00
Bytes stored	12.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	0.00
Vectorization ratio other	0.00
Vector-efficiency ratio all	18.75
Vector-efficiency ratio load	25.00
Vector-efficiency ratio store	20.00
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	12.50
Vector-efficiency ratio other	17.97

Metric	Value
CQA speedup if no scalar integer	1.98
CQA speedup if FP arith vectorized	1.45
CQA speedup if fully vectorized	6.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.09
Bottlenecks	micro-operation queue,
Function	main
Source	cmath:2622-2622,attention_v2.cpp:164-167,random.tcc:3370-3371
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	7.25
CQA cycles if no scalar integer	3.67
CQA cycles if FP arith vectorized	5.00
CQA cycles if fully vectorized	1.21
Front-end cycles	7.25
P0 cycles	6.50
P1 cycles	6.50
P2 cycles	2.50
P3 cycles	2.50
P4 cycles	2.50
P5 cycles	2.50
P6 cycles	5.50
P7 cycles	5.50
P8 cycles	5.50
P9 cycles	5.50
P10 cycles	6.67
P11 cycles	6.67
P12 cycles	6.67
P13 cycles	3.00
P14 cycles	3.00
DIV/SQRT cycles	2.62 - 3.38
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	58.00
Nb uops	58.00
Nb loads	NA
Nb stores	10.00
Nb stack references	16.00
FLOP/cycle	0.41
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	3.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	1.66
Bytes prefetched	0.00
Bytes loaded	0.00
Bytes stored	12.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	0.00
Vectorization ratio other	0.00
Vector-efficiency ratio all	18.75
Vector-efficiency ratio load	25.00
Vector-efficiency ratio store	20.00
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	12.50
Vector-efficiency ratio other	17.97

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	main
Source file and lines	attention_v2.cpp:164-167
Module	attention-armclang-native

The loop is defined in:

/usr/lib/gcc/aarch64-amazon-linux/14/../../../../include/c++/14/cmath:2622
/home/eoseret/llm-attention/attention_v2.cpp:164-167
/usr/lib/gcc/aarch64-amazon-linux/14/../../../../include/c++/14/bits/random.tcc:404-423,458-466,3365-3371

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Failed to get the number of paths
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 7.25 to 3.67 cycles (1.98x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is not vectorized. Only 18% of vector register length is used (average across all VPU instructions). By vectorizing your loop, you can lower the cost of an iteration from 7.25 to 1.21 cycles (6.00x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ffast-math (included in Ofast) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 7.25 to 6.88 cycles (1.05x speedup).

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

unknown: 3 occurrences►
- /usr/lib/gcc/aarch64-amazon-linux/14/../../../../include/c++/14/cmath:2622
- /usr/lib/gcc/aarch64-amazon-linux/14/../../../../include/c++/14/cmath:2622
- /usr/lib/gcc/aarch64-amazon-linux/14/../../../../include/c++/14/cmath:2622

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 3 FP arithmetical operations:

3: divide

The binary loop is storing 12 bytes.

Arithmetic intensity

Arithmetic intensity is 0.25 FP operations per loaded or stored byte.

General properties

nb instructions	58
nb uops	58
loop length	232
used w registers	0
used x registers	6
used b registers	0
used h registers	0
used s registers	4
used d registers	2
used q registers	0
used v registers	0
used z registers	0
nb stack references	16

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	7.25 cycles
front end	7.25 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	6.50	6.50	2.50	2.50	2.50	2.50	5.50	5.50	5.50	5.50	6.67	6.67	6.67	3.00	3.00
cycles	6.50	6.50	2.50	2.50	2.50	2.50	5.50	5.50	5.50	5.50	6.67	6.67	6.67	3.00	3.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

2.62-3.38

Cycles summary

Front-end	7.25
Dispatch	6.67
DIV/SQRT	2.62-3.38
Overall L1	7.25

Vectorization ratios

INT

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	0%

INT+FP

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	0%

Vector efficiency ratios

INT

all	22%
load	25%
store	20%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	25%

all	12%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	12%
other	12%

INT+FP

all	18%
load	25%
store	20%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	12%
other	17%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 7.25 cycles. At this rate:

3% of peak store performance is reached (1.66 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 7.25 to 6.67 cycles (1.09x speedup).

ASM code

In the binary file, the address of the loop is: 11a60

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput	Vectorization
MOVI D0, #0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
FMOV S1, #1.0000000	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (12.5%)
ORR X8, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
B 11b04 <main+0xb44>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
FDIV S0, S0, S1	1	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	0	0	7-10	0.87-1.13	scal (12.5%)
FCMP S0, S10	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (12.5%)
B.GE 12288 <main+0x12c8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STR S0, [X28, X18,LSL #2]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (12.5%)
MOVI D0, #0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
FMOV S1, #1.0000000	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (12.5%)
ORR X8, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
B 11da4 <main+0xde4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
FDIV S0, S0, S1	1	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	0	0	7-10	0.87-1.13	scal (12.5%)
FCMP S0, S10	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (12.5%)
B.GE 122a8 <main+0x12e8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STR S0, [X26, X18,LSL #2]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (12.5%)
MOVI D0, #0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
FMOV S1, #1.0000000	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (12.5%)
ORR X8, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
B 12048 <main+0x1088>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
FDIV S0, S0, S1	1	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	0	0	7-10	0.87-1.13	scal (12.5%)
FCMP S0, S10	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (12.5%)
B.GE 122c8 <main+0x1308>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X8, [SP, #360]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR S0, [X8, X18,LSL #2]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (12.5%)
LDR X8, [SP, #344]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X18, X18, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP X18, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.NE 11a60 <main+0xaa0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
FMOV S0, #1.0000000	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (12.5%)
MOVI D1, #0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
STR X18, [SP, #576]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X0, [SP, #512]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
BL 10140 <@plt_start@+0x120>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X0, [SP, #512]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X18, [SP, #576]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
B 11d0c <main+0xd4c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
FMOV S0, #1.0000000	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (12.5%)
MOVI D1, #0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
STR X18, [SP, #576]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X0, [SP, #512]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
BL 10140 <@plt_start@+0x120>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X0, [SP, #512]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X18, [SP, #576]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
B 11fac <main+0xfec>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
FMOV S0, #1.0000000	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (12.5%)
MOVI D1, #0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
STR X18, [SP, #576]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X0, [SP, #512]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
BL 10140 <@plt_start@+0x120>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X0, [SP, #512]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X18, [SP, #576]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X8, [SP, #360]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR S0, [X8, X18,LSL #2]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (12.5%)
LDR X8, [SP, #344]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X18, X18, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP X18, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	N/A
B.NE 11a60 <main+0xaa0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Function	main
Source file and lines	attention_v2.cpp:164-167
Module	attention-armclang-native

The loop is defined in:

/usr/lib/gcc/aarch64-amazon-linux/14/../../../../include/c++/14/cmath:2622
/home/eoseret/llm-attention/attention_v2.cpp:164-167
/usr/lib/gcc/aarch64-amazon-linux/14/../../../../include/c++/14/bits/random.tcc:404-423,458-466,3365-3371

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Failed to get the number of paths
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 7.25 to 3.67 cycles (1.98x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ffast-math (included in Ofast) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 7.25 to 6.88 cycles (1.05x speedup).

CALL instructions

Detected function call instructions.

Details

unknown: 3 occurrences►
- /usr/lib/gcc/aarch64-amazon-linux/14/../../../../include/c++/14/cmath:2622
- /usr/lib/gcc/aarch64-amazon-linux/14/../../../../include/c++/14/cmath:2622
- /usr/lib/gcc/aarch64-amazon-linux/14/../../../../include/c++/14/cmath:2622

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 3 FP arithmetical operations:

3: divide

The binary loop is storing 12 bytes.

Arithmetic intensity

Arithmetic intensity is 0.25 FP operations per loaded or stored byte.

General properties

nb instructions	58
nb uops	58
loop length	232
used w registers	0
used x registers	6
used b registers	0
used h registers	0
used s registers	4
used d registers	2
used q registers	0
used v registers	0
used z registers	0
nb stack references	16

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	7.25 cycles
front end	7.25 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	6.50	6.50	2.50	2.50	2.50	2.50	5.50	5.50	5.50	5.50	6.67	6.67	6.67	3.00	3.00
cycles	6.50	6.50	2.50	2.50	2.50	2.50	5.50	5.50	5.50	5.50	6.67	6.67	6.67	3.00	3.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

2.62-3.38

Cycles summary

Front-end	7.25
Dispatch	6.67
DIV/SQRT	2.62-3.38
Overall L1	7.25

Vectorization ratios

INT

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	0%

INT+FP

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	0%

Vector efficiency ratios

INT

all	22%
load	25%
store	20%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	25%

all	12%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	12%
other	12%

INT+FP

all	18%
load	25%
store	20%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	12%
other	17%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 7.25 cycles. At this rate:

3% of peak store performance is reached (1.66 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the loop is: 11a60

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput	Vectorization
MOVI D0, #0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
FMOV S1, #1.0000000	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (12.5%)
ORR X8, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
B 11b04 <main+0xb44>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
FDIV S0, S0, S1	1	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	0	0	7-10	0.87-1.13	scal (12.5%)
FCMP S0, S10	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (12.5%)
B.GE 12288 <main+0x12c8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STR S0, [X28, X18,LSL #2]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (12.5%)
MOVI D0, #0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
FMOV S1, #1.0000000	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (12.5%)
ORR X8, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
B 11da4 <main+0xde4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
FDIV S0, S0, S1	1	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	0	0	7-10	0.87-1.13	scal (12.5%)
FCMP S0, S10	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (12.5%)
B.GE 122a8 <main+0x12e8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STR S0, [X26, X18,LSL #2]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (12.5%)
MOVI D0, #0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
FMOV S1, #1.0000000	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (12.5%)
ORR X8, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
B 12048 <main+0x1088>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
FDIV S0, S0, S1	1	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	0	0	7-10	0.87-1.13	scal (12.5%)
FCMP S0, S10	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (12.5%)
B.GE 122c8 <main+0x1308>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X8, [SP, #360]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR S0, [X8, X18,LSL #2]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (12.5%)
LDR X8, [SP, #344]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X18, X18, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP X18, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.NE 11a60 <main+0xaa0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
FMOV S0, #1.0000000	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (12.5%)
MOVI D1, #0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
STR X18, [SP, #576]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X0, [SP, #512]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
BL 10140 <@plt_start@+0x120>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X0, [SP, #512]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X18, [SP, #576]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
B 11d0c <main+0xd4c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
FMOV S0, #1.0000000	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (12.5%)
MOVI D1, #0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
STR X18, [SP, #576]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X0, [SP, #512]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
BL 10140 <@plt_start@+0x120>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X0, [SP, #512]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X18, [SP, #576]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
B 11fac <main+0xfec>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
FMOV S0, #1.0000000	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (12.5%)
MOVI D1, #0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
STR X18, [SP, #576]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X0, [SP, #512]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
BL 10140 <@plt_start@+0x120>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X0, [SP, #512]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X18, [SP, #576]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X8, [SP, #360]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR S0, [X8, X18,LSL #2]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (12.5%)
LDR X8, [SP, #344]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X18, X18, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP X18, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	N/A
B.NE 11a60 <main+0xaa0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

Expensive FP math instructions/calls

CALL instructions

Details

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Expensive FP math instructions/calls

CALL instructions

Details

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code