OV - attention-armclang-native - Loop 62 - attention-armclang-native

	Loop Id: 62	Module: attention-armclang-native	Source: attention_v2.cpp:26-33	Coverage: 0.30%

0x12340 MOVI	D0, #0

0x12344 ADD	W13, W11, W12

0x12348 MADD	W12, W12, W23, W10

0x1234c LDR	S1, [X19, W13,UXTW #2]

0x12350 LDR	S2, [X28, W12,UXTW #2]

0x12354 FCVT	D1, S1

0x12358 FCVT	D2, S2

0x1235c FMADD	D0, D1, D2, D0

0x12360 LDR	X13, [SP, #600]

0x12364 FCVT	S0, D0

0x12368 ADD	W12, W11, W10

0x1236c ADD	X10, X10, #1

0x12370 STR	S0, [X13, W12,UXTW #2]

0x12374 AND	X12, X23, #0x7fffffff

0x12378 CMP	X10, X12

0x1237c B.EQ	12320

0x12380 LDR	X12, [SP, #608]

0x12384 CBZ	X12, 12340

0x12388 MOVI	D0, #0

0x1238c AND	X16, X23, #0x0

0x12390 ORR	X12, XZR, XZR

0x12394 ORR	X13, XZR, X10

0x12398 ORR	W14, WZR, W9

0x1239c HINT	#0

  (63) 0x123a0 SUB	W15, W14, #1

  (63) 0x123a4 LDR	S2, [X28, W13,UXTW #2]

  (63) 0x123a8 ADD	X12, X12, #2

  (63) 0x123ac LDR	S1, [X19, W15,UXTW #2]

  (63) 0x123b0 ADD	W15, W23, W13

  (63) 0x123b4 ADD	X13, X13, X24

  (63) 0x123b8 CMP	X16, X12

  (63) 0x123bc FCVT	D2, S2

  (63) 0x123c0 FCVT	D1, S1

  (63) 0x123c4 FMADD	D0, D1, D2, D0

  (63) 0x123c8 LDR	S1, [X19, W14,UXTW #2]

  (63) 0x123cc LDR	S2, [X28, W15,UXTW #2]

  (63) 0x123d0 ADD	W14, W14, #2

  (63) 0x123d4 FCVT	D1, S1

  (63) 0x123d8 FCVT	D2, S2

  (63) 0x123dc FMADD	D0, D1, D2, D0

  (63) 0x123e0 B.NE	123a0

0x123e4 AND	X13, X23, #0x0

0x123e8 STR	X13, [SP, #592]

0x123ec TBNZ	W23, #0, 12344

0x123f0 B	12360

/home/eoseret/llm-attention/attention_v2.cpp: 26 - 33

--------------------------------------------------------------------------------

26:    for (unsigned int i = 0; i < M; ++i) {

27:       for (unsigned int j = 0; j < N; ++j) {  //vectorized

28:          double sum = 0.0;

29: #pragma clang loop vectorize(enable)

30:          for (unsigned int k = 0; k < K; ++k) { //vectorized

31:             sum += (double)A[i * K + k] * (double)B[k * N + j];

32:          }

33:          C[i * N + j] = alpha * static_cast<float>(sum);

Coverage (%)	Name	Module
►100.00+	__libc_start_call_main	libc.so.6
○	__libc_start_main	libc.so.6
○	_start	attention-armclang-native

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	2.25
CQA speedup if FP arith vectorized	2.04
CQA speedup if fully vectorized	7.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.23
Bottlenecks	micro-operation queue,
Function	main
Source	attention_v2.cpp:26-27,attention_v2.cpp:30-33
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	3.38
CQA cycles if no scalar integer	1.50
CQA cycles if FP arith vectorized	1.66
CQA cycles if fully vectorized	0.48
Front-end cycles	3.38
P0 cycles	2.00
P1 cycles	2.00
P2 cycles	2.75
P3 cycles	2.75
P4 cycles	2.75
P5 cycles	2.75
P6 cycles	1.75
P7 cycles	1.75
P8 cycles	1.75
P9 cycles	1.75
P10 cycles	2.00
P11 cycles	2.00
P12 cycles	2.00
P13 cycles	0.50
P14 cycles	0.50
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	28.00
Nb uops	27.00
Nb loads	NA
Nb stores	2.00
Nb stack references	3.00
FLOP/cycle	0.59
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	1.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	2.67
Bytes prefetched	0.00
Bytes loaded	6.00
Bytes stored	3.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	0.00
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	18.75
Vector-efficiency ratio load	12.50
Vector-efficiency ratio store	18.75
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	25.00
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	19.64

Metric	Value
CQA speedup if no scalar integer	2.25
CQA speedup if FP arith vectorized	2.04
CQA speedup if fully vectorized	7.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.23
Bottlenecks	micro-operation queue,
Function	main
Source	attention_v2.cpp:26-27,attention_v2.cpp:30-33
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	3.38
CQA cycles if no scalar integer	1.50
CQA cycles if FP arith vectorized	1.66
CQA cycles if fully vectorized	0.48
Front-end cycles	3.38
P0 cycles	2.00
P1 cycles	2.00
P2 cycles	2.75
P3 cycles	2.75
P4 cycles	2.75
P5 cycles	2.75
P6 cycles	1.75
P7 cycles	1.75
P8 cycles	1.75
P9 cycles	1.75
P10 cycles	2.00
P11 cycles	2.00
P12 cycles	2.00
P13 cycles	0.50
P14 cycles	0.50
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	28.00
Nb uops	27.00
Nb loads	NA
Nb stores	2.00
Nb stack references	3.00
FLOP/cycle	0.59
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	1.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	2.67
Bytes prefetched	0.00
Bytes loaded	6.00
Bytes stored	3.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	0.00
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	18.75
Vector-efficiency ratio load	12.50
Vector-efficiency ratio store	18.75
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	25.00
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	19.64

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	main
Source file and lines	attention_v2.cpp:26-33
Module	attention-armclang-native

The loop is defined in /home/eoseret/llm-attention/attention_v2.cpp:26-33.

Analyzed code is defined in /home/eoseret/llm-attention/attention_v2.cpp:26-27,30-33.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Failed to get the number of paths
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 3.38 to 1.50 cycles (2.25x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is not vectorized. Only 18% of vector register length is used (average across all VPU instructions). By vectorizing your loop, you can lower the cost of an iteration from 3.38 to 0.48 cycles (7.00x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ffast-math (included in Ofast) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

FMA

Detected 1 FMA (fused multiply-add) operations.

Conversion instructions

Detected expensive conversion instructions.

Details

FCVT: 3 occurrences►
- /home/eoseret/llm-attention/attention_v2.cpp:31
- /home/eoseret/llm-attention/attention_v2.cpp:31
- /home/eoseret/llm-attention/attention_v2.cpp:33

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 2 FP arithmetical operations:

1: addition or subtraction (all inside FMA instructions)
1: multiply (all inside FMA instructions)

The binary loop is loading 6 bytes. The binary loop is storing 3 bytes.

Arithmetic intensity

Arithmetic intensity is 0.22 FP operations per loaded or stored byte.

General properties

nb instructions	28
nb uops	27
loop length	112
used w registers	8
used x registers	8
used b registers	0
used h registers	0
used s registers	4
used d registers	3
used q registers	0
used v registers	0
used z registers	0
nb stack references	3

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	3.38 cycles
front end	3.38 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	2.00	2.00	2.75	2.75	2.75	2.75	1.75	1.75	1.75	1.75	2.00	2.00	2.00	0.50	0.50
cycles	2.00	2.00	2.75	2.75	2.75	2.75	1.75	1.75	1.75	1.75	2.00	2.00	2.00	0.50	0.50

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	3.38
Dispatch	2.75
Overall L1	3.38

Vectorization ratios

INT

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

INT+FP

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

INT

all	18%
load	12%
store	18%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	21%

all	18%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	25%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	16%

INT+FP

all	18%
load	12%
store	18%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	25%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	19%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 3.38 cycles. At this rate:

1% of peak load performance is reached (1.78 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
1% of peak store performance is reached (0.89 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 3.38 to 2.75 cycles (1.23x speedup).

ASM code

In the binary file, the address of the loop is: 12380

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput	Vectorization
MOVI D0, #0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
ADD W13, W11, W12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MADD W12, W12, W23, W10	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
LDR S1, [X19, W13,UXTW #2]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (12.5%)
LDR S2, [X28, W12,UXTW #2]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (12.5%)
FCVT D1, S1	1	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
FCVT D2, S2	1	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
FMADD D0, D1, D2, D0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25	scal (25.0%)
LDR X13, [SP, #600]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
FCVT S0, D0	1	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	0	0	3	0.50	scal (25.0%)
ADD W12, W11, W10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X10, X10, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR S0, [X13, W12,UXTW #2]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (12.5%)
AND X12, X23, #0x7fffffff	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP X10, X12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	N/A
B.EQ 12320 <main+0x1360>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X12, [SP, #608]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CBZ X12, 12340 <main+0x1380>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVI D0, #0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
AND X16, X23, #0x0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ORR X12, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR X13, XZR, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR W14, WZR, W9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
HINT #0																			N/A
AND X13, X23, #0x0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR X13, [SP, #592]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
TBNZ W23, #0, 12344 <main+0x1384>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
B 12360 <main+0x13a0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Function	main
Source file and lines	attention_v2.cpp:26-33
Module	attention-armclang-native

The loop is defined in /home/eoseret/llm-attention/attention_v2.cpp:26-33.

Analyzed code is defined in /home/eoseret/llm-attention/attention_v2.cpp:26-27,30-33.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Failed to get the number of paths
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 3.38 to 1.50 cycles (2.25x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ffast-math (included in Ofast) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

FMA

Detected 1 FMA (fused multiply-add) operations.

Conversion instructions

Detected expensive conversion instructions.

Details

FCVT: 3 occurrences►
- /home/eoseret/llm-attention/attention_v2.cpp:31
- /home/eoseret/llm-attention/attention_v2.cpp:31
- /home/eoseret/llm-attention/attention_v2.cpp:33

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 2 FP arithmetical operations:

1: addition or subtraction (all inside FMA instructions)
1: multiply (all inside FMA instructions)

The binary loop is loading 6 bytes. The binary loop is storing 3 bytes.

Arithmetic intensity

Arithmetic intensity is 0.22 FP operations per loaded or stored byte.

General properties

nb instructions	28
nb uops	27
loop length	112
used w registers	8
used x registers	8
used b registers	0
used h registers	0
used s registers	4
used d registers	3
used q registers	0
used v registers	0
used z registers	0
nb stack references	3

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	3.38 cycles
front end	3.38 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	2.00	2.00	2.75	2.75	2.75	2.75	1.75	1.75	1.75	1.75	2.00	2.00	2.00	0.50	0.50
cycles	2.00	2.00	2.75	2.75	2.75	2.75	1.75	1.75	1.75	1.75	2.00	2.00	2.00	0.50	0.50

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	3.38
Dispatch	2.75
Overall L1	3.38

Vectorization ratios

INT

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

INT+FP

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

INT

all	18%
load	12%
store	18%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	21%

all	18%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	25%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	16%

INT+FP

all	18%
load	12%
store	18%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	25%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	19%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 3.38 cycles. At this rate:

1% of peak load performance is reached (1.78 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
1% of peak store performance is reached (0.89 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the loop is: 12380

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput	Vectorization
MOVI D0, #0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
ADD W13, W11, W12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MADD W12, W12, W23, W10	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
LDR S1, [X19, W13,UXTW #2]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (12.5%)
LDR S2, [X28, W12,UXTW #2]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (12.5%)
FCVT D1, S1	1	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
FCVT D2, S2	1	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
FMADD D0, D1, D2, D0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25	scal (25.0%)
LDR X13, [SP, #600]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
FCVT S0, D0	1	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	0	0	3	0.50	scal (25.0%)
ADD W12, W11, W10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X10, X10, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR S0, [X13, W12,UXTW #2]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (12.5%)
AND X12, X23, #0x7fffffff	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP X10, X12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	N/A
B.EQ 12320 <main+0x1360>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X12, [SP, #608]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CBZ X12, 12340 <main+0x1380>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVI D0, #0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
AND X16, X23, #0x0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ORR X12, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR X13, XZR, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR W14, WZR, W9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
HINT #0																			N/A
AND X13, X23, #0x0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR X13, [SP, #592]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
TBNZ W23, #0, 12344 <main+0x1384>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
B 12360 <main+0x13a0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

FMA

Conversion instructions

Details

Workaround

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

FMA

Conversion instructions

Details

Workaround

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code