OV - attention-armclang-native - Loop 59 - attention-armclang-native

	Loop Id: 59	Module: attention-armclang-native	Source: attention_v2.cpp:26-33	Coverage: 0.55%

0x12464 MOVI	D0, #0

0x12468 ADD	W13, W11, W12

0x1246c MADD	W12, W12, W23, W10

0x12470 LDR	S1, [X19, W13,UXTW #2]

0x12474 LDR	S2, [X26, W12,UXTW #2]

0x12478 FCVT	D1, S1

0x1247c FCVT	D2, S2

0x12480 FMADD	D0, D1, D2, D0

0x12484 LDR	X13, [SP, #536]

0x12488 FCVT	S0, D0

0x1248c ADD	W12, W11, W10

0x12490 ADD	X10, X10, #1

0x12494 STR	S0, [X13, W12,UXTW #2]

0x12498 AND	X12, X23, #0x7fffffff

0x1249c CMP	X10, X12

0x124a0 B.EQ	12448

0x124a4 LDR	X12, [SP, #608]

0x124a8 CBZ	X12, 12464

0x124ac MOVI	D0, #0

0x124b0 AND	X16, X23, #0x0

0x124b4 ORR	X12, XZR, XZR

0x124b8 ORR	X13, XZR, X10

0x124bc ORR	W14, WZR, W9

  (60) 0x124c0 SUB	W15, W14, #1

  (60) 0x124c4 LDR	S2, [X26, W13,UXTW #2]

  (60) 0x124c8 ADD	X12, X12, #2

  (60) 0x124cc LDR	S1, [X19, W15,UXTW #2]

  (60) 0x124d0 ADD	W15, W23, W13

  (60) 0x124d4 ADD	X13, X13, X24

  (60) 0x124d8 CMP	X16, X12

  (60) 0x124dc FCVT	D2, S2

  (60) 0x124e0 FCVT	D1, S1

  (60) 0x124e4 FMADD	D0, D1, D2, D0

  (60) 0x124e8 LDR	S1, [X19, W14,UXTW #2]

  (60) 0x124ec LDR	S2, [X26, W15,UXTW #2]

  (60) 0x124f0 ADD	W14, W14, #2

  (60) 0x124f4 FCVT	D1, S1

  (60) 0x124f8 FCVT	D2, S2

  (60) 0x124fc FMADD	D0, D1, D2, D0

  (60) 0x12500 B.NE	124c0

0x12504 AND	X13, X23, #0x0

0x12508 STR	X13, [SP, #592]

0x1250c TBNZ	W23, #0, 12468

0x12510 B	12484

/home/eoseret/llm-attention/attention_v2.cpp: 26 - 33

--------------------------------------------------------------------------------

26:    for (unsigned int i = 0; i < M; ++i) {

27:       for (unsigned int j = 0; j < N; ++j) {  //vectorized

28:          double sum = 0.0;

29: #pragma clang loop vectorize(enable)

30:          for (unsigned int k = 0; k < K; ++k) { //vectorized

31:             sum += (double)A[i * K + k] * (double)B[k * N + j];

32:          }

33:          C[i * N + j] = alpha * static_cast<float>(sum);

Coverage (%)	Name	Module
►100.00+	__libc_start_call_main	libc.so.6
○	__libc_start_main	libc.so.6
○	_start	attention-armclang-native

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	1.94
CQA speedup if FP arith vectorized	1.41
CQA speedup if fully vectorized	6.99
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.13
Bottlenecks
Function	main
Source	attention_v2.cpp:26-27,attention_v2.cpp:30-33
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	2.58
CQA cycles if no scalar integer	1.33
CQA cycles if FP arith vectorized	1.83
CQA cycles if fully vectorized	0.37
Front-end cycles	2.58
P0 cycles	1.50
P1 cycles	1.50
P2 cycles	2.17
P3 cycles	2.17
P4 cycles	2.17
P5 cycles	2.17
P6 cycles	1.33
P7 cycles	1.25
P8 cycles	1.25
P9 cycles	1.17
P10 cycles	1.72
P11 cycles	1.61
P12 cycles	1.67
P13 cycles	0.33
P14 cycles	0.33
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	20.67
Nb uops	20.67
Nb loads	NA
Nb stores	1.67
Nb stack references	2.67
FLOP/cycle	0.52
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.67
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	2.71
Bytes prefetched	0.00
Bytes loaded	4.00
Bytes stored	3.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	0.00
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	18.73
Vector-efficiency ratio load	12.50
Vector-efficiency ratio store	16.67
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	25.00
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	19.79

Metric	Value
CQA speedup if no scalar integer	1.50
CQA speedup if FP arith vectorized	1.50
CQA speedup if fully vectorized	7.20
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.23
Bottlenecks	micro-operation queue,
Function	main
Source	attention_v2.cpp:26-27,attention_v2.cpp:30-33
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	2.25
CQA cycles if no scalar integer	1.50
CQA cycles if FP arith vectorized	1.50
CQA cycles if fully vectorized	0.31
Front-end cycles	2.25
P0 cycles	1.00
P1 cycles	1.00
P2 cycles	1.50
P3 cycles	1.50
P4 cycles	1.50
P5 cycles	1.50
P6 cycles	1.50
P7 cycles	1.50
P8 cycles	1.50
P9 cycles	1.50
P10 cycles	1.83
P11 cycles	1.50
P12 cycles	1.67
P13 cycles	0.00
P14 cycles	0.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	18.00
Nb uops	18.00
Nb loads	NA
Nb stores	1.00
Nb stack references	2.00
FLOP/cycle	0.89
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	1.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	4.00
Bytes prefetched	0.00
Bytes loaded	6.00
Bytes stored	3.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	0.00
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	17.19
Vector-efficiency ratio load	12.50
Vector-efficiency ratio store	12.50
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	25.00
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	18.75

Metric	Value
CQA speedup if no scalar integer	2.38
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	6.91
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.06
Bottlenecks	micro-operation queue,
Function	main
Source	attention_v2.cpp:26-27,attention_v2.cpp:30-33
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	2.38
CQA cycles if no scalar integer	1.00
CQA cycles if FP arith vectorized	2.38
CQA cycles if fully vectorized	0.34
Front-end cycles	2.38
P0 cycles	2.00
P1 cycles	2.00
P2 cycles	2.25
P3 cycles	2.25
P4 cycles	2.25
P5 cycles	2.25
P6 cycles	1.00
P7 cycles	0.75
P8 cycles	0.75
P9 cycles	0.50
P10 cycles	1.33
P11 cycles	1.33
P12 cycles	1.33
P13 cycles	0.50
P14 cycles	0.50
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	19.00
Nb uops	19.00
Nb loads	NA
Nb stores	2.00
Nb stack references	3.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	1.26
Bytes prefetched	0.00
Bytes loaded	0.00
Bytes stored	3.00
Stride 0	0.00
Stride 1	0.00
Stride n	0.00
Stride unknown	1.00
Stride indirect	1.00
Vectorization ratio all	0.00
Vectorization ratio load	NA
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	20.83
Vector-efficiency ratio load	NA
Vector-efficiency ratio store	18.75
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	21.88

Metric	Value
CQA speedup if no scalar integer	2.08
CQA speedup if FP arith vectorized	1.92
CQA speedup if fully vectorized	6.90
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.14
Bottlenecks	micro-operation queue,
Function	main
Source	attention_v2.cpp:26-27,attention_v2.cpp:30-33
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	3.13
CQA cycles if no scalar integer	1.50
CQA cycles if FP arith vectorized	1.63
CQA cycles if fully vectorized	0.45
Front-end cycles	3.13
P0 cycles	1.50
P1 cycles	1.50
P2 cycles	2.75
P3 cycles	2.75
P4 cycles	2.75
P5 cycles	2.75
P6 cycles	1.50
P7 cycles	1.50
P8 cycles	1.50
P9 cycles	1.50
P10 cycles	2.00
P11 cycles	2.00
P12 cycles	2.00
P13 cycles	0.50
P14 cycles	0.50
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	25.00
Nb uops	25.00
Nb loads	NA
Nb stores	2.00
Nb stack references	3.00
FLOP/cycle	0.64
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	1.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	2.88
Bytes prefetched	0.00
Bytes loaded	6.00
Bytes stored	3.00
Stride 0	0.00
Stride 1	0.00
Stride n	0.00
Stride unknown	1.00
Stride indirect	1.00
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	0.00
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	18.18
Vector-efficiency ratio load	12.50
Vector-efficiency ratio store	18.75
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	25.00
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	18.75

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	main
Source file and lines	attention_v2.cpp:26-33
Module	attention-armclang-native

The loop is defined in /home/eoseret/llm-attention/attention_v2.cpp:26-33.

Analyzed code is defined in /home/eoseret/llm-attention/attention_v2.cpp:26-27,30-33.

Warnings:
Non-innermost loop: analyzing only self part (ignoring child loops).
This loop has 3 execution paths.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. Only 18% of vector register length is used (average across all VPU instructions). By vectorizing your loop, you can lower the cost of an iteration from 2.58 to 0.37 cycles (6.99x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ffast-math (included in Ofast) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

FMA

Detected 0.67 FMA (fused multiply-add) operations.

Conversion instructions

Detected expensive conversion instructions.

Details

FCVT: 0 occurrences

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 1.3333333333333 FP arithmetical operations:

0.67: addition or subtraction (all inside FMA instructions)
0.67: multiply (all inside FMA instructions)

The binary loop is loading 4 bytes. The binary loop is storing 3 bytes.

Arithmetic intensity

Arithmetic intensity is 0.19 FP operations per loaded or stored byte.

General properties

nb instructions	20.67
nb uops	20.67
loop length	82.67
used w registers	6.67
used x registers	6.67
used b registers	0
used h registers	0
used s registers	3.33
used d registers	2.33
used q registers	0
used v registers	0
used z registers	0
nb stack references	2.67

Front-end

MACRO FUSION NOT POSSIBLE

micro-operation queue	2.58 cycles
front end	2.58 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	1.50	1.50	2.17	2.17	2.17	2.17	1.33	1.25	1.25	1.17	1.72	1.61	1.67	0.33	0.33
cycles	1.50	1.50	2.17	2.17	2.17	2.17	1.33	1.25	1.25	1.17	1.72	1.61	1.67	0.33	0.33

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	2.58
Dispatch	2.28
Data deps.	1.00
Overall L1	2.58

Vectorization ratios

INT

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

INT+FP

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

INT

all	17%
load	12%
store	16%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	22%

all	20%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	25%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	19%

INT+FP

all	18%
load	12%
store	16%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	25%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	19%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 2.58 cycles. At this rate:

1% of peak load performance is reached (1.53 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
2% of peak store performance is reached (1.19 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

Function	main
Source file and lines	attention_v2.cpp:26-33
Module	attention-armclang-native

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 2.25 to 1.50 cycles (1.50x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is not vectorized. Only 17% of vector register length is used (average across all VPU instructions). By vectorizing your loop, you can lower the cost of an iteration from 2.25 to 0.31 cycles (7.20x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ffast-math (included in Ofast) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

FMA

Detected 1 FMA (fused multiply-add) operations.

Conversion instructions

Detected expensive conversion instructions.

Details

FCVT: 3 occurrences►
- /home/eoseret/llm-attention/attention_v2.cpp:31
- /home/eoseret/llm-attention/attention_v2.cpp:31
- /home/eoseret/llm-attention/attention_v2.cpp:33

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 2 FP arithmetical operations:

1: addition or subtraction (all inside FMA instructions)
1: multiply (all inside FMA instructions)

The binary loop is loading 6 bytes. The binary loop is storing 3 bytes.

Arithmetic intensity

Arithmetic intensity is 0.22 FP operations per loaded or stored byte.

General properties

nb instructions	18
nb uops	18
loop length	72
used w registers	5
used x registers	6
used b registers	0
used h registers	0
used s registers	4
used d registers	3
used q registers	0
used v registers	0
used z registers	0
nb stack references	2

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	2.25 cycles
front end	2.25 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	1.00	1.00	1.50	1.50	1.50	1.50	1.50	1.50	1.50	1.50	1.83	1.50	1.67	0.00	0.00
cycles	1.00	1.00	1.50	1.50	1.50	1.50	1.50	1.50	1.50	1.50	1.83	1.50	1.67	0.00	0.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	2.25
Dispatch	1.83
Data deps.	1.00
Overall L1	2.25

Vectorization ratios

INT

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

INT+FP

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

INT

all	15%
load	12%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	25%

all	18%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	25%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	16%

INT+FP

all	17%
load	12%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	25%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	18%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 2.25 cycles. At this rate:

2% of peak load performance is reached (2.67 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
2% of peak store performance is reached (1.33 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 2.25 to 1.83 cycles (1.23x speedup).

ASM code

In the binary file, the address of the loop is: 124a4

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	Latency	Recip. throughput	Vectorization
MOVI D0, #0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (25.0%)
ADD W13, W11, W12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
MADD W12, W12, W23, W10	1	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	N/A
LDR S1, [X19, W13,UXTW #2]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (12.5%)
LDR S2, [X26, W12,UXTW #2]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (12.5%)
FCVT D1, S1	1	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	3	0.50	scal (12.5%)
FCVT D2, S2	1	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	3	0.50	scal (12.5%)
FMADD D0, D1, D2, D0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	scal (25.0%)
LDR X13, [SP, #536]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
FCVT S0, D0	1	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	3	0.50	scal (25.0%)
ADD W12, W11, W10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
ADD X10, X10, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
STR S0, [X13, W12,UXTW #2]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	scal (12.5%)
AND X12, X23, #0x7fffffff	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
CMP X10, X12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33	N/A
B.EQ 12448 <main+0x1488>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X12, [SP, #608]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
CBZ X12, 12464 <main+0x14a4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Function	main
Source file and lines	attention_v2.cpp:26-33
Module	attention-armclang-native

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 2.38 to 1.00 cycles (2.37x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is not vectorized. Only 20% of vector register length is used (average across all VPU instructions). By vectorizing your loop, you can lower the cost of an iteration from 2.38 to 0.34 cycles (6.91x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ffast-math (included in Ofast) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant unknown stride: 1 occurrence(s)
Irregular (variable stride) or indirect: 1 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)
Try to remove indirect accesses. If applicable, precompute elements out of the innermost loop.

Conversion instructions

Detected expensive conversion instructions.

Details

FCVT: 1 occurrences►
- /home/eoseret/llm-attention/attention_v2.cpp:33

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is storing 3 bytes.

General properties

nb instructions	19
nb uops	19
loop length	76
used w registers	7
used x registers	6
used b registers	0
used h registers	0
used s registers	2
used d registers	1
used q registers	0
used v registers	0
used z registers	0
nb stack references	3

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	2.38 cycles
front end	2.38 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	2.00	2.00	2.25	2.25	2.25	2.25	1.00	0.75	0.75	0.50	1.33	1.33	1.33	0.50	0.50
cycles	2.00	2.00	2.25	2.25	2.25	2.25	1.00	0.75	0.75	0.50	1.33	1.33	1.33	0.50	0.50

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	2.38
Dispatch	2.25
Data deps.	1.00
Overall L1	2.38

Vectorization ratios

INT

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

INT+FP

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

INT

all	20%
load	NA (no load vectorizable/vectorized instructions)
store	18%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	20%

all	25%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	25%

INT+FP

all	20%
load	NA (no load vectorizable/vectorized instructions)
store	18%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	21%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 2.38 cycles. At this rate:

2% of peak store performance is reached (1.26 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the loop is: 124a4

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput	Vectorization
LDR X13, [SP, #536]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
FCVT S0, D0	1	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	0	0	3	0.50	scal (25.0%)
ADD W12, W11, W10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X10, X10, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR S0, [X13, W12,UXTW #2]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (12.5%)
AND X12, X23, #0x7fffffff	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP X10, X12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	N/A
B.EQ 12448 <main+0x1488>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X12, [SP, #608]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CBZ X12, 12464 <main+0x14a4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVI D0, #0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
AND X16, X23, #0x0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ORR X12, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR X13, XZR, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR W14, WZR, W9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
AND X13, X23, #0x0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR X13, [SP, #592]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
TBNZ W23, #0, 12468 <main+0x14a8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
B 12484 <main+0x14c4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Function	main
Source file and lines	attention_v2.cpp:26-33
Module	attention-armclang-native

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 3.13 to 1.50 cycles (2.08x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ffast-math (included in Ofast) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

FMA

Detected 1 FMA (fused multiply-add) operations.

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant unknown stride: 1 occurrence(s)
Irregular (variable stride) or indirect: 1 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)
Try to remove indirect accesses. If applicable, precompute elements out of the innermost loop.

Conversion instructions

Detected expensive conversion instructions.

Details

FCVT: 3 occurrences►
- /home/eoseret/llm-attention/attention_v2.cpp:31
- /home/eoseret/llm-attention/attention_v2.cpp:31
- /home/eoseret/llm-attention/attention_v2.cpp:33

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 2 FP arithmetical operations:

1: addition or subtraction (all inside FMA instructions)
1: multiply (all inside FMA instructions)

The binary loop is loading 6 bytes. The binary loop is storing 3 bytes.

Arithmetic intensity

Arithmetic intensity is 0.22 FP operations per loaded or stored byte.

General properties

nb instructions	25
nb uops	25
loop length	100
used w registers	8
used x registers	8
used b registers	0
used h registers	0
used s registers	4
used d registers	3
used q registers	0
used v registers	0
used z registers	0
nb stack references	3

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	3.13 cycles
front end	3.13 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	1.50	1.50	2.75	2.75	2.75	2.75	1.50	1.50	1.50	1.50	2.00	2.00	2.00	0.50	0.50
cycles	1.50	1.50	2.75	2.75	2.75	2.75	1.50	1.50	1.50	1.50	2.00	2.00	2.00	0.50	0.50

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	3.13
Dispatch	2.75
Data deps.	1.00
Overall L1	3.13

Vectorization ratios

INT

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

INT+FP

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

INT

all	17%
load	12%
store	18%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	20%

all	18%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	25%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	16%

INT+FP

all	18%
load	12%
store	18%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	25%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	18%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 3.13 cycles. At this rate:

2% of peak load performance is reached (1.92 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
2% of peak store performance is reached (0.96 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the loop is: 124a4

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput	Vectorization
ADD W13, W11, W12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MADD W12, W12, W23, W10	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
LDR S1, [X19, W13,UXTW #2]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (12.5%)
LDR S2, [X26, W12,UXTW #2]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (12.5%)
FCVT D1, S1	1	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
FCVT D2, S2	1	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
FMADD D0, D1, D2, D0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25	scal (25.0%)
LDR X13, [SP, #536]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
FCVT S0, D0	1	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	0	0	3	0.50	scal (25.0%)
ADD W12, W11, W10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X10, X10, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR S0, [X13, W12,UXTW #2]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (12.5%)
AND X12, X23, #0x7fffffff	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP X10, X12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	N/A
B.EQ 12448 <main+0x1488>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X12, [SP, #608]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CBZ X12, 12464 <main+0x14a4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVI D0, #0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
AND X16, X23, #0x0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ORR X12, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR X13, XZR, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR W14, WZR, W9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
AND X13, X23, #0x0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR X13, [SP, #592]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
TBNZ W23, #0, 12468 <main+0x14a8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Report Configuration

Vectorization

Details

Workaround

FMA

Conversion instructions

Details

Workaround

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Code clean check

Workaround

Vectorization

Details

Workaround

FMA

Conversion instructions

Details

Workaround

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Slow data structures access

Details

Workaround

Conversion instructions

Details

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

FMA

Slow data structures access

Details

Workaround

Conversion instructions

Details

Workaround

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks