| Loop Id: 49 | Module: attention-armclang-native | Source: attention_v2.cpp:27-33 | Coverage: 4.47% |
|---|
| Loop Id: 49 | Module: attention-armclang-native | Source: attention_v2.cpp:27-33 | Coverage: 4.47% |
|---|
0x12880 FCVT S0, D0 |
0x12884 LDR X15, [SP, #544] |
0x12888 ADD W14, W12, W10 |
0x1288c ADD X10, X10, #1 |
0x12890 CMP X10, X26 |
0x12894 FDIV S0, S0, S9 |
0x12898 STR S0, [X15, W14,UXTW #2] |
0x1289c B.EQ 12848 |
0x128a0 CNTW X15, ALL |
0x128a4 MOVI D0, #0 |
0x128a8 AND X14, X23, #0x7fffffff |
0x128ac CMP X14, X15 |
0x128b0 B.CC 128c4 |
0x128b4 LDR X14, [SP, #608] |
0x128b8 CMN W10, W14 |
0x128bc CSINC W14, W13, WZR, #3 |
0x128c0 TBZ W14, #0, 12984 |
0x128c4 ORR X15, XZR, XZR |
0x128c8 SUB W16, W23, W15 |
0x128cc ADD X14, X15, #1 |
0x128d0 TBZ W16, #0, 128fc |
0x128d4 LDR X17, [SP, #600] |
0x128d8 ADD W16, W11, W15 |
0x128dc MADD W15, W15, W27, W10 |
0x128e0 LDR S1, [X17, W16,UXTW #2] |
0x128e4 LDR X16, [SP, #584] |
0x128e8 LDR S2, [X16, W15,UXTW #2] |
0x128ec ORR X15, XZR, X14 |
0x128f0 FCVT D1, S1 |
0x128f4 FCVT D2, S2 |
0x128f8 FMADD D0, D1, D2, D0 |
0x128fc LDR X0, [SP, #600] |
0x12900 LDR X1, [SP, #520] |
0x12904 LDR X2, [SP, #584] |
0x12908 AND X16, X23, #0x7fffffff |
0x1290c CMP X16, X14 |
0x12910 B.EQ 12880 |
0x12914 MUL X17, X27, X15 |
0x12918 AND X14, X23, #0x7fffffff |
0x1291c ADD X18, X10, X27 |
0x12920 SUB X14, X14, X15 |
0x12924 ADD W15, W8, W15 |
0x12928 ADD X16, X10, X17 |
0x1292c ADD X17, X18, X17 |
0x12930 HINT #0 |
0x12934 HINT #0 |
0x12938 HINT #0 |
0x1293c HINT #0 |
(50) 0x12940 LDR S1, [X0, W15,UXTW #2] |
(50) 0x12944 LDR S2, [X2, W16,UXTW #2] |
(50) 0x12948 ADD W18, W15, #1 |
(50) 0x1294c SUBS X14, X14, #2 |
(50) 0x12950 ADD X16, X16, X1 |
(50) 0x12954 ADD W15, W15, #2 |
(50) 0x12958 FCVT D1, S1 |
(50) 0x1295c FCVT D2, S2 |
(50) 0x12960 FMADD D0, D1, D2, D0 |
(50) 0x12964 LDR S1, [X0, W18,UXTW #2] |
(50) 0x12968 LDR S2, [X2, W17,UXTW #2] |
(50) 0x1296c ADD X17, X17, X1 |
(50) 0x12970 FCVT D1, S1 |
(50) 0x12974 FCVT D2, S2 |
(50) 0x12978 FMADD D0, D1, D2, D0 |
(50) 0x1297c B.NE 12940 |
0x12980 B 12880 |
0x12984 LDR X18, [SP, #480] |
0x12988 LDR X0, [SP, #600] |
0x1298c LDR X1, [SP, #584] |
0x12990 MOVI V0.2D, #0 |
0x12994 MOVI V1.2D, #0 |
0x12998 CNTW X17, ALL |
0x1299c PTRUE P0.D, ALL |
0x129a0 ORR X14, XZR, XZR |
(51) 0x129a4 ADD W15, W8, W14 |
(51) 0x129a8 ADD X16, X0, W15,UXTW #2 |
(51) 0x129ac LD1W {Z2.D}, P0/Z, [X0, X15,LSL #2] |
(51) 0x129b0 ADD W15, W10, W14 |
(51) 0x129b4 ADD X14, X14, X17 |
(51) 0x129b8 LD1W {Z4.D}, P0/Z, [X1, X15,LSL #2] |
(51) 0x129bc CMP X18, X14 |
(51) 0x129c0 LD1W {Z3.D}, P0/Z, [X16, #1, MUL VL] |
(51) 0x129c4 ADD X16, X1, W15,UXTW #2 |
(51) 0x129c8 LD1W {Z5.D}, P0/Z, [X16, #1, MUL VL] |
(51) 0x129cc FCVT Z2.D, P0/M, Z2.S |
(51) 0x129d0 FCVT Z4.D, P0/M, Z4.S |
(51) 0x129d4 FCVT Z3.D, P0/M, Z3.S |
(51) 0x129d8 FCVT Z5.D, P0/M, Z5.S |
(51) 0x129dc FMLA Z0.D, P0/M, Z2.D, Z4.D |
(51) 0x129e0 FMLA Z1.D, P0/M, Z3.D, Z5.D |
(51) 0x129e4 B.NE 129a4 |
0x129e8 FADD Z0.D, Z1.D, Z0.D |
0x129ec AND X14, X23, #0x7fffffff |
0x129f0 ORR X15, XZR, X18 |
0x129f4 CMP X14, X18 |
0x129f8 FADDV D0, P0, Z0.D |
0x129fc B.EQ 12880 |
0x12a00 B 128c8 |
/home/eoseret/llm-attention/attention_v2.cpp: 27 - 33 |
-------------------------------------------------------------------------------- |
27: for (unsigned int j = 0; j < N; ++j) { //vectorized |
28: double sum = 0.0; |
29: #pragma clang loop vectorize(enable) |
30: for (unsigned int k = 0; k < K; ++k) { //vectorized |
31: sum += (double)A[i * K + k] * (double)B[k * N + j]; |
32: } |
33: C[i * N + j] = alpha * static_cast<float>(sum); |
| Coverage (%) | Name | Source Location | Module |
|---|---|---|---|
| ►100.00+ | __libc_start_call_main | libc.so.6 | |
| ○ | __libc_start_main | libc.so.6 | |
| ○ | _start | attention-armclang-native |
| min | med | avg | max |
|---|---|---|---|
| Percentile Index | 10 | 20 | 30 | 40 | 50 | 60 | 70 | 80 | 90 | 100 |
|---|---|---|---|---|---|---|---|---|---|---|
| Value |
| min | med | avg | max |
|---|---|---|---|
| Percentile Index | 10 | 20 | 30 | 40 | 50 | 60 | 70 | 80 | 90 | 100 |
|---|---|---|---|---|---|---|---|---|---|---|
| Value |
| Path / |
| Metric | Value |
|---|---|
| CQA speedup if no scalar integer | 3.75 |
| CQA speedup if FP arith vectorized | 1.03 |
| CQA speedup if fully vectorized | 1.26 |
| CQA speedup if no inter-iteration dependency | NA |
| CQA speedup if next bottleneck killed | 1.03 |
| Bottlenecks | micro-operation queue, |
| Function | main |
| Source | attention_v2.cpp:27-27,attention_v2.cpp:30-33 |
| Source loop unroll info | NA |
| Source loop unroll confidence level | NA |
| Unroll/vectorization loop type | NA |
| Unroll factor | NA |
| CQA cycles | 7.50 |
| CQA cycles if no scalar integer | 2.00 |
| CQA cycles if FP arith vectorized | 7.31 |
| CQA cycles if fully vectorized | 5.94 |
| Front-end cycles | 7.50 |
| P0 cycles | 4.00 |
| P1 cycles | 4.00 |
| P2 cycles | 7.25 |
| P3 cycles | 7.25 |
| P4 cycles | 7.25 |
| P5 cycles | 7.25 |
| P6 cycles | 3.00 |
| P7 cycles | 3.00 |
| P8 cycles | 3.00 |
| P9 cycles | 3.00 |
| P10 cycles | 4.50 |
| P11 cycles | 4.17 |
| P12 cycles | 4.33 |
| P13 cycles | 0.00 |
| P14 cycles | 0.00 |
| DIV/SQRT cycles | 0.87 - 1.13 |
| Inter-iter dependencies cycles | NA |
| FE+BE cycles (UFS) | NA |
| Stall cycles (UFS) | NA |
| Nb insns | 64.00 |
| Nb uops | 60.00 |
| Nb loads | NA |
| Nb stores | 1.00 |
| Nb stack references | 10.00 |
| FLOP/cycle | 1.47 |
| Nb FLOP add-sub | 8.00 |
| Nb FLOP mul | 0.00 |
| Nb FLOP fma | 1.00 |
| Nb FLOP div | 1.00 |
| Nb FLOP rcp | 0.00 |
| Nb FLOP sqrt | 0.00 |
| Nb FLOP rsqrt | 0.00 |
| Bytes/cycle | 1.20 |
| Bytes prefetched | 0.00 |
| Bytes loaded | 6.00 |
| Bytes stored | 3.00 |
| Stride 0 | NA |
| Stride 1 | NA |
| Stride n | NA |
| Stride unknown | NA |
| Stride indirect | NA |
| Vectorization ratio all | 7.69 |
| Vectorization ratio load | 0.00 |
| Vectorization ratio store | 0.00 |
| Vectorization ratio mul | NA |
| Vectorization ratio add_sub | 50.00 |
| Vectorization ratio fma | 0.00 |
| Vectorization ratio div_sqrt | 0.00 |
| Vectorization ratio other | 0.00 |
| Vector-efficiency ratio all | 30.29 |
| Vector-efficiency ratio load | 21.88 |
| Vector-efficiency ratio store | 12.50 |
| Vector-efficiency ratio mul | NA |
| Vector-efficiency ratio add_sub | 62.50 |
| Vector-efficiency ratio fma | 25.00 |
| Vector-efficiency ratio div_sqrt | 12.50 |
| Vector-efficiency ratio other | 28.41 |
| Metric | Value |
|---|---|
| CQA speedup if no scalar integer | 3.75 |
| CQA speedup if FP arith vectorized | 1.03 |
| CQA speedup if fully vectorized | 1.26 |
| CQA speedup if no inter-iteration dependency | NA |
| CQA speedup if next bottleneck killed | 1.03 |
| Bottlenecks | micro-operation queue, |
| Function | main |
| Source | attention_v2.cpp:27-27,attention_v2.cpp:30-33 |
| Source loop unroll info | NA |
| Source loop unroll confidence level | NA |
| Unroll/vectorization loop type | NA |
| Unroll factor | NA |
| CQA cycles | 7.50 |
| CQA cycles if no scalar integer | 2.00 |
| CQA cycles if FP arith vectorized | 7.31 |
| CQA cycles if fully vectorized | 5.94 |
| Front-end cycles | 7.50 |
| P0 cycles | 4.00 |
| P1 cycles | 4.00 |
| P2 cycles | 7.25 |
| P3 cycles | 7.25 |
| P4 cycles | 7.25 |
| P5 cycles | 7.25 |
| P6 cycles | 3.00 |
| P7 cycles | 3.00 |
| P8 cycles | 3.00 |
| P9 cycles | 3.00 |
| P10 cycles | 4.50 |
| P11 cycles | 4.17 |
| P12 cycles | 4.33 |
| P13 cycles | 0.00 |
| P14 cycles | 0.00 |
| DIV/SQRT cycles | 0.87 - 1.13 |
| Inter-iter dependencies cycles | NA |
| FE+BE cycles (UFS) | NA |
| Stall cycles (UFS) | NA |
| Nb insns | 64.00 |
| Nb uops | 60.00 |
| Nb loads | NA |
| Nb stores | 1.00 |
| Nb stack references | 10.00 |
| FLOP/cycle | 1.47 |
| Nb FLOP add-sub | 8.00 |
| Nb FLOP mul | 0.00 |
| Nb FLOP fma | 1.00 |
| Nb FLOP div | 1.00 |
| Nb FLOP rcp | 0.00 |
| Nb FLOP sqrt | 0.00 |
| Nb FLOP rsqrt | 0.00 |
| Bytes/cycle | 1.20 |
| Bytes prefetched | 0.00 |
| Bytes loaded | 6.00 |
| Bytes stored | 3.00 |
| Stride 0 | NA |
| Stride 1 | NA |
| Stride n | NA |
| Stride unknown | NA |
| Stride indirect | NA |
| Vectorization ratio all | 7.69 |
| Vectorization ratio load | 0.00 |
| Vectorization ratio store | 0.00 |
| Vectorization ratio mul | NA |
| Vectorization ratio add_sub | 50.00 |
| Vectorization ratio fma | 0.00 |
| Vectorization ratio div_sqrt | 0.00 |
| Vectorization ratio other | 0.00 |
| Vector-efficiency ratio all | 30.29 |
| Vector-efficiency ratio load | 21.88 |
| Vector-efficiency ratio store | 12.50 |
| Vector-efficiency ratio mul | NA |
| Vector-efficiency ratio add_sub | 62.50 |
| Vector-efficiency ratio fma | 25.00 |
| Vector-efficiency ratio div_sqrt | 12.50 |
| Vector-efficiency ratio other | 28.41 |
| Path / |
| Function | main |
| Source file and lines | attention_v2.cpp:27-33 |
| Module | attention-armclang-native |
| nb instructions | 64 |
| nb uops | 60 |
| loop length | 256 |
| used w registers | 11 |
| used x registers | 13 |
| used b registers | 0 |
| used h registers | 0 |
| used s registers | 5 |
| used d registers | 3 |
| used q registers | 0 |
| used v registers | 2 |
| used z registers | 2 |
| nb stack references | 10 |
| micro-operation queue | 7.50 cycles |
| front end | 7.50 cycles |
| P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | P12 | P13 | P14 | |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| uops | 4.00 | 4.00 | 7.25 | 7.25 | 7.25 | 7.25 | 3.00 | 3.00 | 3.00 | 3.00 | 4.50 | 4.17 | 4.33 | 0.00 | 0.00 |
| cycles | 4.00 | 4.00 | 7.25 | 7.25 | 7.25 | 7.25 | 3.00 | 3.00 | 3.00 | 3.00 | 4.50 | 4.17 | 4.33 | 0.00 | 0.00 |
| Cycles executing div or sqrt instructions | 0.87-1.13 |
| Front-end | 7.50 |
| Dispatch | 7.25 |
| DIV/SQRT | 0.87-1.13 |
| Overall L1 | 7.50 |
| all | 0% |
| load | 0% |
| store | 0% |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | 0% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| other | 0% |
| all | 28% |
| load | NA (no load vectorizable/vectorized instructions) |
| store | NA (no store vectorizable/vectorized instructions) |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | 100% |
| fma | 0% |
| div/sqrt | 0% |
| other | 0% |
| all | 7% |
| load | 0% |
| store | 0% |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | 50% |
| fma | 0% |
| div/sqrt | 0% |
| other | 0% |
| all | 26% |
| load | 21% |
| store | 12% |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | 25% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| other | 32% |
| all | 41% |
| load | NA (no load vectorizable/vectorized instructions) |
| store | NA (no store vectorizable/vectorized instructions) |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | 100% |
| fma | 25% |
| div/sqrt | 12% |
| other | 16% |
| all | 30% |
| load | 21% |
| store | 12% |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | 62% |
| fma | 25% |
| div/sqrt | 12% |
| other | 28% |
| Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | P12 | P13 | P14 | Latency | Recip. throughput | Vectorization |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| FCVT S0, D0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 | scal (25.0%) |
| LDR X15, [SP, #544] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 | N/A |
| ADD W14, W12, W10 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | N/A |
| ADD X10, X10, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | scal (25.0%) |
| CMP X10, X26 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 | scal (25.0%) |
| FDIV S0, S0, S9 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 7-10 | 0.87-1.13 | scal (12.5%) |
| STR S0, [X15, W14,UXTW #2] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 2 | 0.50 | scal (12.5%) |
| B.EQ 12848 <main+0x1888> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | N/A |
| CNTW X15, ALL | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 1 | N/A |
| MOVI D0, #0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 2 | 0.25 | N/A |
| AND X14, X23, #0x7fffffff | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | N/A |
| CMP X14, X15 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 | scal (25.0%) |
| B.CC 128c4 <main+0x1904> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | N/A |
| LDR X14, [SP, #608] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 | N/A |
| CMN W10, W14 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 | scal (12.5%) |
| CSINC W14, W13, WZR, #3 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | N/A |
| TBZ W14, #0, 12984 <main+0x19c4> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | N/A |
| ORR X15, XZR, XZR | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | N/A |
| SUB W16, W23, W15 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | N/A |
| ADD X14, X15, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | N/A |
| TBZ W16, #0, 128fc <main+0x193c> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | N/A |
| LDR X17, [SP, #600] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 | N/A |
| ADD W16, W11, W15 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | N/A |
| MADD W15, W15, W27, W10 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 1 | N/A |
| LDR S1, [X17, W16,UXTW #2] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 6 | 0.33 | scal (12.5%) |
| LDR X16, [SP, #584] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 | N/A |
| LDR S2, [X16, W15,UXTW #2] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 6 | 0.33 | scal (12.5%) |
| ORR X15, XZR, X14 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | N/A |
| FCVT D1, S1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 | scal (12.5%) |
| FCVT D2, S2 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 | scal (12.5%) |
| FMADD D0, D1, D2, D0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 4 | 0.25 | scal (25.0%) |
| LDR X0, [SP, #600] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 | scal (25.0%) |
| LDR X1, [SP, #520] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 | scal (25.0%) |
| LDR X2, [SP, #584] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 | scal (25.0%) |
| AND X16, X23, #0x7fffffff | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | N/A |
| CMP X16, X14 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 | scal (25.0%) |
| B.EQ 12880 <main+0x18c0> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | N/A |
| MUL X17, X27, X15 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 0.50 | N/A |
| AND X14, X23, #0x7fffffff | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | N/A |
| ADD X18, X10, X27 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | scal (25.0%) |
| SUB X14, X14, X15 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | N/A |
| ADD W15, W8, W15 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | N/A |
| ADD X16, X10, X17 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | N/A |
| ADD X17, X18, X17 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | N/A |
| HINT #0 | N/A | ||||||||||||||||||
| HINT #0 | N/A | ||||||||||||||||||
| HINT #0 | N/A | ||||||||||||||||||
| HINT #0 | N/A | ||||||||||||||||||
| B 12880 <main+0x18c0> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | N/A |
| LDR X18, [SP, #480] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 | scal (25.0%) |
| LDR X0, [SP, #600] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 | scal (25.0%) |
| LDR X1, [SP, #584] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 | scal (25.0%) |
| MOVI V0.2D, #0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 2 | 0.25 | scal (25.0%) |
| MOVI V1.2D, #0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 2 | 0.25 | scal (25.0%) |
| CNTW X17, ALL | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 1 | N/A |
| PTRUE P0.D, ALL | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 1 | scal (100.0%) |
| ORR X14, XZR, XZR | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | N/A |
| FADD Z0.D, Z1.D, Z0.D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 0.50 | vect (100.0%) |
| AND X14, X23, #0x7fffffff | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | N/A |
| ORR X15, XZR, X18 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | N/A |
| CMP X14, X18 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 | scal (25.0%) |
| FADDV D0, P0, Z0.D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.75 | 0.75 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 9 | 2 | vect (100.0%) |
| B.EQ 12880 <main+0x18c0> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | N/A |
| B 128c8 <main+0x1908> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | N/A |
| Function | main |
| Source file and lines | attention_v2.cpp:27-33 |
| Module | attention-armclang-native |
| nb instructions | 64 |
| nb uops | 60 |
| loop length | 256 |
| used w registers | 11 |
| used x registers | 13 |
| used b registers | 0 |
| used h registers | 0 |
| used s registers | 5 |
| used d registers | 3 |
| used q registers | 0 |
| used v registers | 2 |
| used z registers | 2 |
| nb stack references | 10 |
| micro-operation queue | 7.50 cycles |
| front end | 7.50 cycles |
| P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | P12 | P13 | P14 | |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| uops | 4.00 | 4.00 | 7.25 | 7.25 | 7.25 | 7.25 | 3.00 | 3.00 | 3.00 | 3.00 | 4.50 | 4.17 | 4.33 | 0.00 | 0.00 |
| cycles | 4.00 | 4.00 | 7.25 | 7.25 | 7.25 | 7.25 | 3.00 | 3.00 | 3.00 | 3.00 | 4.50 | 4.17 | 4.33 | 0.00 | 0.00 |
| Cycles executing div or sqrt instructions | 0.87-1.13 |
| Front-end | 7.50 |
| Dispatch | 7.25 |
| DIV/SQRT | 0.87-1.13 |
| Overall L1 | 7.50 |
| all | 0% |
| load | 0% |
| store | 0% |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | 0% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| other | 0% |
| all | 28% |
| load | NA (no load vectorizable/vectorized instructions) |
| store | NA (no store vectorizable/vectorized instructions) |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | 100% |
| fma | 0% |
| div/sqrt | 0% |
| other | 0% |
| all | 7% |
| load | 0% |
| store | 0% |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | 50% |
| fma | 0% |
| div/sqrt | 0% |
| other | 0% |
| all | 26% |
| load | 21% |
| store | 12% |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | 25% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| other | 32% |
| all | 41% |
| load | NA (no load vectorizable/vectorized instructions) |
| store | NA (no store vectorizable/vectorized instructions) |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | 100% |
| fma | 25% |
| div/sqrt | 12% |
| other | 16% |
| all | 30% |
| load | 21% |
| store | 12% |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | 62% |
| fma | 25% |
| div/sqrt | 12% |
| other | 28% |
| Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | P12 | P13 | P14 | Latency | Recip. throughput | Vectorization |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| FCVT S0, D0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 | scal (25.0%) |
| LDR X15, [SP, #544] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 | N/A |
| ADD W14, W12, W10 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | N/A |
| ADD X10, X10, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | scal (25.0%) |
| CMP X10, X26 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 | scal (25.0%) |
| FDIV S0, S0, S9 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 7-10 | 0.87-1.13 | scal (12.5%) |
| STR S0, [X15, W14,UXTW #2] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 2 | 0.50 | scal (12.5%) |
| B.EQ 12848 <main+0x1888> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | N/A |
| CNTW X15, ALL | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 1 | N/A |
| MOVI D0, #0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 2 | 0.25 | N/A |
| AND X14, X23, #0x7fffffff | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | N/A |
| CMP X14, X15 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 | scal (25.0%) |
| B.CC 128c4 <main+0x1904> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | N/A |
| LDR X14, [SP, #608] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 | N/A |
| CMN W10, W14 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 | scal (12.5%) |
| CSINC W14, W13, WZR, #3 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | N/A |
| TBZ W14, #0, 12984 <main+0x19c4> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | N/A |
| ORR X15, XZR, XZR | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | N/A |
| SUB W16, W23, W15 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | N/A |
| ADD X14, X15, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | N/A |
| TBZ W16, #0, 128fc <main+0x193c> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | N/A |
| LDR X17, [SP, #600] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 | N/A |
| ADD W16, W11, W15 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | N/A |
| MADD W15, W15, W27, W10 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 1 | N/A |
| LDR S1, [X17, W16,UXTW #2] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 6 | 0.33 | scal (12.5%) |
| LDR X16, [SP, #584] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 | N/A |
| LDR S2, [X16, W15,UXTW #2] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 6 | 0.33 | scal (12.5%) |
| ORR X15, XZR, X14 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | N/A |
| FCVT D1, S1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 | scal (12.5%) |
| FCVT D2, S2 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 | scal (12.5%) |
| FMADD D0, D1, D2, D0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 4 | 0.25 | scal (25.0%) |
| LDR X0, [SP, #600] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 | scal (25.0%) |
| LDR X1, [SP, #520] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 | scal (25.0%) |
| LDR X2, [SP, #584] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 | scal (25.0%) |
| AND X16, X23, #0x7fffffff | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | N/A |
| CMP X16, X14 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 | scal (25.0%) |
| B.EQ 12880 <main+0x18c0> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | N/A |
| MUL X17, X27, X15 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 0.50 | N/A |
| AND X14, X23, #0x7fffffff | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | N/A |
| ADD X18, X10, X27 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | scal (25.0%) |
| SUB X14, X14, X15 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | N/A |
| ADD W15, W8, W15 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | N/A |
| ADD X16, X10, X17 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | N/A |
| ADD X17, X18, X17 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | N/A |
| HINT #0 | N/A | ||||||||||||||||||
| HINT #0 | N/A | ||||||||||||||||||
| HINT #0 | N/A | ||||||||||||||||||
| HINT #0 | N/A | ||||||||||||||||||
| B 12880 <main+0x18c0> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | N/A |
| LDR X18, [SP, #480] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 | scal (25.0%) |
| LDR X0, [SP, #600] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 | scal (25.0%) |
| LDR X1, [SP, #584] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 | scal (25.0%) |
| MOVI V0.2D, #0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 2 | 0.25 | scal (25.0%) |
| MOVI V1.2D, #0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 2 | 0.25 | scal (25.0%) |
| CNTW X17, ALL | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 1 | N/A |
| PTRUE P0.D, ALL | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 1 | scal (100.0%) |
| ORR X14, XZR, XZR | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | N/A |
| FADD Z0.D, Z1.D, Z0.D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 0.50 | vect (100.0%) |
| AND X14, X23, #0x7fffffff | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | N/A |
| ORR X15, XZR, X18 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | N/A |
| CMP X14, X18 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 | scal (25.0%) |
| FADDV D0, P0, Z0.D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.75 | 0.75 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 9 | 2 | vect (100.0%) |
| B.EQ 12880 <main+0x18c0> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | N/A |
| B 128c8 <main+0x1908> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | N/A |
