OV - attention-armclang-native - Loop 42 - attention-armclang-native

	Loop Id: 42	Module: attention-armclang-native	Source: attention_v2.cpp:55-56	Coverage: 0.10%

0x12d8c LD1B	{Z0.B}, P0/Z, [X15, X26]    [5]

0x12d90 ADD	X8, X15, X26

0x12d94 ORR	P0.B, P4/Z, P4.B, P4.B

0x12d98 LDR	Z1, [X8, #1, MUL VL]    [4]

0x12d9c FSUB	Z0.S, Z0.S, Z19.S

0x12da0 FSUB	Z16.S, Z1.S, Z19.S

0x12da4 BL	10190

0x12da8 ORR	Z17.D, Z0.D, Z0.D

0x12dac ORR	Z0.D, Z16.D, Z16.D

0x12db0 ORR	P0.B, P4/Z, P4.B, P4.B

0x12db4 BL	10190

0x12db8 FDIV	Z0.S, P4/M, Z0.S, Z18.S

0x12dbc LDR	X9, [SP, #512]    [1]

0x12dc0 LDR	X15, [SP, #592]    [1]

0x12dc4 PTRUE	P0.B, ALL

0x12dc8 ADD	X8, X9, X26

0x12dcc STR	Z0, [X8, #1, MUL VL]    [3]

0x12dd0 FDIV	Z17.S, P4/M, Z17.S, Z18.S

0x12dd4 CNTH	X8, ALL

0x12dd8 ST1B	{Z17.B}, P0, [X9, X26]    [2]

0x12ddc ADDS	X28, X28, X8

0x12de0 RDVL	X8, #2

0x12de4 ADD	X26, X26, X8

0x12de8 B.NE	12d8c

/home/eoseret/llm-attention/attention_v2.cpp: 55 - 56

--------------------------------------------------------------------------------

55:       for (int idx = 0; idx <= row; ++idx)  //vectorised

56:          P[row * N + idx] = expf(S_row[idx] - max_val) / sum;

Coverage (%)	Name	Module
►100.00+	__libc_start_call_main	libc.so.6
○	__libc_start_main	libc.so.6
○	_start	attention-armclang-native

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	2.80 - 3.60
Bottlenecks	P6, P8,
Function	main
Source	attention_v2.cpp:55-56
Source loop unroll info	unrolled by 16
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	16
CQA cycles	13.99 - 18.02
CQA cycles if no scalar integer	13.99 - 18.02
CQA cycles if FP arith vectorized	13.99 - 18.02
CQA cycles if fully vectorized	13.99 - 18.02
Front-end cycles	3.00
P0 cycles	1.50
P1 cycles	1.50
P2 cycles	2.00
P3 cycles	2.00
P4 cycles	5.00
P5 cycles	2.00
P6 cycles	3.00
P7 cycles	3.00
P8 cycles	1.00
P9 cycles	1.00
P10 cycles	2.00
P11 cycles	2.00
P12 cycles	2.00
P13 cycles	0.00
P14 cycles	0.00
DIV/SQRT cycles	13.99 - 18.02
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	24.00
Nb uops	24.00
Nb loads	NA
Nb stores	2.00
Nb stack references	2.00
FLOP/cycle	2.29 - 1.78
Nb FLOP add-sub	16.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	16.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	7.10 - 9.15
Bytes prefetched	0.00
Bytes loaded	64.00
Bytes stored	64.00
Stride 0	1.00
Stride 1	0.00
Stride n	0.00
Stride unknown	2.00
Stride indirect	2.00
Vectorization ratio all	85.71
Vectorization ratio load	100.00
Vectorization ratio store	100.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	66.67
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	100.00
Vectorization ratio other	80.00
Vector-efficiency ratio all	82.14
Vector-efficiency ratio load	100.00
Vector-efficiency ratio store	100.00
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	75.00
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	100.00
Vector-efficiency ratio other	65.00

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	2.80 - 3.60
Bottlenecks	P6, P8,
Function	main
Source	attention_v2.cpp:55-56
Source loop unroll info	unrolled by 16
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	16
CQA cycles	13.99 - 18.02
CQA cycles if no scalar integer	13.99 - 18.02
CQA cycles if FP arith vectorized	13.99 - 18.02
CQA cycles if fully vectorized	13.99 - 18.02
Front-end cycles	3.00
P0 cycles	1.50
P1 cycles	1.50
P2 cycles	2.00
P3 cycles	2.00
P4 cycles	5.00
P5 cycles	2.00
P6 cycles	3.00
P7 cycles	3.00
P8 cycles	1.00
P9 cycles	1.00
P10 cycles	2.00
P11 cycles	2.00
P12 cycles	2.00
P13 cycles	0.00
P14 cycles	0.00
DIV/SQRT cycles	13.99 - 18.02
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	24.00
Nb uops	24.00
Nb loads	NA
Nb stores	2.00
Nb stack references	2.00
FLOP/cycle	2.29 - 1.78
Nb FLOP add-sub	16.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	16.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	7.10 - 9.15
Bytes prefetched	0.00
Bytes loaded	64.00
Bytes stored	64.00
Stride 0	1.00
Stride 1	0.00
Stride n	0.00
Stride unknown	2.00
Stride indirect	2.00
Vectorization ratio all	85.71
Vectorization ratio load	100.00
Vectorization ratio store	100.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	66.67
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	100.00
Vectorization ratio other	80.00
Vector-efficiency ratio all	82.14
Vector-efficiency ratio load	100.00
Vector-efficiency ratio store	100.00
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	75.00
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	100.00
Vector-efficiency ratio other	65.00

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	main
Source file and lines	attention_v2.cpp:55-56
Module	attention-armclang-native

The loop is defined in /home/eoseret/llm-attention/attention_v2.cpp:55-56.

The related source loop is unrolled by 16 (including vectorization).

gain
potential
hint
expert

Vectorization

Your loop is partially vectorized. 82% of vector register length is used (average across all VPU instructions).

Details

85% of VPU instructions are used in vector version (process two or more data elements in vector registers):

66% of VPU addition or subtraction instructions are used in vector version.
80% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 18.02 to 5.00 cycles (3.60x speedup).

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

unknown: 2 occurrences►
- /home/eoseret/llm-attention/attention_v2.cpp:56
- /home/eoseret/llm-attention/attention_v2.cpp:56

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant unknown stride: 2 occurrence(s)
Irregular (variable stride) or indirect: 2 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)
Try to remove indirect accesses. If applicable, precompute elements out of the innermost loop.

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 32 FP arithmetical operations:

16: addition or subtraction
16: divide

The binary loop is loading 64 bytes. The binary loop is storing 64 bytes.

Arithmetic intensity

Arithmetic intensity is 0.25 FP operations per loaded or stored byte.

General properties

nb instructions	24
nb uops	24
loop length	96
used w registers	0
used x registers	5
used b registers	0
used h registers	0
used s registers	1
used d registers	0
used q registers	0
used v registers	0
used z registers	6
nb stack references	2

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	3.00 cycles
front end	3.00 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	1.50	1.50	2.00	2.00	5.00	2.00	3.00	3.00	1.00	1.00	2.00	2.00	2.00	0.00	0.00
cycles	1.50	1.50	2.00	2.00	5.00	2.00	3.00	3.00	1.00	1.00	2.00	2.00	2.00	0.00	0.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions	13.99-18.02
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	3.00
Dispatch	5.00
DIV/SQRT	13.99-18.02
Data deps.	1.00
Overall L1	13.99-18.02

Vectorization ratios

INT

all	80%
load	100%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	80%

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	100%
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	85%
load	100%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	66%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	100%
other	80%

Vector efficiency ratios

INT

all	75%
load	100%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	25%
fma	NA (no fma vectorizable/vectorized instructions)
other	65%

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	100%
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	82%
load	100%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	75%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	100%
other	65%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 18.02 cycles. At this rate:

3% of peak load performance is reached (3.55 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
7% of peak store performance is reached (3.55 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 12d8c

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	Latency	Recip. throughput	Vectorization
LD1B {Z0.B}, P0/Z, [X15, X26]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50	vect (100.0%)
ADD X8, X15, X26	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
ORR P0.B, P4/Z, P4.B, P4.B	1	0	0	0	0	1	0	0	0	0	0	0	0	0	1	1	vect (12.5%)
LDR Z1, [X8, #1, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50	vect (100.0%)
FSUB Z0.S, Z0.S, Z19.S	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
FSUB Z16.S, Z1.S, Z19.S	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
BL 10190 <@plt_start@+0x170>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR Z17.D, Z0.D, Z0.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
ORR Z0.D, Z16.D, Z16.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
ORR P0.B, P4/Z, P4.B, P4.B	1	0	0	0	0	1	0	0	0	0	0	0	0	0	1	1	vect (12.5%)
BL 10190 <@plt_start@+0x170>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
FDIV Z0.S, P4/M, Z0.S, Z18.S	1	0	0	0	0	0	0	1	0	0	0	0	0	0	7-10	6.99-9.01	vect (100.0%)
LDR X9, [SP, #512]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
LDR X15, [SP, #592]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
PTRUE P0.B, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (100.0%)
ADD X8, X9, X26	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
STR Z0, [X8, #1, MUL VL]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	2	0.50	vect (100.0%)
FDIV Z17.S, P4/M, Z17.S, Z18.S	1	0	0	0	0	0	0	1	0	0	0	0	0	0	7-10	6.99-9.01	vect (100.0%)
CNTH X8, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	N/A
ST1B {Z17.B}, P0, [X9, X26]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	2	0.50	vect (100.0%)
ADDS X28, X28, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
RDVL X8, #2	1	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	N/A
ADD X26, X26, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
B.NE 12d8c <main+0x1dcc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Function	main
Source file and lines	attention_v2.cpp:55-56
Module	attention-armclang-native

The loop is defined in /home/eoseret/llm-attention/attention_v2.cpp:55-56.

The related source loop is unrolled by 16 (including vectorization).

gain
potential
hint
expert

Vectorization

Your loop is partially vectorized. 82% of vector register length is used (average across all VPU instructions).

Details

85% of VPU instructions are used in vector version (process two or more data elements in vector registers):

66% of VPU addition or subtraction instructions are used in vector version.
80% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 18.02 to 5.00 cycles (3.60x speedup).

CALL instructions

Detected function call instructions.

Details

unknown: 2 occurrences►
- /home/eoseret/llm-attention/attention_v2.cpp:56
- /home/eoseret/llm-attention/attention_v2.cpp:56

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant unknown stride: 2 occurrence(s)
Irregular (variable stride) or indirect: 2 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)
Try to remove indirect accesses. If applicable, precompute elements out of the innermost loop.

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 32 FP arithmetical operations:

16: addition or subtraction
16: divide

The binary loop is loading 64 bytes. The binary loop is storing 64 bytes.

Arithmetic intensity

Arithmetic intensity is 0.25 FP operations per loaded or stored byte.

General properties

nb instructions	24
nb uops	24
loop length	96
used w registers	0
used x registers	5
used b registers	0
used h registers	0
used s registers	1
used d registers	0
used q registers	0
used v registers	0
used z registers	6
nb stack references	2

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	3.00 cycles
front end	3.00 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	1.50	1.50	2.00	2.00	5.00	2.00	3.00	3.00	1.00	1.00	2.00	2.00	2.00	0.00	0.00
cycles	1.50	1.50	2.00	2.00	5.00	2.00	3.00	3.00	1.00	1.00	2.00	2.00	2.00	0.00	0.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions	13.99-18.02
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	3.00
Dispatch	5.00
DIV/SQRT	13.99-18.02
Data deps.	1.00
Overall L1	13.99-18.02

Vectorization ratios

INT

all	80%
load	100%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	80%

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	100%
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	85%
load	100%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	66%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	100%
other	80%

Vector efficiency ratios

INT

all	75%
load	100%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	25%
fma	NA (no fma vectorizable/vectorized instructions)
other	65%

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	100%
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	82%
load	100%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	75%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	100%
other	65%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 18.02 cycles. At this rate:

3% of peak load performance is reached (3.55 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
7% of peak store performance is reached (3.55 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 12d8c

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	Latency	Recip. throughput	Vectorization
LD1B {Z0.B}, P0/Z, [X15, X26]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50	vect (100.0%)
ADD X8, X15, X26	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
ORR P0.B, P4/Z, P4.B, P4.B	1	0	0	0	0	1	0	0	0	0	0	0	0	0	1	1	vect (12.5%)
LDR Z1, [X8, #1, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50	vect (100.0%)
FSUB Z0.S, Z0.S, Z19.S	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
FSUB Z16.S, Z1.S, Z19.S	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
BL 10190 <@plt_start@+0x170>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR Z17.D, Z0.D, Z0.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
ORR Z0.D, Z16.D, Z16.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
ORR P0.B, P4/Z, P4.B, P4.B	1	0	0	0	0	1	0	0	0	0	0	0	0	0	1	1	vect (12.5%)
BL 10190 <@plt_start@+0x170>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
FDIV Z0.S, P4/M, Z0.S, Z18.S	1	0	0	0	0	0	0	1	0	0	0	0	0	0	7-10	6.99-9.01	vect (100.0%)
LDR X9, [SP, #512]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
LDR X15, [SP, #592]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
PTRUE P0.B, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (100.0%)
ADD X8, X9, X26	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
STR Z0, [X8, #1, MUL VL]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	2	0.50	vect (100.0%)
FDIV Z17.S, P4/M, Z17.S, Z18.S	1	0	0	0	0	0	0	1	0	0	0	0	0	0	7-10	6.99-9.01	vect (100.0%)
CNTH X8, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	N/A
ST1B {Z17.B}, P0, [X9, X26]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	2	0.50	vect (100.0%)
ADDS X28, X28, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
RDVL X8, #2	1	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	N/A
ADD X26, X26, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
B.NE 12d8c <main+0x1dcc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Report Configuration

Vectorization

Details

Expensive FP math instructions/calls

CALL instructions

Details

Slow data structures access

Details

Workaround

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Expensive FP math instructions/calls

CALL instructions

Details

Slow data structures access

Details

Workaround

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code