OV - attention-armclang-native - Loop 41 - attention-armclang-native

	Loop Id: 41	Module: attention-armclang-native	Source: attention_v2.cpp:43-273 [...]	Coverage: 0.15%

0x12a60 LDR	X8, [SP, #424]

0x12a64 LDR	X9, [SP, #512]

0x12a68 STR	X26, [SP, #448]

0x12a6c ADD	X16, X16, #1

0x12a70 STR	S20, [X8, X27,LSL #2]

0x12a74 LDP	X8, X14, [SP, #456]

0x12a78 ADD	X15, X15, X8

0x12a7c ADD	X9, X9, X8

0x12a80 ADDVL	X8, SP, #3

0x12a84 SUB	X14, X14, #1

0x12a88 STR	X9, [SP, #512]

0x12a8c LDR	X8, [X8, #10632]

0x12a90 CMP	X26, X8

0x12a94 LDP	X26, X27, [SP, #408]

0x12a98 B.EQ	12f00

0x12a9c AND	X17, X16, #0x0

0x12aa0 CMP	X16, #4

0x12aa4 B.CS	12ac0

0x12aa8 MOVN	W9, #128

0x12aac LDR	X26, [SP, #512]

0x12ab0 CNTH	X12, ALL

0x12ab4 ORR	X8, XZR, XZR

0x12ab8 FMOV	S21, W9

0x12abc B	12b60

0x12ac0 LDR	X26, [SP, #512]

0x12ac4 CNTH	X12, ALL

0x12ac8 CMP	X16, X12

0x12acc PTRUE	P0.S, ALL

0x12ad0 RDVL	X13, #2

0x12ad4 B.CS	12ae8

0x12ad8 MOVN	W9, #128

0x12adc ORR	X8, XZR, XZR

0x12ae0 FMOV	S21, W9

0x12ae4 B	12b34

0x12ae8 LDR	X8, [SP, #376]

0x12aec DUPM	Z0.S, #0xff7fffff

0x12af0 DUPM	Z1.S, #0xff7fffff

0x12af4 ORR	X11, XZR, X15

0x12af8 AND	X9, X16, X8

0x12afc SUB	X8, X16, X9

0x12b00 ADD	X10, X9, X14

  (32) 0x12b04 LDR	Z2, [X11, MUL VL]

  (32) 0x12b08 LDR	Z3, [X11, #1, MUL VL]

  (32) 0x12b0c ADDS	X10, X10, X12

  (32) 0x12b10 ADD	X11, X11, X13

  (32) 0x12b14 FMAXNM	Z0.S, P0/M, Z0.S, Z2.S

  (32) 0x12b18 FMAXNM	Z1.S, P0/M, Z1.S, Z3.S

  (32) 0x12b1c B.NE	12b04

0x12b20 FMAXNM	Z0.S, P0/M, Z0.S, Z1.S

0x12b24 FMAXNMV	S21, P0, Z0.S

0x12b28 CBZ	X9, 12b74

0x12b2c CMP	X9, #4

0x12b30 B.CC	12b60

0x12b34 DUP	V0.4S, V21.S[0]

0x12b38 SUB	X9, X8, X17

0x12b3c UBFM	X10, X8, #62, #61

0x12b40 AND	X8, X16, #0x0

  (47) 0x12b44 LDR	Q1, [X15, X10]

  (47) 0x12b48 ADDS	X9, X9, #4

  (47) 0x12b4c ADD	X10, X10, #16

  (47) 0x12b50 FMAXNM	V0.4S, V1.4S, V0.4S

  (47) 0x12b54 B.NE	12b44

0x12b58 FMAXNMV	S21, V0.4S

0x12b5c B	12b6c

  (46) 0x12b60 LDR	S0, [X15, X8,LSL #2]

  (46) 0x12b64 ADD	X8, X8, #1

  (46) 0x12b68 FMAXNM	S21, S0, S21

  (46) 0x12b6c CMP	X16, X8

  (46) 0x12b70 B.NE	12b60

0x12b74 CMP	X16, #4

0x12b78 SUB	X8, X29, #32

0x12b7c STR	X15, [SP, #592]

0x12b80 STR	X16, [SP, #576]

0x12b84 STR	Z21, [X8, #509, MUL VL]

0x12b88 STR	X14, [SP, #464]

0x12b8c STR	X17, [SP, #440]

0x12b90 B.CS	12ba0

0x12b94 MOVI	D20, #0

0x12b98 ORR	X27, XZR, XZR

0x12b9c B	12cc4

0x12ba0 CMP	X16, X12

0x12ba4 B.CS	12bc0

0x12ba8 ORR	X27, XZR, XZR

0x12bac MOVI	D20, #0

0x12bb0 B	12c54

0x12bc0 LDR	X8, [SP, #376]

0x12bc4 DUP	Z18.S, Z21.S[0]

0x12bc8 MOVI	V19.2D, #0

0x12bcc MOVI	V20.2D, #0

0x12bd0 ORR	X28, XZR, X15

0x12bd4 AND	X8, X16, X8

0x12bd8 SUB	X27, X16, X8

0x12bdc ADD	X26, X8, X14

0x12be0 STR	X8, [SP, #312]

  (33) 0x12be4 LDR	Z0, [X28, MUL VL]

  (33) 0x12be8 LDR	Z1, [X28, #1, MUL VL]

  (33) 0x12bec PTRUE	P0.S, ALL

  (33) 0x12bf0 FSUB	Z0.S, Z0.S, Z18.S

  (33) 0x12bf4 FSUB	Z16.S, Z1.S, Z18.S

  (33) 0x12bf8 BL	10190

  (33) 0x12bfc ORR	Z17.D, Z0.D, Z0.D

  (33) 0x12c00 ORR	Z0.D, Z16.D, Z16.D

  (33) 0x12c04 PTRUE	P0.S, ALL

  (33) 0x12c08 BL	10190

  (33) 0x12c0c CNTH	X8, ALL

  (33) 0x12c10 FADD	Z19.S, Z17.S, Z19.S

  (33) 0x12c14 FADD	Z20.S, Z0.S, Z20.S

  (33) 0x12c18 ADDS	X26, X26, X8

  (33) 0x12c1c RDVL	X8, #2

  (33) 0x12c20 PTRUE	P0.S, ALL

  (33) 0x12c24 ADD	X28, X28, X8

  (33) 0x12c28 B.NE	12be4

0x12c2c FADD	Z0.S, Z20.S, Z19.S

0x12c30 LDR	X26, [SP, #512]

0x12c34 LDR	X8, [SP, #312]

0x12c38 FADDV	S20, P0, Z0.S

0x12c3c CBZ	X8, 12d14

0x12c40 LDR	X28, [SP, #432]

0x12c44 LDR	X15, [SP, #592]

0x12c48 LDR	X16, [SP, #576]

0x12c4c CMP	X8, #4

0x12c50 B.CC	12cc4

0x12c54 LDR	X8, [SP, #440]

0x12c58 MOVI	V16.2D, #0

0x12c5c DUP	V17.4S, V21.S[0]

0x12c60 UBFM	X28, X27, #62, #61

0x12c64 MOV	V16.S[0], V20.S[0]

0x12c68 SUB	X26, X27, X8

0x12c6c AND	X27, X16, #0x0

0x12c70 HINT	#0

0x12c74 HINT	#0

0x12c78 HINT	#0

0x12c7c HINT	#0

  (45) 0x12c80 LDR	Q0, [X15, X28]

  (45) 0x12c84 FSUB	V0.4S, V0.4S, V17.4S

  (45) 0x12c88 BL	10040

  (45) 0x12c8c LDR	X15, [SP, #592]

  (45) 0x12c90 FADD	V16.4S, V0.4S, V16.4S

  (45) 0x12c94 ADDS	X26, X26, #4

  (45) 0x12c98 ADD	X28, X28, #16

  (45) 0x12c9c B.NE	12c80

0x12ca0 SUB	X8, X29, #32

0x12ca4 LDR	X16, [SP, #576]

0x12ca8 FADDP	V0.4S, V16.4S, V16.4S

0x12cac LDR	X28, [SP, #432]

0x12cb0 LDR	X26, [SP, #512]

0x12cb4 FADDP	S20, V0.2S

0x12cb8 LDR	Z21, [X8, #509, MUL VL]

0x12cbc CMP	X16, X27

0x12cc0 B.EQ	12cfc

  (44) 0x12cc4 LDR	S0, [X15, X27,LSL #2]

  (44) 0x12cc8 SUB	X8, X29, #32

  (44) 0x12ccc STR	Z20, [X8, #510, MUL VL]

  (44) 0x12cd0 FSUB	S0, S0, S21

  (44) 0x12cd4 BL	101d0

  (44) 0x12cd8 SUB	X8, X29, #32

  (44) 0x12cdc LDR	X16, [SP, #576]

  (44) 0x12ce0 LDR	X15, [SP, #592]

  (44) 0x12ce4 ADD	X27, X27, #1

  (44) 0x12ce8 LDR	Z20, [X8, #510, MUL VL]

  (44) 0x12cec LDR	Z21, [X8, #509, MUL VL]

  (44) 0x12cf0 CMP	X16, X27

  (44) 0x12cf4 FADD	S20, S0, S20

  (44) 0x12cf8 B.NE	12cc4

0x12cfc CMP	X16, #4

0x12d00 SUB	X8, X29, #32

0x12d04 STR	Z20, [X8, #510, MUL VL]

0x12d08 B.CS	12d40

0x12d0c ORR	X27, XZR, XZR

0x12d10 B	12e68

0x12d14 LDR	X28, [SP, #432]

0x12d18 LDR	X15, [SP, #592]

0x12d1c LDR	X16, [SP, #576]

0x12d20 CMP	X16, #4

0x12d24 SUB	X8, X29, #32

0x12d28 STR	Z20, [X8, #510, MUL VL]

0x12d2c B.CC	12d0c

0x12d30 HINT	#0

0x12d34 HINT	#0

0x12d38 HINT	#0

0x12d3c HINT	#0

0x12d40 CNTH	X8, ALL

0x12d44 STR	X26, [SP, #512]

0x12d48 CMP	X16, X8

0x12d4c B.CS	12d60

0x12d50 ORR	X27, XZR, XZR

0x12d54 B	12e08

0x12d60 LDR	X8, [SP, #376]

0x12d64 DUP	Z18.S, Z20.S[0]

0x12d68 DUP	Z19.S, Z21.S[0]

0x12d6c PTRUE	P0.B, ALL

0x12d70 PTRUE	P4.S, ALL

0x12d74 ORR	X26, XZR, XZR

0x12d78 AND	X9, X16, X8

0x12d7c LDR	X8, [SP, #464]

0x12d80 SUB	X27, X16, X9

0x12d84 STR	X9, [SP, #312]

0x12d88 ADD	X28, X9, X8

  (42) 0x12d8c LD1B	{Z0.B}, P0/Z, [X15, X26]

  (42) 0x12d90 ADD	X8, X15, X26

  (42) 0x12d94 ORR	P0.B, P4/Z, P4.B, P4.B

  (42) 0x12d98 LDR	Z1, [X8, #1, MUL VL]

  (42) 0x12d9c FSUB	Z0.S, Z0.S, Z19.S

  (42) 0x12da0 FSUB	Z16.S, Z1.S, Z19.S

  (42) 0x12da4 BL	10190

  (42) 0x12da8 ORR	Z17.D, Z0.D, Z0.D

  (42) 0x12dac ORR	Z0.D, Z16.D, Z16.D

  (42) 0x12db0 ORR	P0.B, P4/Z, P4.B, P4.B

  (42) 0x12db4 BL	10190

  (42) 0x12db8 FDIV	Z0.S, P4/M, Z0.S, Z18.S

  (42) 0x12dbc LDR	X9, [SP, #512]

  (42) 0x12dc0 LDR	X15, [SP, #592]

  (42) 0x12dc4 PTRUE	P0.B, ALL

  (42) 0x12dc8 ADD	X8, X9, X26

  (42) 0x12dcc STR	Z0, [X8, #1, MUL VL]

  (42) 0x12dd0 FDIV	Z17.S, P4/M, Z17.S, Z18.S

  (42) 0x12dd4 CNTH	X8, ALL

  (42) 0x12dd8 ST1B	{Z17.B}, P0, [X9, X26]

  (42) 0x12ddc ADDS	X28, X28, X8

  (42) 0x12de0 RDVL	X8, #2

  (42) 0x12de4 ADD	X26, X26, X8

  (42) 0x12de8 B.NE	12d8c

0x12dec LDR	X28, [SP, #432]

0x12df0 LDR	X26, [SP, #512]

0x12df4 LDR	X16, [SP, #576]

0x12df8 LDR	X8, [SP, #312]

0x12dfc CBZ	X8, 12e9c

0x12e00 CMP	X8, #4

0x12e04 B.CC	12e68

0x12e08 LDR	X8, [SP, #440]

0x12e0c DUP	V16.4S, V20.S[0]

0x12e10 DUP	V17.4S, V21.S[0]

0x12e14 UBFM	X28, X27, #62, #61

0x12e18 SUB	X26, X27, X8

0x12e1c AND	X27, X16, #0x0

  (43) 0x12e20 LDR	Q0, [X15, X28]

  (43) 0x12e24 FSUB	V0.4S, V0.4S, V17.4S

  (43) 0x12e28 BL	10040

  (43) 0x12e2c FDIV	V0.4S, V0.4S, V16.4S

  (43) 0x12e30 LDR	X8, [SP, #512]

  (43) 0x12e34 LDR	X15, [SP, #592]

  (43) 0x12e38 ADDS	X26, X26, #4

  (43) 0x12e3c STR	Q0, [X8, X28]

  (43) 0x12e40 ADD	X28, X28, #16

  (43) 0x12e44 B.NE	12e20

0x12e48 SUB	X8, X29, #32

0x12e4c LDR	X16, [SP, #576]

0x12e50 LDR	X28, [SP, #432]

0x12e54 LDR	X26, [SP, #512]

0x12e58 CMP	X16, X27

0x12e5c LDR	Z21, [X8, #509, MUL VL]

0x12e60 LDR	Z20, [X8, #510, MUL VL]

0x12e64 B.EQ	12e9c

  (34) 0x12e68 LDR	S0, [X15, X27,LSL #2]

  (34) 0x12e6c FSUB	S0, S0, S21

  (34) 0x12e70 BL	101d0

  (34) 0x12e74 SUB	X8, X29, #32

  (34) 0x12e78 LDR	X16, [SP, #576]

  (34) 0x12e7c LDR	X15, [SP, #592]

  (34) 0x12e80 LDR	Z20, [X8, #510, MUL VL]

  (34) 0x12e84 LDR	Z21, [X8, #509, MUL VL]

  (34) 0x12e88 FDIV	S0, S0, S20

  (34) 0x12e8c STR	S0, [X26, X27,LSL #2]

  (34) 0x12e90 ADD	X27, X27, #1

  (34) 0x12e94 CMP	X16, X27

  (34) 0x12e98 B.NE	12e68

0x12e9c ADDVL	X8, SP, #3

0x12ea0 LDR	X27, [SP, #448]

0x12ea4 LDR	X8, [X8, #10632]

0x12ea8 ADD	X26, X27, #1

0x12eac CMP	X26, X8

0x12eb0 B.CS	12a60

0x12eb4 LDP	X9, X8, [SP, #328]

0x12eb8 MOVZ	X10, #4

0x12ebc ORR	W1, WZR, WZR

0x12ec0 MADD	X9, X9, X27, X10

0x12ec4 SUB	W8, W8, W27

0x12ec8 UBFM	X8, X8, #62, #31

0x12ecc AND	X9, X9, #0x0

0x12ed0 ADD	X2, X8, #4

0x12ed4 ADD	X0, X22, X9

0x12ed8 BL	100c0

0x12edc SUB	X8, X29, #32

0x12ee0 LDR	X16, [SP, #576]

0x12ee4 LDR	X15, [SP, #592]

0x12ee8 LDR	Z20, [X8, #510, MUL VL]

0x12eec B	12a60

/home/eoseret/llm-attention/attention_v2.cpp: 43 - 273

--------------------------------------------------------------------------------

43:    for (int row = 0; row < N; ++row) {

44:       const float *S_row = &S[row * N];

45:

46:       float max_val = -FLT_MAX;

47:       for (int idx = 0; idx <= row; ++idx) // vectorised

48:          if (S_row[idx] > max_val) max_val = S_row[idx];

49:

50:       float sum = 0.0f;

51: #pragma clang loop vectorize(enable)

52:       for (int idx = 0; idx <= row; ++idx) // vectorised

53:          sum += expf(S_row[idx] - max_val);

54:

55:       for (int idx = 0; idx <= row; ++idx)  //vectorised

56:          P[row * N + idx] = expf(S_row[idx] - max_val) / sum;

57:

58:       for (int idx = row + 1; idx < N; ++idx)

59:          P[row * N + idx] = 0.0f;

60:

61:       D[row] = sum;

[...]

273:       start = std::chrono::steady_clock::now();

Coverage (%)	Name	Module
►100.00+	__libc_start_call_main	libc.so.6
○	__libc_start_main	libc.so.6
○	_start	attention-armclang-native

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	2.87
CQA speedup if FP arith vectorized	1.01
CQA speedup if fully vectorized	1.47
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.20
Bottlenecks	micro-operation queue,
Function	main
Source	attention_v2.cpp:43-44,attention_v2.cpp:47-47,attention_v2.cpp:52-52,attention_v2.cpp:55-55,attention_v2.cpp:58-61,attention_v2.cpp:273-273
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	21.88
CQA cycles if no scalar integer	7.63
CQA cycles if FP arith vectorized	21.73
CQA cycles if fully vectorized	14.85
Front-end cycles	21.88
P0 cycles	13.00
P1 cycles	13.00
P2 cycles	18.25
P3 cycles	18.25
P4 cycles	18.25
P5 cycles	18.25
P6 cycles	7.50
P7 cycles	7.50
P8 cycles	7.50
P9 cycles	7.50
P10 cycles	17.83
P11 cycles	17.50
P12 cycles	17.67
P13 cycles	4.50
P14 cycles	4.50
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	183.00
Nb uops	175.00
Nb loads	NA
Nb stores	13.00
Nb stack references	43.00
FLOP/cycle	0.96
Nb FLOP add-sub	21.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	10.38
Bytes prefetched	0.00
Bytes loaded	128.00
Bytes stored	99.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	20.00
Vectorization ratio load	16.00
Vectorization ratio store	23.08
Vectorization ratio mul	NA
Vectorization ratio add_sub	17.65
Vectorization ratio fma	0.00
Vectorization ratio div_sqrt	NA
Vectorization ratio other	22.22
Vector-efficiency ratio all	38.52
Vector-efficiency ratio load	37.00
Vector-efficiency ratio store	41.35
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	35.29
Vector-efficiency ratio fma	25.00
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	39.81

Metric	Value
CQA speedup if no scalar integer	2.87
CQA speedup if FP arith vectorized	1.01
CQA speedup if fully vectorized	1.47
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.20
Bottlenecks	micro-operation queue,
Function	main
Source	attention_v2.cpp:43-44,attention_v2.cpp:47-47,attention_v2.cpp:52-52,attention_v2.cpp:55-55,attention_v2.cpp:58-61,attention_v2.cpp:273-273
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	21.88
CQA cycles if no scalar integer	7.63
CQA cycles if FP arith vectorized	21.73
CQA cycles if fully vectorized	14.85
Front-end cycles	21.88
P0 cycles	13.00
P1 cycles	13.00
P2 cycles	18.25
P3 cycles	18.25
P4 cycles	18.25
P5 cycles	18.25
P6 cycles	7.50
P7 cycles	7.50
P8 cycles	7.50
P9 cycles	7.50
P10 cycles	17.83
P11 cycles	17.50
P12 cycles	17.67
P13 cycles	4.50
P14 cycles	4.50
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	183.00
Nb uops	175.00
Nb loads	NA
Nb stores	13.00
Nb stack references	43.00
FLOP/cycle	0.96
Nb FLOP add-sub	21.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	10.38
Bytes prefetched	0.00
Bytes loaded	128.00
Bytes stored	99.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	20.00
Vectorization ratio load	16.00
Vectorization ratio store	23.08
Vectorization ratio mul	NA
Vectorization ratio add_sub	17.65
Vectorization ratio fma	0.00
Vectorization ratio div_sqrt	NA
Vectorization ratio other	22.22
Vector-efficiency ratio all	38.52
Vector-efficiency ratio load	37.00
Vector-efficiency ratio store	41.35
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	35.29
Vector-efficiency ratio fma	25.00
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	39.81

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	main
Source file and lines	attention_v2.cpp:43-273
Module	attention-armclang-native

The loop is defined in /home/eoseret/llm-attention/attention_v2.cpp:43-61,273.

Analyzed code is defined in /home/eoseret/llm-attention/attention_v2.cpp:43-44,47,52,55,58-61,273.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Failed to get the number of paths
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 21.88 to 7.63 cycles (2.87x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is poorly vectorized. Only 38% of vector register length is used (average across all VPU instructions). By fully vectorizing your loop, you can lower the cost of an iteration from 21.88 to 14.85 cycles (1.47x speedup).

Details

20% of VPU instructions are used in vector version (process two or more data elements in vector registers):

16% of VPU loads are used in vector version.
23% of VPU stores are used in vector version.
17% of VPU addition or subtraction instructions are used in vector version.
0% of VPU fused multiply-add instructions are used in vector version.
22% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ffast-math (included in Ofast) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

unknown: 1 occurrences►
- /home/eoseret/llm-attention/attention_v2.cpp:59

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 21 FP arithmetical operations:

21: addition or subtraction

The binary loop is loading 128 bytes. The binary loop is storing 99 bytes.

Arithmetic intensity

Arithmetic intensity is 0.09 FP operations per loaded or stored byte.

General properties

nb instructions	183
nb uops	175
loop length	732
used w registers	5
used x registers	18
used b registers	0
used h registers	0
used s registers	3
used d registers	1
used q registers	0
used v registers	6
used z registers	6
nb stack references	43

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	21.88 cycles
front end	21.88 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	13.00	13.00	18.25	18.25	18.25	18.25	7.50	7.50	7.50	7.50	17.83	17.50	17.67	4.50	4.50
cycles	13.00	13.00	18.25	18.25	18.25	18.25	7.50	7.50	7.50	7.50	17.83	17.50	17.67	4.50	4.50

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	21.88
Dispatch	18.25
Overall L1	21.88

Vectorization ratios

INT

all	15%
load	16%
store	23%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
other	18%

all	66%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	75%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	60%

INT+FP

all	20%
load	16%
store	23%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	17%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	22%

Vector efficiency ratios

INT

all	36%
load	37%
store	41%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	25%
fma	25%
other	38%

all	61%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	68%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	55%

INT+FP

all	38%
load	37%
store	41%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	35%
fma	25%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	39%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 21.88 cycles. At this rate:

6% of peak load performance is reached (5.85 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
9% of peak store performance is reached (4.53 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 21.88 to 18.25 cycles (1.20x speedup).

ASM code

In the binary file, the address of the loop is: 12a9c

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput	Vectorization
LDR X8, [SP, #424]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X9, [SP, #512]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
STR X26, [SP, #448]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ADD X16, X16, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
STR S20, [X8, X27,LSL #2]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (12.5%)
LDP X8, X14, [SP, #456]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
ADD X15, X15, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X9, X9, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADDVL X8, SP, #3	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
SUB X14, X14, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
STR X9, [SP, #512]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X8, [X8, #10632]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X26, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
LDP X26, X27, [SP, #408]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
B.EQ 12f00 <main+0x1f40>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
AND X17, X16, #0x0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
CMP X16, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.CS 12ac0 <main+0x1b00>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVN W9, #128	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
LDR X26, [SP, #512]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
CNTH X12, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
ORR X8, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
FMOV S21, W9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (12.5%)
B 12b60 <main+0x1ba0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X26, [SP, #512]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
CNTH X12, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
CMP X16, X12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
PTRUE P0.S, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (100.0%)
RDVL X13, #2	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
B.CS 12ae8 <main+0x1b28>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVN W9, #128	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
ORR X8, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
FMOV S21, W9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (12.5%)
B 12b34 <main+0x1b74>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X8, [SP, #376]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
DUPM Z0.S, #0xff7fffff	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	vect (100.0%)
DUPM Z1.S, #0xff7fffff	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	vect (100.0%)
ORR X11, XZR, X15	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
AND X9, X16, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
SUB X8, X16, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X10, X9, X14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
FMAXNM Z0.S, P0/M, Z0.S, Z1.S	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	vect (100.0%)
FMAXNMV S21, P0, Z0.S	1	0	0	0	0	0	0	0.75	0.75	0.25	0.25	0	0	0	0	0	11	2.50	vect (100.0%)
CBZ X9, 12b74 <main+0x1bb4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X9, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.CC 12b60 <main+0x1ba0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
DUP V0.4S, V21.S[0]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (50.0%)
SUB X9, X8, X17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
UBFM X10, X8, #62, #61	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
AND X8, X16, #0x0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
FMAXNMV S21, V0.4S	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.50	vect (50.0%)
B 12b6c <main+0x1bac>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X16, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
SUB X8, X29, #32	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR X15, [SP, #592]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X16, [SP, #576]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR Z21, [X8, #509, MUL VL]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
STR X14, [SP, #464]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X17, [SP, #440]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
B.CS 12ba0 <main+0x1be0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVI D20, #0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
ORR X27, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
B 12cc4 <main+0x1d04>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X16, X12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.CS 12bc0 <main+0x1c00>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X27, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVI D20, #0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
B 12c54 <main+0x1c94>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X8, [SP, #376]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
DUP Z18.S, Z21.S[0]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	vect (100.0%)
MOVI V19.2D, #0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
MOVI V20.2D, #0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
ORR X28, XZR, X15	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
AND X8, X16, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SUB X27, X16, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X26, X8, X14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
STR X8, [SP, #312]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
FADD Z0.S, Z20.S, Z19.S	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	vect (100.0%)
LDR X26, [SP, #512]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X8, [SP, #312]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
FADDV S20, P0, Z0.S	1	0	0	0	0	0	0	0.75	0.75	0.25	0.25	0	0	0	0	0	11	2.50	vect (100.0%)
CBZ X8, 12d14 <main+0x1d54>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X28, [SP, #432]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X15, [SP, #592]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X16, [SP, #576]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
CMP X8, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.CC 12cc4 <main+0x1d04>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X8, [SP, #440]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
MOVI V16.2D, #0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
DUP V17.4S, V21.S[0]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (50.0%)
UBFM X28, X27, #62, #61	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
MOV V16.S[0], V20.S[0]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (12.5%)
SUB X26, X27, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
AND X27, X16, #0x0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
SUB X8, X29, #32	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X16, [SP, #576]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
FADDP V0.4S, V16.4S, V16.4S	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (50.0%)
LDR X28, [SP, #432]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X26, [SP, #512]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
FADDP S20, V0.2S	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
LDR Z21, [X8, #509, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	6	0.50	vect (100.0%)
CMP X16, X27	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 12cfc <main+0x1d3c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X16, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
SUB X8, X29, #32	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR Z20, [X8, #510, MUL VL]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
B.CS 12d40 <main+0x1d80>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X27, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
B 12e68 <main+0x1ea8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X28, [SP, #432]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X15, [SP, #592]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X16, [SP, #576]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
CMP X16, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
SUB X8, X29, #32	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR Z20, [X8, #510, MUL VL]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
B.CC 12d0c <main+0x1d4c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
CNTH X8, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
STR X26, [SP, #512]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
CMP X16, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.CS 12d60 <main+0x1da0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X27, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
B 12e08 <main+0x1e48>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X8, [SP, #376]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
DUP Z18.S, Z20.S[0]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	vect (100.0%)
DUP Z19.S, Z21.S[0]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	vect (100.0%)
PTRUE P0.B, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (100.0%)
PTRUE P4.S, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (100.0%)
ORR X26, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
AND X9, X16, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
LDR X8, [SP, #464]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
SUB X27, X16, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR X9, [SP, #312]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ADD X28, X9, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
LDR X28, [SP, #432]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X26, [SP, #512]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X16, [SP, #576]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X8, [SP, #312]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CBZ X8, 12e9c <main+0x1edc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X8, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.CC 12e68 <main+0x1ea8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X8, [SP, #440]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
DUP V16.4S, V20.S[0]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (50.0%)
DUP V17.4S, V21.S[0]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (50.0%)
UBFM X28, X27, #62, #61	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
SUB X26, X27, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
AND X27, X16, #0x0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SUB X8, X29, #32	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X16, [SP, #576]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X28, [SP, #432]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X26, [SP, #512]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
CMP X16, X27	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
LDR Z21, [X8, #509, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	6	0.50	vect (100.0%)
LDR Z20, [X8, #510, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	6	0.50	vect (100.0%)
B.EQ 12e9c <main+0x1edc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADDVL X8, SP, #3	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
LDR X27, [SP, #448]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X8, [X8, #10632]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X26, X27, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
CMP X26, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.CS 12a60 <main+0x1aa0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X9, X8, [SP, #328]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
MOVZ X10, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ORR W1, WZR, WZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
MADD X9, X9, X27, X10	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
SUB W8, W8, W27	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
UBFM X8, X8, #62, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
AND X9, X9, #0x0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X2, X8, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X0, X22, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
BL 100c0 <@plt_start@+0xa0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB X8, X29, #32	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X16, [SP, #576]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X15, [SP, #592]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR Z20, [X8, #510, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	6	0.50	vect (100.0%)
B 12a60 <main+0x1aa0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Function	main
Source file and lines	attention_v2.cpp:43-273
Module	attention-armclang-native

The loop is defined in /home/eoseret/llm-attention/attention_v2.cpp:43-61,273.

Analyzed code is defined in /home/eoseret/llm-attention/attention_v2.cpp:43-44,47,52,55,58-61,273.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Failed to get the number of paths
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 21.88 to 7.63 cycles (2.87x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

20% of VPU instructions are used in vector version (process two or more data elements in vector registers):

16% of VPU loads are used in vector version.
23% of VPU stores are used in vector version.
17% of VPU addition or subtraction instructions are used in vector version.
0% of VPU fused multiply-add instructions are used in vector version.
22% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ffast-math (included in Ofast) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

CALL instructions

Detected function call instructions.

Details

unknown: 1 occurrences►
- /home/eoseret/llm-attention/attention_v2.cpp:59

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 21 FP arithmetical operations:

21: addition or subtraction

The binary loop is loading 128 bytes. The binary loop is storing 99 bytes.

Arithmetic intensity

Arithmetic intensity is 0.09 FP operations per loaded or stored byte.

General properties

nb instructions	183
nb uops	175
loop length	732
used w registers	5
used x registers	18
used b registers	0
used h registers	0
used s registers	3
used d registers	1
used q registers	0
used v registers	6
used z registers	6
nb stack references	43

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	21.88 cycles
front end	21.88 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	13.00	13.00	18.25	18.25	18.25	18.25	7.50	7.50	7.50	7.50	17.83	17.50	17.67	4.50	4.50
cycles	13.00	13.00	18.25	18.25	18.25	18.25	7.50	7.50	7.50	7.50	17.83	17.50	17.67	4.50	4.50

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	21.88
Dispatch	18.25
Overall L1	21.88

Vectorization ratios

INT

all	15%
load	16%
store	23%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
other	18%

all	66%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	75%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	60%

INT+FP

all	20%
load	16%
store	23%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	17%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	22%

Vector efficiency ratios

INT

all	36%
load	37%
store	41%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	25%
fma	25%
other	38%

all	61%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	68%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	55%

INT+FP

all	38%
load	37%
store	41%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	35%
fma	25%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	39%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 21.88 cycles. At this rate:

6% of peak load performance is reached (5.85 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
9% of peak store performance is reached (4.53 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the loop is: 12a9c

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput	Vectorization
LDR X8, [SP, #424]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X9, [SP, #512]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
STR X26, [SP, #448]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ADD X16, X16, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
STR S20, [X8, X27,LSL #2]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (12.5%)
LDP X8, X14, [SP, #456]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
ADD X15, X15, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X9, X9, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADDVL X8, SP, #3	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
SUB X14, X14, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
STR X9, [SP, #512]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X8, [X8, #10632]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X26, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
LDP X26, X27, [SP, #408]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
B.EQ 12f00 <main+0x1f40>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
AND X17, X16, #0x0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
CMP X16, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.CS 12ac0 <main+0x1b00>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVN W9, #128	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
LDR X26, [SP, #512]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
CNTH X12, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
ORR X8, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
FMOV S21, W9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (12.5%)
B 12b60 <main+0x1ba0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X26, [SP, #512]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
CNTH X12, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
CMP X16, X12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
PTRUE P0.S, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (100.0%)
RDVL X13, #2	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
B.CS 12ae8 <main+0x1b28>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVN W9, #128	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
ORR X8, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
FMOV S21, W9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (12.5%)
B 12b34 <main+0x1b74>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X8, [SP, #376]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
DUPM Z0.S, #0xff7fffff	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	vect (100.0%)
DUPM Z1.S, #0xff7fffff	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	vect (100.0%)
ORR X11, XZR, X15	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
AND X9, X16, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
SUB X8, X16, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X10, X9, X14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
FMAXNM Z0.S, P0/M, Z0.S, Z1.S	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	vect (100.0%)
FMAXNMV S21, P0, Z0.S	1	0	0	0	0	0	0	0.75	0.75	0.25	0.25	0	0	0	0	0	11	2.50	vect (100.0%)
CBZ X9, 12b74 <main+0x1bb4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X9, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.CC 12b60 <main+0x1ba0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
DUP V0.4S, V21.S[0]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (50.0%)
SUB X9, X8, X17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
UBFM X10, X8, #62, #61	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
AND X8, X16, #0x0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
FMAXNMV S21, V0.4S	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.50	vect (50.0%)
B 12b6c <main+0x1bac>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X16, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
SUB X8, X29, #32	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR X15, [SP, #592]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X16, [SP, #576]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR Z21, [X8, #509, MUL VL]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
STR X14, [SP, #464]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X17, [SP, #440]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
B.CS 12ba0 <main+0x1be0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVI D20, #0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
ORR X27, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
B 12cc4 <main+0x1d04>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X16, X12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.CS 12bc0 <main+0x1c00>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X27, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVI D20, #0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
B 12c54 <main+0x1c94>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X8, [SP, #376]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
DUP Z18.S, Z21.S[0]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	vect (100.0%)
MOVI V19.2D, #0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
MOVI V20.2D, #0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
ORR X28, XZR, X15	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
AND X8, X16, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SUB X27, X16, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X26, X8, X14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
STR X8, [SP, #312]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
FADD Z0.S, Z20.S, Z19.S	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	vect (100.0%)
LDR X26, [SP, #512]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X8, [SP, #312]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
FADDV S20, P0, Z0.S	1	0	0	0	0	0	0	0.75	0.75	0.25	0.25	0	0	0	0	0	11	2.50	vect (100.0%)
CBZ X8, 12d14 <main+0x1d54>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X28, [SP, #432]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X15, [SP, #592]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X16, [SP, #576]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
CMP X8, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.CC 12cc4 <main+0x1d04>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X8, [SP, #440]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
MOVI V16.2D, #0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
DUP V17.4S, V21.S[0]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (50.0%)
UBFM X28, X27, #62, #61	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
MOV V16.S[0], V20.S[0]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (12.5%)
SUB X26, X27, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
AND X27, X16, #0x0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
SUB X8, X29, #32	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X16, [SP, #576]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
FADDP V0.4S, V16.4S, V16.4S	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (50.0%)
LDR X28, [SP, #432]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X26, [SP, #512]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
FADDP S20, V0.2S	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
LDR Z21, [X8, #509, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	6	0.50	vect (100.0%)
CMP X16, X27	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 12cfc <main+0x1d3c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X16, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
SUB X8, X29, #32	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR Z20, [X8, #510, MUL VL]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
B.CS 12d40 <main+0x1d80>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X27, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
B 12e68 <main+0x1ea8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X28, [SP, #432]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X15, [SP, #592]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X16, [SP, #576]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
CMP X16, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
SUB X8, X29, #32	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR Z20, [X8, #510, MUL VL]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
B.CC 12d0c <main+0x1d4c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
CNTH X8, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
STR X26, [SP, #512]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
CMP X16, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.CS 12d60 <main+0x1da0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X27, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
B 12e08 <main+0x1e48>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X8, [SP, #376]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
DUP Z18.S, Z20.S[0]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	vect (100.0%)
DUP Z19.S, Z21.S[0]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	vect (100.0%)
PTRUE P0.B, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (100.0%)
PTRUE P4.S, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (100.0%)
ORR X26, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
AND X9, X16, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
LDR X8, [SP, #464]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
SUB X27, X16, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR X9, [SP, #312]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ADD X28, X9, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
LDR X28, [SP, #432]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X26, [SP, #512]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X16, [SP, #576]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X8, [SP, #312]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CBZ X8, 12e9c <main+0x1edc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X8, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.CC 12e68 <main+0x1ea8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X8, [SP, #440]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
DUP V16.4S, V20.S[0]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (50.0%)
DUP V17.4S, V21.S[0]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (50.0%)
UBFM X28, X27, #62, #61	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
SUB X26, X27, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
AND X27, X16, #0x0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SUB X8, X29, #32	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X16, [SP, #576]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X28, [SP, #432]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X26, [SP, #512]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
CMP X16, X27	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
LDR Z21, [X8, #509, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	6	0.50	vect (100.0%)
LDR Z20, [X8, #510, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	6	0.50	vect (100.0%)
B.EQ 12e9c <main+0x1edc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADDVL X8, SP, #3	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
LDR X27, [SP, #448]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X8, [X8, #10632]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X26, X27, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
CMP X26, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.CS 12a60 <main+0x1aa0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X9, X8, [SP, #328]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
MOVZ X10, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ORR W1, WZR, WZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
MADD X9, X9, X27, X10	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
SUB W8, W8, W27	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
UBFM X8, X8, #62, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
AND X9, X9, #0x0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X2, X8, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X0, X22, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
BL 100c0 <@plt_start@+0xa0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB X8, X29, #32	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X16, [SP, #576]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X15, [SP, #592]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR Z20, [X8, #510, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	6	0.50	vect (100.0%)
B 12a60 <main+0x1aa0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

CALL instructions

Details

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

CALL instructions

Details

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code