OV - attention-armclang-native - Loop 38 - attention-armclang-native

	Loop Id: 38	Module: attention-armclang-native	Source: attention_v2.cpp:26-33	Coverage: 1.31%

0x12f80 LDR	X15, [SP, #528]

0x12f84 FCVT	S0, D0

0x12f88 ADD	W14, W12, W10

0x12f8c ADD	X10, X10, #1

0x12f90 STR	S0, [X15, W14,UXTW #2]

0x12f94 AND	X14, X23, #0x7fffffff

0x12f98 CMP	X10, X14

0x12f9c B.EQ	12f48

0x12fa0 ADDVL	X14, SP, #3

0x12fa4 MOVI	D0, #0

0x12fa8 LDR	X14, [X14, #10632]

0x12fac CNTW	X15, ALL

0x12fb0 CMP	X14, X15

0x12fb4 B.CC	12fc8

0x12fb8 LDR	X14, [SP, #496]

0x12fbc CMN	W10, W14

0x12fc0 CSINC	W14, W13, WZR, #3

0x12fc4 TBZ	W14, #0, 1306c

0x12fc8 ORR	X15, XZR, XZR

0x12fcc SUB	W16, W27, W15

0x12fd0 ADD	X14, X15, #1

0x12fd4 TBZ	W16, #0, 12ff8

0x12fd8 ADD	W16, W11, W15

0x12fdc MADD	W15, W15, W23, W10

0x12fe0 LDR	S1, [X22, W16,UXTW #2]

0x12fe4 LDR	S2, [X25, W15,UXTW #2]

0x12fe8 ORR	X15, XZR, X14

0x12fec FCVT	D1, S1

0x12ff0 FCVT	D2, S2

0x12ff4 FMADD	D0, D1, D2, D0

0x12ff8 ADDVL	X16, SP, #3

0x12ffc LDR	X16, [X16, #10632]

0x13000 CMP	X16, X14

0x13004 B.EQ	12f80

0x13008 ADDVL	X14, SP, #3

0x1300c MUL	X17, X23, X15

0x13010 ADD	X18, X10, X23

0x13014 LDR	X14, [X14, #10632]

0x13018 ADD	X16, X10, X17

0x1301c ADD	X17, X18, X17

0x13020 SUB	X14, X14, X15

0x13024 ADD	W15, W8, W15

  (39) 0x13028 LDR	S1, [X22, W15,UXTW #2]

  (39) 0x1302c LDR	S2, [X25, W16,UXTW #2]

  (39) 0x13030 ADD	W18, W15, #1

  (39) 0x13034 SUBS	X14, X14, #2

  (39) 0x13038 ADD	X16, X16, X24

  (39) 0x1303c ADD	W15, W15, #2

  (39) 0x13040 FCVT	D1, S1

  (39) 0x13044 FCVT	D2, S2

  (39) 0x13048 FMADD	D0, D1, D2, D0

  (39) 0x1304c LDR	S1, [X22, W18,UXTW #2]

  (39) 0x13050 LDR	S2, [X25, W17,UXTW #2]

  (39) 0x13054 ADD	X17, X17, X24

  (39) 0x13058 FCVT	D1, S1

  (39) 0x1305c FCVT	D2, S2

  (39) 0x13060 FMADD	D0, D1, D2, D0

  (39) 0x13064 B.NE	13028

0x13068 B	12f80

0x1306c LDR	X18, [SP, #472]

0x13070 MOVI	V0.2D, #0

0x13074 MOVI	V1.2D, #0

0x13078 CNTW	X17, ALL

0x1307c ORR	X14, XZR, XZR

0x13080 PTRUE	P0.D, ALL

  (40) 0x13084 ADD	W15, W8, W14

  (40) 0x13088 ADD	X16, X22, W15,UXTW #2

  (40) 0x1308c LD1W	{Z2.D}, P0/Z, [X22, X15,LSL #2]

  (40) 0x13090 ADD	W15, W10, W14

  (40) 0x13094 ADD	X14, X14, X17

  (40) 0x13098 LD1W	{Z4.D}, P0/Z, [X25, X15,LSL #2]

  (40) 0x1309c CMP	X18, X14

  (40) 0x130a0 LD1W	{Z3.D}, P0/Z, [X16, #1, MUL VL]

  (40) 0x130a4 ADD	X16, X25, W15,UXTW #2

  (40) 0x130a8 LD1W	{Z5.D}, P0/Z, [X16, #1, MUL VL]

  (40) 0x130ac FCVT	Z2.D, P0/M, Z2.S

  (40) 0x130b0 FCVT	Z4.D, P0/M, Z4.S

  (40) 0x130b4 FCVT	Z3.D, P0/M, Z3.S

  (40) 0x130b8 FCVT	Z5.D, P0/M, Z5.S

  (40) 0x130bc FMLA	Z0.D, P0/M, Z2.D, Z4.D

  (40) 0x130c0 FMLA	Z1.D, P0/M, Z3.D, Z5.D

  (40) 0x130c4 B.NE	13084

0x130c8 FADD	Z0.D, Z1.D, Z0.D

0x130cc ADDVL	X14, SP, #3

0x130d0 ORR	X15, XZR, X18

0x130d4 FADDV	D0, P0, Z0.D

0x130d8 LDR	X14, [X14, #10632]

0x130dc CMP	X14, X18

0x130e0 B.EQ	12f80

0x130e4 B	12fcc

/home/eoseret/llm-attention/attention_v2.cpp: 26 - 33

--------------------------------------------------------------------------------

26:    for (unsigned int i = 0; i < M; ++i) {

27:       for (unsigned int j = 0; j < N; ++j) {  //vectorized

28:          double sum = 0.0;

29: #pragma clang loop vectorize(enable)

30:          for (unsigned int k = 0; k < K; ++k) { //vectorized

31:             sum += (double)A[i * K + k] * (double)B[k * N + j];

32:          }

33:          C[i * N + j] = alpha * static_cast<float>(sum);

Coverage (%)	Name	Module
►100.00+	__libc_start_call_main	libc.so.6
○	__libc_start_main	libc.so.6
○	_start	attention-armclang-native

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	2.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.10
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.07
Bottlenecks	P4,
Function	main
Source	attention_v2.cpp:26-27,attention_v2.cpp:30-33
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	8.00
CQA cycles if no scalar integer	4.00
CQA cycles if FP arith vectorized	8.00
CQA cycles if fully vectorized	7.25
Front-end cycles	7.13
P0 cycles	4.00
P1 cycles	4.00
P2 cycles	7.50
P3 cycles	7.25
P4 cycles	8.00
P5 cycles	7.25
P6 cycles	2.75
P7 cycles	2.75
P8 cycles	2.75
P9 cycles	2.75
P10 cycles	3.50
P11 cycles	3.17
P12 cycles	3.33
P13 cycles	0.00
P14 cycles	0.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	57.00
Nb uops	57.00
Nb loads	NA
Nb stores	1.00
Nb stack references	3.00
FLOP/cycle	1.25
Nb FLOP add-sub	8.00
Nb FLOP mul	0.00
Nb FLOP fma	1.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	1.13
Bytes prefetched	0.00
Bytes loaded	6.00
Bytes stored	3.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	9.52
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	0.00
Vectorization ratio add_sub	50.00
Vectorization ratio fma	0.00
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	32.14
Vector-efficiency ratio load	12.50
Vector-efficiency ratio store	12.50
Vector-efficiency ratio mul	25.00
Vector-efficiency ratio add_sub	62.50
Vector-efficiency ratio fma	25.00
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	28.13

Metric	Value
CQA speedup if no scalar integer	2.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.10
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.07
Bottlenecks	P4,
Function	main
Source	attention_v2.cpp:26-27,attention_v2.cpp:30-33
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	8.00
CQA cycles if no scalar integer	4.00
CQA cycles if FP arith vectorized	8.00
CQA cycles if fully vectorized	7.25
Front-end cycles	7.13
P0 cycles	4.00
P1 cycles	4.00
P2 cycles	7.50
P3 cycles	7.25
P4 cycles	8.00
P5 cycles	7.25
P6 cycles	2.75
P7 cycles	2.75
P8 cycles	2.75
P9 cycles	2.75
P10 cycles	3.50
P11 cycles	3.17
P12 cycles	3.33
P13 cycles	0.00
P14 cycles	0.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	57.00
Nb uops	57.00
Nb loads	NA
Nb stores	1.00
Nb stack references	3.00
FLOP/cycle	1.25
Nb FLOP add-sub	8.00
Nb FLOP mul	0.00
Nb FLOP fma	1.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	1.13
Bytes prefetched	0.00
Bytes loaded	6.00
Bytes stored	3.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	9.52
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	0.00
Vectorization ratio add_sub	50.00
Vectorization ratio fma	0.00
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	32.14
Vector-efficiency ratio load	12.50
Vector-efficiency ratio store	12.50
Vector-efficiency ratio mul	25.00
Vector-efficiency ratio add_sub	62.50
Vector-efficiency ratio fma	25.00
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	28.13

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	main
Source file and lines	attention_v2.cpp:26-33
Module	attention-armclang-native

The loop is defined in /home/eoseret/llm-attention/attention_v2.cpp:26-33.

Analyzed code is defined in /home/eoseret/llm-attention/attention_v2.cpp:26-27,30-33.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Failed to get the number of paths
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 8.00 to 4.00 cycles (2.00x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is not vectorized. Only 32% of vector register length is used (average across all VPU instructions). By fully vectorizing your loop, you can lower the cost of an iteration from 8.00 to 7.25 cycles (1.10x speedup).

Details

9% of VPU instructions are used in vector version (process two or more data elements in vector registers):

0% of VPU loads are used in vector version.
0% of VPU stores are used in vector version.
50% of VPU addition or subtraction instructions are used in vector version.
0% of VPU multiply instructions are used in vector version.
0% of VPU fused multiply-add instructions are used in vector version.
0% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ffast-math (included in Ofast) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

FMA

Detected 1 FMA (fused multiply-add) operations.

Conversion instructions

Detected expensive conversion instructions.

Details

FCVT: 3 occurrences►
- /home/eoseret/llm-attention/attention_v2.cpp:33
- /home/eoseret/llm-attention/attention_v2.cpp:31
- /home/eoseret/llm-attention/attention_v2.cpp:31

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 10 FP arithmetical operations:

9: addition or subtraction (1 inside FMA instructions)
1: multiply (all inside FMA instructions)

The binary loop is loading 6 bytes. The binary loop is storing 3 bytes.

Arithmetic intensity

Arithmetic intensity is 1.11 FP operations per loaded or stored byte.

General properties

nb instructions	57
nb uops	57
loop length	228
used w registers	11
used x registers	10
used b registers	0
used h registers	0
used s registers	4
used d registers	3
used q registers	0
used v registers	2
used z registers	2
nb stack references	3

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	7.13 cycles
front end	7.13 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	4.00	4.00	7.50	7.25	8.00	7.25	2.75	2.75	2.75	2.75	3.50	3.17	3.33	0.00	0.00
cycles	4.00	4.00	7.50	7.25	8.00	7.25	2.75	2.75	2.75	2.75	3.50	3.17	3.33	0.00	0.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	7.13
Dispatch	8.00
Overall L1	8.00

Vectorization ratios

INT

all	0%
load	0%
store	0%
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	33%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	100%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

INT+FP

all	9%
load	0%
store	0%
mul	0%
add-sub	50%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

INT

all	26%
load	12%
store	12%
mul	25%
add-sub	25%
fma	NA (no fma vectorizable/vectorized instructions)
other	31%

all	45%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	100%
fma	25%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	16%

INT+FP

all	32%
load	12%
store	12%
mul	25%
add-sub	62%
fma	25%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	28%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 8.00 cycles. At this rate:

0% of peak load performance is reached (0.75 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
0% of peak store performance is reached (0.38 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 12fa0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	Latency	Recip. throughput	Vectorization
LDR X15, [SP, #528]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
FCVT S0, D0	1	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	3	0.50	scal (25.0%)
ADD W14, W12, W10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
ADD X10, X10, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
STR S0, [X15, W14,UXTW #2]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	scal (12.5%)
AND X14, X23, #0x7fffffff	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
CMP X10, X14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 12f48 <main+0x1f88>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADDVL X14, SP, #3	1	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	N/A
MOVI D0, #0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (25.0%)
LDR X14, [X14, #10632]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
CNTW X15, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	N/A
CMP X14, X15	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.CC 12fc8 <main+0x2008>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X14, [SP, #496]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
CMN W10, W14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
CSINC W14, W13, WZR, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
TBZ W14, #0, 1306c <main+0x20ac>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X15, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
SUB W16, W27, W15	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
ADD X14, X15, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
TBZ W16, #0, 12ff8 <main+0x2038>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD W16, W11, W15	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
MADD W15, W15, W23, W10	1	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	N/A
LDR S1, [X22, W16,UXTW #2]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (12.5%)
LDR S2, [X25, W15,UXTW #2]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (12.5%)
ORR X15, XZR, X14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
FCVT D1, S1	1	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	3	0.50	scal (12.5%)
FCVT D2, S2	1	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	3	0.50	scal (12.5%)
FMADD D0, D1, D2, D0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	scal (25.0%)
ADDVL X16, SP, #3	1	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	N/A
LDR X16, [X16, #10632]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
CMP X16, X14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 12f80 <main+0x1fc0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADDVL X14, SP, #3	1	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	N/A
MUL X17, X23, X15	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	scal (25.0%)
ADD X18, X10, X23	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
LDR X14, [X14, #10632]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
ADD X16, X10, X17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
ADD X17, X18, X17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
SUB X14, X14, X15	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
ADD W15, W8, W15	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
B 12f80 <main+0x1fc0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X18, [SP, #472]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
MOVI V0.2D, #0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (25.0%)
MOVI V1.2D, #0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (25.0%)
CNTW X17, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
ORR X14, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
PTRUE P0.D, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (100.0%)
FADD Z0.D, Z1.D, Z0.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
ADDVL X14, SP, #3	1	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	N/A
ORR X15, XZR, X18	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
FADDV D0, P0, Z0.D	1	0	0	0	0	0	0	0.75	0.75	0.25	0.25	0	0	0	9	2	vect (100.0%)
LDR X14, [X14, #10632]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
CMP X14, X18	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33	N/A
B.EQ 12f80 <main+0x1fc0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
B 12fcc <main+0x200c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Function	main
Source file and lines	attention_v2.cpp:26-33
Module	attention-armclang-native

The loop is defined in /home/eoseret/llm-attention/attention_v2.cpp:26-33.

Analyzed code is defined in /home/eoseret/llm-attention/attention_v2.cpp:26-27,30-33.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Failed to get the number of paths
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 8.00 to 4.00 cycles (2.00x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

9% of VPU instructions are used in vector version (process two or more data elements in vector registers):

0% of VPU loads are used in vector version.
0% of VPU stores are used in vector version.
50% of VPU addition or subtraction instructions are used in vector version.
0% of VPU multiply instructions are used in vector version.
0% of VPU fused multiply-add instructions are used in vector version.
0% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ffast-math (included in Ofast) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

FMA

Detected 1 FMA (fused multiply-add) operations.

Conversion instructions

Detected expensive conversion instructions.

Details

FCVT: 3 occurrences►
- /home/eoseret/llm-attention/attention_v2.cpp:33
- /home/eoseret/llm-attention/attention_v2.cpp:31
- /home/eoseret/llm-attention/attention_v2.cpp:31

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 10 FP arithmetical operations:

9: addition or subtraction (1 inside FMA instructions)
1: multiply (all inside FMA instructions)

The binary loop is loading 6 bytes. The binary loop is storing 3 bytes.

Arithmetic intensity

Arithmetic intensity is 1.11 FP operations per loaded or stored byte.

General properties

nb instructions	57
nb uops	57
loop length	228
used w registers	11
used x registers	10
used b registers	0
used h registers	0
used s registers	4
used d registers	3
used q registers	0
used v registers	2
used z registers	2
nb stack references	3

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	7.13 cycles
front end	7.13 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	4.00	4.00	7.50	7.25	8.00	7.25	2.75	2.75	2.75	2.75	3.50	3.17	3.33	0.00	0.00
cycles	4.00	4.00	7.50	7.25	8.00	7.25	2.75	2.75	2.75	2.75	3.50	3.17	3.33	0.00	0.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	7.13
Dispatch	8.00
Overall L1	8.00

Vectorization ratios

INT

all	0%
load	0%
store	0%
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	33%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	100%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

INT+FP

all	9%
load	0%
store	0%
mul	0%
add-sub	50%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

INT

all	26%
load	12%
store	12%
mul	25%
add-sub	25%
fma	NA (no fma vectorizable/vectorized instructions)
other	31%

all	45%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	100%
fma	25%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	16%

INT+FP

all	32%
load	12%
store	12%
mul	25%
add-sub	62%
fma	25%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	28%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 8.00 cycles. At this rate:

0% of peak load performance is reached (0.75 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
0% of peak store performance is reached (0.38 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 12fa0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	Latency	Recip. throughput	Vectorization
LDR X15, [SP, #528]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
FCVT S0, D0	1	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	3	0.50	scal (25.0%)
ADD W14, W12, W10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
ADD X10, X10, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
STR S0, [X15, W14,UXTW #2]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	scal (12.5%)
AND X14, X23, #0x7fffffff	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
CMP X10, X14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 12f48 <main+0x1f88>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADDVL X14, SP, #3	1	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	N/A
MOVI D0, #0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (25.0%)
LDR X14, [X14, #10632]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
CNTW X15, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	N/A
CMP X14, X15	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.CC 12fc8 <main+0x2008>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X14, [SP, #496]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
CMN W10, W14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
CSINC W14, W13, WZR, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
TBZ W14, #0, 1306c <main+0x20ac>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X15, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
SUB W16, W27, W15	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
ADD X14, X15, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
TBZ W16, #0, 12ff8 <main+0x2038>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD W16, W11, W15	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
MADD W15, W15, W23, W10	1	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	N/A
LDR S1, [X22, W16,UXTW #2]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (12.5%)
LDR S2, [X25, W15,UXTW #2]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (12.5%)
ORR X15, XZR, X14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
FCVT D1, S1	1	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	3	0.50	scal (12.5%)
FCVT D2, S2	1	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	3	0.50	scal (12.5%)
FMADD D0, D1, D2, D0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	scal (25.0%)
ADDVL X16, SP, #3	1	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	N/A
LDR X16, [X16, #10632]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
CMP X16, X14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 12f80 <main+0x1fc0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADDVL X14, SP, #3	1	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	N/A
MUL X17, X23, X15	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	scal (25.0%)
ADD X18, X10, X23	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
LDR X14, [X14, #10632]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
ADD X16, X10, X17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
ADD X17, X18, X17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
SUB X14, X14, X15	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
ADD W15, W8, W15	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
B 12f80 <main+0x1fc0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X18, [SP, #472]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
MOVI V0.2D, #0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (25.0%)
MOVI V1.2D, #0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (25.0%)
CNTW X17, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
ORR X14, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
PTRUE P0.D, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (100.0%)
FADD Z0.D, Z1.D, Z0.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
ADDVL X14, SP, #3	1	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	N/A
ORR X15, XZR, X18	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
FADDV D0, P0, Z0.D	1	0	0	0	0	0	0	0.75	0.75	0.25	0.25	0	0	0	9	2	vect (100.0%)
LDR X14, [X14, #10632]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
CMP X14, X18	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33	N/A
B.EQ 12f80 <main+0x1fc0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
B 12fcc <main+0x200c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

FMA

Conversion instructions

Details

Workaround

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

FMA

Conversion instructions

Details

Workaround

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code