OV - attention-armclang-native - Loop 37 - attention-armclang-native

0x12f48 ADD	W9, W9, #1

0x12f4c ADD	X8, X8, X27

0x12f50 CMP	W9, W27

0x12f54 B.EQ	130e8

0x12f58 LDR	X13, [SP, #496]

0x12f5c MUL	W11, W9, W27

0x12f60 MUL	W12, W9, W23

0x12f64 ORR	X10, XZR, XZR

0x12f68 CMN	W11, W13

0x12f6c LDR	W13, [SP, #400]

0x12f70 CSINC	W13, W13, WZR, #3

0x12f74 B	12fa0

  (38) 0x12f80 LDR	X15, [SP, #528]

  (38) 0x12f84 FCVT	S0, D0

  (38) 0x12f88 ADD	W14, W12, W10

  (38) 0x12f8c ADD	X10, X10, #1

  (38) 0x12f90 STR	S0, [X15, W14,UXTW #2]

  (38) 0x12f94 AND	X14, X23, #0x7fffffff

  (38) 0x12f98 CMP	X10, X14

  (38) 0x12f9c B.EQ	12f48

  (38) 0x12fa0 ADDVL	X14, SP, #3

  (38) 0x12fa4 MOVI	D0, #0

  (38) 0x12fa8 LDR	X14, [X14, #10632]

  (38) 0x12fac CNTW	X15, ALL

  (38) 0x12fb0 CMP	X14, X15

  (38) 0x12fb4 B.CC	12fc8

  (38) 0x12fb8 LDR	X14, [SP, #496]

  (38) 0x12fbc CMN	W10, W14

  (38) 0x12fc0 CSINC	W14, W13, WZR, #3

  (38) 0x12fc4 TBZ	W14, #0, 1306c

  (38) 0x12fc8 ORR	X15, XZR, XZR

  (38) 0x12fcc SUB	W16, W27, W15

  (38) 0x12fd0 ADD	X14, X15, #1

  (38) 0x12fd4 TBZ	W16, #0, 12ff8

  (38) 0x12fd8 ADD	W16, W11, W15

  (38) 0x12fdc MADD	W15, W15, W23, W10

  (38) 0x12fe0 LDR	S1, [X22, W16,UXTW #2]

  (38) 0x12fe4 LDR	S2, [X25, W15,UXTW #2]

  (38) 0x12fe8 ORR	X15, XZR, X14

  (38) 0x12fec FCVT	D1, S1

  (38) 0x12ff0 FCVT	D2, S2

  (38) 0x12ff4 FMADD	D0, D1, D2, D0

  (38) 0x12ff8 ADDVL	X16, SP, #3

  (38) 0x12ffc LDR	X16, [X16, #10632]

  (38) 0x13000 CMP	X16, X14

  (38) 0x13004 B.EQ	12f80

  (38) 0x13008 ADDVL	X14, SP, #3

  (38) 0x1300c MUL	X17, X23, X15

  (38) 0x13010 ADD	X18, X10, X23

  (38) 0x13014 LDR	X14, [X14, #10632]

  (38) 0x13018 ADD	X16, X10, X17

  (38) 0x1301c ADD	X17, X18, X17

  (38) 0x13020 SUB	X14, X14, X15

  (38) 0x13024 ADD	W15, W8, W15

    (39) 0x13028 LDR	S1, [X22, W15,UXTW #2]

    (39) 0x1302c LDR	S2, [X25, W16,UXTW #2]

    (39) 0x13030 ADD	W18, W15, #1

    (39) 0x13034 SUBS	X14, X14, #2

    (39) 0x13038 ADD	X16, X16, X24

    (39) 0x1303c ADD	W15, W15, #2

    (39) 0x13040 FCVT	D1, S1

    (39) 0x13044 FCVT	D2, S2

    (39) 0x13048 FMADD	D0, D1, D2, D0

    (39) 0x1304c LDR	S1, [X22, W18,UXTW #2]

    (39) 0x13050 LDR	S2, [X25, W17,UXTW #2]

    (39) 0x13054 ADD	X17, X17, X24

    (39) 0x13058 FCVT	D1, S1

    (39) 0x1305c FCVT	D2, S2

    (39) 0x13060 FMADD	D0, D1, D2, D0

    (39) 0x13064 B.NE	13028

  (38) 0x13068 B	12f80

  (38) 0x1306c LDR	X18, [SP, #472]

  (38) 0x13070 MOVI	V0.2D, #0

  (38) 0x13074 MOVI	V1.2D, #0

  (38) 0x13078 CNTW	X17, ALL

  (38) 0x1307c ORR	X14, XZR, XZR

  (38) 0x13080 PTRUE	P0.D, ALL

    (40) 0x13084 ADD	W15, W8, W14

    (40) 0x13088 ADD	X16, X22, W15,UXTW #2

    (40) 0x1308c LD1W	{Z2.D}, P0/Z, [X22, X15,LSL #2]

    (40) 0x13090 ADD	W15, W10, W14

    (40) 0x13094 ADD	X14, X14, X17

    (40) 0x13098 LD1W	{Z4.D}, P0/Z, [X25, X15,LSL #2]

    (40) 0x1309c CMP	X18, X14

    (40) 0x130a0 LD1W	{Z3.D}, P0/Z, [X16, #1, MUL VL]

    (40) 0x130a4 ADD	X16, X25, W15,UXTW #2

    (40) 0x130a8 LD1W	{Z5.D}, P0/Z, [X16, #1, MUL VL]

    (40) 0x130ac FCVT	Z2.D, P0/M, Z2.S

    (40) 0x130b0 FCVT	Z4.D, P0/M, Z4.S

    (40) 0x130b4 FCVT	Z3.D, P0/M, Z3.S

    (40) 0x130b8 FCVT	Z5.D, P0/M, Z5.S

    (40) 0x130bc FMLA	Z0.D, P0/M, Z2.D, Z4.D

    (40) 0x130c0 FMLA	Z1.D, P0/M, Z3.D, Z5.D

    (40) 0x130c4 B.NE	13084

  (38) 0x130c8 FADD	Z0.D, Z1.D, Z0.D

  (38) 0x130cc ADDVL	X14, SP, #3

  (38) 0x130d0 ORR	X15, XZR, X18

  (38) 0x130d4 FADDV	D0, P0, Z0.D

  (38) 0x130d8 LDR	X14, [X14, #10632]

  (38) 0x130dc CMP	X14, X18

  (38) 0x130e0 B.EQ	12f80

  (38) 0x130e4 B	12fcc

/home/eoseret/llm-attention/attention_v2.cpp: 26 - 33

--------------------------------------------------------------------------------

26:    for (unsigned int i = 0; i < M; ++i) {

27:       for (unsigned int j = 0; j < N; ++j) {  //vectorized

28:          double sum = 0.0;

29: #pragma clang loop vectorize(enable)

30:          for (unsigned int k = 0; k < K; ++k) { //vectorized

31:             sum += (double)A[i * K + k] * (double)B[k * N + j];

32:          }

33:          C[i * N + j] = alpha * static_cast<float>(sum);

Coverage (%)	Name	Module
►100.00+	__libc_start_call_main	libc.so.6
○	__libc_start_main	libc.so.6
○	_start	attention-armclang-native

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	6.40
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.33
Bottlenecks	P2, P3, P4, P5,
Function	main
Source	attention_v2.cpp:26-26
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	2.00
CQA cycles if no scalar integer	2.00
CQA cycles if FP arith vectorized	2.00
CQA cycles if fully vectorized	0.31
Front-end cycles	1.50
P0 cycles	1.00
P1 cycles	1.00
P2 cycles	2.00
P3 cycles	2.00
P4 cycles	2.00
P5 cycles	2.00
P6 cycles	0.00
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	0.00
P10 cycles	0.67
P11 cycles	0.67
P12 cycles	0.67
P13 cycles	0.00
P14 cycles	0.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	12.00
Nb uops	12.00
Nb loads	NA
Nb stores	0.00
Nb stack references	2.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	1.50
Bytes prefetched	0.00
Bytes loaded	3.00
Bytes stored	0.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	NA
Vectorization ratio store	NA
Vectorization ratio mul	0.00
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	17.50
Vector-efficiency ratio load	NA
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	12.50
Vector-efficiency ratio add_sub	18.75
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	18.75

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	6.40
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.33
Bottlenecks	P2, P3, P4, P5,
Function	main
Source	attention_v2.cpp:26-26
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	2.00
CQA cycles if no scalar integer	2.00
CQA cycles if FP arith vectorized	2.00
CQA cycles if fully vectorized	0.31
Front-end cycles	1.50
P0 cycles	1.00
P1 cycles	1.00
P2 cycles	2.00
P3 cycles	2.00
P4 cycles	2.00
P5 cycles	2.00
P6 cycles	0.00
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	0.00
P10 cycles	0.67
P11 cycles	0.67
P12 cycles	0.67
P13 cycles	0.00
P14 cycles	0.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	12.00
Nb uops	12.00
Nb loads	NA
Nb stores	0.00
Nb stack references	2.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	1.50
Bytes prefetched	0.00
Bytes loaded	3.00
Bytes stored	0.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	NA
Vectorization ratio store	NA
Vectorization ratio mul	0.00
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	17.50
Vector-efficiency ratio load	NA
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	12.50
Vector-efficiency ratio add_sub	18.75
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	18.75

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	main
Source file and lines	attention_v2.cpp:26-33
Module	attention-armclang-native

The loop is defined in /home/eoseret/llm-attention/attention_v2.cpp:26-33.

Analyzed code is defined in /home/eoseret/llm-attention/attention_v2.cpp:26.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Failed to get the number of paths
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. Only 17% of vector register length is used (average across all VPU instructions). By vectorizing your loop, you can lower the cost of an iteration from 2.00 to 0.31 cycles (6.40x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ffast-math (included in Ofast) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 3 bytes.

General properties

nb instructions	12
nb uops	12
loop length	48
used w registers	7
used x registers	5
used b registers	0
used h registers	0
used s registers	1
used d registers	0
used q registers	0
used v registers	0
used z registers	0
nb stack references	2

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	1.50 cycles
front end	1.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	1.00	1.00	2.00	2.00	2.00	2.00	0.00	0.00	0.00	0.00	0.67	0.67	0.67	0.00	0.00
cycles	1.00	1.00	2.00	2.00	2.00	2.00	0.00	0.00	0.00	0.00	0.67	0.67	0.67	0.00	0.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

NA

Cycles summary

Front-end	1.50
Dispatch	2.00
Overall L1	2.00

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	17%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	12%
add-sub	18%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	18%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 2.00 cycles. At this rate:

1% of peak load performance is reached (1.50 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 12f58

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P10	P11	P12	Latency	Recip. throughput	Vectorization
ADD W9, W9, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25	scal (12.5%)
ADD X8, X8, X27	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25	scal (25.0%)
CMP W9, W27	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.33	scal (12.5%)
B.EQ 130e8 <main+0x2128>	1	0.50	0.50	0	0	0	0	0	0	0	1	0.50	N/A
LDR X13, [SP, #496]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
MUL W11, W9, W27	1	0	0	0	0	0.50	0.50	0	0	0	2	0.50	N/A
MUL W12, W9, W23	1	0	0	0	0	0.50	0.50	0	0	0	2	0.50	scal (12.5%)
ORR X10, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25	scal (25.0%)
CMN W11, W13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.33	N/A
LDR W13, [SP, #400]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
CSINC W13, W13, WZR, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25	N/A
B 12fa0 <main+0x1fe0>	1	0.50	0.50	0	0	0	0	0	0	0	1	0.50	N/A

Function	main
Source file and lines	attention_v2.cpp:26-33
Module	attention-armclang-native

The loop is defined in /home/eoseret/llm-attention/attention_v2.cpp:26-33.

Analyzed code is defined in /home/eoseret/llm-attention/attention_v2.cpp:26.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Failed to get the number of paths
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. Only 17% of vector register length is used (average across all VPU instructions). By vectorizing your loop, you can lower the cost of an iteration from 2.00 to 0.31 cycles (6.40x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ffast-math (included in Ofast) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 3 bytes.

General properties

nb instructions	12
nb uops	12
loop length	48
used w registers	7
used x registers	5
used b registers	0
used h registers	0
used s registers	1
used d registers	0
used q registers	0
used v registers	0
used z registers	0
nb stack references	2

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	1.50 cycles
front end	1.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	1.00	1.00	2.00	2.00	2.00	2.00	0.00	0.00	0.00	0.00	0.67	0.67	0.67	0.00	0.00
cycles	1.00	1.00	2.00	2.00	2.00	2.00	0.00	0.00	0.00	0.00	0.67	0.67	0.67	0.00	0.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

NA

Cycles summary

Front-end	1.50
Dispatch	2.00
Overall L1	2.00

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	17%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	12%
add-sub	18%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	18%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 2.00 cycles. At this rate:

1% of peak load performance is reached (1.50 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 12f58

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P10	P11	P12	Latency	Recip. throughput	Vectorization
ADD W9, W9, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25	scal (12.5%)
ADD X8, X8, X27	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25	scal (25.0%)
CMP W9, W27	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.33	scal (12.5%)
B.EQ 130e8 <main+0x2128>	1	0.50	0.50	0	0	0	0	0	0	0	1	0.50	N/A
LDR X13, [SP, #496]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
MUL W11, W9, W27	1	0	0	0	0	0.50	0.50	0	0	0	2	0.50	N/A
MUL W12, W9, W23	1	0	0	0	0	0.50	0.50	0	0	0	2	0.50	scal (12.5%)
ORR X10, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25	scal (25.0%)
CMN W11, W13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.33	N/A
LDR W13, [SP, #400]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
CSINC W13, W13, WZR, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25	N/A
B 12fa0 <main+0x1fe0>	1	0.50	0.50	0	0	0	0	0	0	0	1	0.50	N/A

Report Configuration

Vectorization

Details

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code