OV - attention-armclang-native - Loop 33 - attention-armclang-native

	Loop Id: 33	Module: attention-armclang-native	Source: attention_v2.cpp:52-53	Coverage: 0.10%

0x12be4 LDR	Z0, [X28, MUL VL]    [1]

0x12be8 LDR	Z1, [X28, #1, MUL VL]    [1]

0x12bec PTRUE	P0.S, ALL

0x12bf0 FSUB	Z0.S, Z0.S, Z18.S

0x12bf4 FSUB	Z16.S, Z1.S, Z18.S

0x12bf8 BL	10190

0x12bfc ORR	Z17.D, Z0.D, Z0.D

0x12c00 ORR	Z0.D, Z16.D, Z16.D

0x12c04 PTRUE	P0.S, ALL

0x12c08 BL	10190

0x12c0c CNTH	X8, ALL

0x12c10 FADD	Z19.S, Z17.S, Z19.S

0x12c14 FADD	Z20.S, Z0.S, Z20.S

0x12c18 ADDS	X26, X26, X8

0x12c1c RDVL	X8, #2

0x12c20 PTRUE	P0.S, ALL

0x12c24 ADD	X28, X28, X8

0x12c28 B.NE	12be4

/home/eoseret/llm-attention/attention_v2.cpp: 52 - 53

--------------------------------------------------------------------------------

52:       for (int idx = 0; idx <= row; ++idx) // vectorised

53:          sum += expf(S_row[idx] - max_val);

Coverage (%)	Name	Module
►100.00+	__libc_start_call_main	libc.so.6
○	__libc_start_main	libc.so.6
○	_start	attention-armclang-native

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.67
Bottlenecks	P4,
Function	main
Source	attention_v2.cpp:52-53
Source loop unroll info	unrolled by 16
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	16
CQA cycles	5.00
CQA cycles if no scalar integer	5.00
CQA cycles if FP arith vectorized	5.00
CQA cycles if fully vectorized	5.00
Front-end cycles	2.25
P0 cycles	1.50
P1 cycles	1.50
P2 cycles	1.50
P3 cycles	1.25
P4 cycles	5.00
P5 cycles	1.25
P6 cycles	3.00
P7 cycles	3.00
P8 cycles	2.00
P9 cycles	2.00
P10 cycles	1.00
P11 cycles	1.00
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	0.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	2
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	18.00
Nb uops	18.00
Nb loads	NA
Nb stores	0.00
Nb stack references	0.00
FLOP/cycle	6.40
Nb FLOP add-sub	32.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	12.80
Bytes prefetched	0.00
Bytes loaded	64.00
Bytes stored	0.00
Stride 0	0.00
Stride 1	0.00
Stride n	0.00
Stride unknown	1.00
Stride indirect	0.00
Vectorization ratio all	66.67
Vectorization ratio load	100.00
Vectorization ratio store	NA
Vectorization ratio mul	NA
Vectorization ratio add_sub	80.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	40.00
Vector-efficiency ratio all	93.75
Vector-efficiency ratio load	100.00
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	85.00
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	100.00

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.67
Bottlenecks	P4,
Function	main
Source	attention_v2.cpp:52-53
Source loop unroll info	unrolled by 16
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	16
CQA cycles	5.00
CQA cycles if no scalar integer	5.00
CQA cycles if FP arith vectorized	5.00
CQA cycles if fully vectorized	5.00
Front-end cycles	2.25
P0 cycles	1.50
P1 cycles	1.50
P2 cycles	1.50
P3 cycles	1.25
P4 cycles	5.00
P5 cycles	1.25
P6 cycles	3.00
P7 cycles	3.00
P8 cycles	2.00
P9 cycles	2.00
P10 cycles	1.00
P11 cycles	1.00
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	0.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	2
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	18.00
Nb uops	18.00
Nb loads	NA
Nb stores	0.00
Nb stack references	0.00
FLOP/cycle	6.40
Nb FLOP add-sub	32.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	12.80
Bytes prefetched	0.00
Bytes loaded	64.00
Bytes stored	0.00
Stride 0	0.00
Stride 1	0.00
Stride n	0.00
Stride unknown	1.00
Stride indirect	0.00
Vectorization ratio all	66.67
Vectorization ratio load	100.00
Vectorization ratio store	NA
Vectorization ratio mul	NA
Vectorization ratio add_sub	80.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	40.00
Vector-efficiency ratio all	93.75
Vector-efficiency ratio load	100.00
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	85.00
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	100.00

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	main
Source file and lines	attention_v2.cpp:52-53
Module	attention-armclang-native

The loop is defined in /home/eoseret/llm-attention/attention_v2.cpp:52-53.

The related source loop is unrolled by 16 (including vectorization).

gain
potential
hint
expert

Vectorization

Your loop is partially vectorized. 93% of vector register length is used (average across all VPU instructions).

Details

66% of VPU instructions are used in vector version (process two or more data elements in vector registers):

80% of VPU addition or subtraction instructions are used in vector version.
40% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

No data for this section

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

unknown: 2 occurrences►
- /home/eoseret/llm-attention/attention_v2.cpp:53
- /home/eoseret/llm-attention/attention_v2.cpp:53

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant unknown stride: 1 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 32 FP arithmetical operations:

32: addition or subtraction

The binary loop is loading 64 bytes.

Arithmetic intensity

Arithmetic intensity is 0.50 FP operations per loaded or stored byte.

General properties

nb instructions	18
nb uops	18
loop length	72
used w registers	0
used x registers	3
used b registers	0
used h registers	0
used s registers	0
used d registers	0
used q registers	0
used v registers	0
used z registers	7
nb stack references	0

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	2.25 cycles
front end	2.25 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	1.50	1.50	1.50	1.25	5.00	1.25	3.00	3.00	0.00	0.00	1.00	1.00	0.00	0.00	0.00
cycles	1.50	1.50	1.50	1.25	5.00	1.25	3.00	3.00	2.00	2.00	1.00	1.00	0.00	0.00	0.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	2.00

Cycles summary

Front-end	2.25
Dispatch	5.00
Data deps.	2.00
Overall L1	5.00

Vectorization ratios

INT

all	50%
load	100%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	40%

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	66%
load	100%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	80%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	40%

Vector efficiency ratios

INT

all	90%
load	100%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	25%
fma	NA (no fma vectorizable/vectorized instructions)
other	100%

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	93%
load	100%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	85%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	100%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 5.00 cycles. At this rate:

13% of peak load performance is reached (12.80 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 12be4

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P10	P11	Latency	Recip. throughput	Vectorization
LDR Z0, [X28, MUL VL]	1	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
LDR Z1, [X28, #1, MUL VL]	1	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
PTRUE P0.S, ALL	1	0	0	0	0	1	0	0	0	0	0	2	1	scal (100.0%)
FSUB Z0.S, Z0.S, Z18.S	1	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
FSUB Z16.S, Z1.S, Z18.S	1	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
BL 10190 <@plt_start@+0x170>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	1	0.50	N/A
ORR Z17.D, Z0.D, Z0.D	1	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
ORR Z0.D, Z16.D, Z16.D	1	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
PTRUE P0.S, ALL	1	0	0	0	0	1	0	0	0	0	0	2	1	scal (100.0%)
BL 10190 <@plt_start@+0x170>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	1	0.50	N/A
CNTH X8, ALL	1	0	0	0	0	1	0	0	0	0	0	2	1	N/A
FADD Z19.S, Z17.S, Z19.S	1	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
FADD Z20.S, Z0.S, Z20.S	1	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
ADDS X26, X26, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.33	scal (25.0%)
RDVL X8, #2	1	0	0	0	0	1	0	0	0	0	0	2	1	N/A
PTRUE P0.S, ALL	1	0	0	0	0	1	0	0	0	0	0	2	1	scal (100.0%)
ADD X28, X28, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
B.NE 12be4 <main+0x1c24>	1	0.50	0.50	0	0	0	0	0	0	0	0	1	0.50	N/A

Function	main
Source file and lines	attention_v2.cpp:52-53
Module	attention-armclang-native

The loop is defined in /home/eoseret/llm-attention/attention_v2.cpp:52-53.

The related source loop is unrolled by 16 (including vectorization).

gain
potential
hint
expert

Vectorization

Your loop is partially vectorized. 93% of vector register length is used (average across all VPU instructions).

Details

66% of VPU instructions are used in vector version (process two or more data elements in vector registers):

80% of VPU addition or subtraction instructions are used in vector version.
40% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

No data for this section

CALL instructions

Detected function call instructions.

Details

unknown: 2 occurrences►
- /home/eoseret/llm-attention/attention_v2.cpp:53
- /home/eoseret/llm-attention/attention_v2.cpp:53

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant unknown stride: 1 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 32 FP arithmetical operations:

32: addition or subtraction

The binary loop is loading 64 bytes.

Arithmetic intensity

Arithmetic intensity is 0.50 FP operations per loaded or stored byte.

General properties

nb instructions	18
nb uops	18
loop length	72
used w registers	0
used x registers	3
used b registers	0
used h registers	0
used s registers	0
used d registers	0
used q registers	0
used v registers	0
used z registers	7
nb stack references	0

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	2.25 cycles
front end	2.25 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	1.50	1.50	1.50	1.25	5.00	1.25	3.00	3.00	0.00	0.00	1.00	1.00	0.00	0.00	0.00
cycles	1.50	1.50	1.50	1.25	5.00	1.25	3.00	3.00	2.00	2.00	1.00	1.00	0.00	0.00	0.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	2.00

Cycles summary

Front-end	2.25
Dispatch	5.00
Data deps.	2.00
Overall L1	5.00

Vectorization ratios

INT

all	50%
load	100%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	40%

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	66%
load	100%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	80%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	40%

Vector efficiency ratios

INT

all	90%
load	100%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	25%
fma	NA (no fma vectorizable/vectorized instructions)
other	100%

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	93%
load	100%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	85%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	100%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 5.00 cycles. At this rate:

13% of peak load performance is reached (12.80 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 12be4

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P10	P11	Latency	Recip. throughput	Vectorization
LDR Z0, [X28, MUL VL]	1	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
LDR Z1, [X28, #1, MUL VL]	1	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
PTRUE P0.S, ALL	1	0	0	0	0	1	0	0	0	0	0	2	1	scal (100.0%)
FSUB Z0.S, Z0.S, Z18.S	1	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
FSUB Z16.S, Z1.S, Z18.S	1	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
BL 10190 <@plt_start@+0x170>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	1	0.50	N/A
ORR Z17.D, Z0.D, Z0.D	1	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
ORR Z0.D, Z16.D, Z16.D	1	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
PTRUE P0.S, ALL	1	0	0	0	0	1	0	0	0	0	0	2	1	scal (100.0%)
BL 10190 <@plt_start@+0x170>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	1	0.50	N/A
CNTH X8, ALL	1	0	0	0	0	1	0	0	0	0	0	2	1	N/A
FADD Z19.S, Z17.S, Z19.S	1	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
FADD Z20.S, Z0.S, Z20.S	1	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
ADDS X26, X26, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.33	scal (25.0%)
RDVL X8, #2	1	0	0	0	0	1	0	0	0	0	0	2	1	N/A
PTRUE P0.S, ALL	1	0	0	0	0	1	0	0	0	0	0	2	1	scal (100.0%)
ADD X28, X28, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
B.NE 12be4 <main+0x1c24>	1	0.50	0.50	0	0	0	0	0	0	0	0	1	0.50	N/A

Report Configuration

Vectorization

Details

CALL instructions

Details

Slow data structures access

Details

Workaround

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

CALL instructions

Details

Slow data structures access

Details

Workaround

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code