OV - attention-gcc-native - Loop 22

0x410d80 LDR	S31, [X2, #12]    [1]

0x410d84 LDP	S29, S30, [X2, #4]    [1]

0x410d88 LDR	S28, [X2], #16    [1]

0x410d8c STR	S28, [X0]    [2]

0x410d90 STR	S29, [X0, X6,LSL #2]    [2]

0x410d94 STR	S30, [X0, X9]    [2]

0x410d98 STR	S31, [X0, X7]    [2]

0x410d9c ADD	X0, X0, X8

0x410da0 CMP	X5, X2

0x410da4 B.NE	410d80

/usr/include/c++/14/bits/stl_vector.h: 1128 - 1128

--------------------------------------------------------------------------------

1128:       operator[](size_type __n) _GLIBCXX_NOEXCEPT

/home/eoseret/llm-attention/attention_v2.cpp: 237 - 238

--------------------------------------------------------------------------------

237:          for (int j = 0; j < dim; ++j)// vectorized

238:             h_KT[j * context_size + i] = h_K[i * dim + j];

Coverage (%)	Name	Source Location	Module
►100.00+	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start	stl_vector.h:1920	attention-gcc-native

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	7.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.17
Bottlenecks	P10, P11, P12,
Function	main
Source	stl_vector.h:1128-1128,attention_v2.cpp:237-238
Source loop unroll info	multi-versionned
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	2.33
CQA cycles if no scalar integer	2.33
CQA cycles if FP arith vectorized	2.33
CQA cycles if fully vectorized	0.33
Front-end cycles	1.25
P0 cycles	0.50
P1 cycles	0.50
P2 cycles	0.75
P3 cycles	0.75
P4 cycles	0.75
P5 cycles	0.75
P6 cycles	2.00
P7 cycles	2.00
P8 cycles	0.00
P9 cycles	0.00
P10 cycles	2.33
P11 cycles	2.33
P12 cycles	2.33
P13 cycles	0.00
P14 cycles	0.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	10.00
Nb uops	10.00
Nb loads	NA
Nb stores	4.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	7.71
Bytes prefetched	0.00
Bytes loaded	6.00
Bytes stored	12.00
Stride 0	1.00
Stride 1	0.00
Stride n	0.00
Stride unknown	1.00
Stride indirect	0.00
Vectorization ratio all	14.29
Vectorization ratio load	33.33
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	NA
Vector-efficiency ratio all	14.29
Vector-efficiency ratio load	16.67
Vector-efficiency ratio store	12.50
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	NA

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	7.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.17
Bottlenecks	P10, P11, P12,
Function	main
Source	stl_vector.h:1128-1128,attention_v2.cpp:237-238
Source loop unroll info	multi-versionned
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	2.33
CQA cycles if no scalar integer	2.33
CQA cycles if FP arith vectorized	2.33
CQA cycles if fully vectorized	0.33
Front-end cycles	1.25
P0 cycles	0.50
P1 cycles	0.50
P2 cycles	0.75
P3 cycles	0.75
P4 cycles	0.75
P5 cycles	0.75
P6 cycles	2.00
P7 cycles	2.00
P8 cycles	0.00
P9 cycles	0.00
P10 cycles	2.33
P11 cycles	2.33
P12 cycles	2.33
P13 cycles	0.00
P14 cycles	0.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	10.00
Nb uops	10.00
Nb loads	NA
Nb stores	4.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	7.71
Bytes prefetched	0.00
Bytes loaded	6.00
Bytes stored	12.00
Stride 0	1.00
Stride 1	0.00
Stride n	0.00
Stride unknown	1.00
Stride indirect	0.00
Vectorization ratio all	14.29
Vectorization ratio load	33.33
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	NA
Vector-efficiency ratio all	14.29
Vector-efficiency ratio load	16.67
Vector-efficiency ratio store	12.50
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	NA

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	main
Source file and lines	attention_v2.cpp:237-238
Module	attention-gcc-native

The loop is defined in:

/usr/include/c++/14/bits/stl_vector.h:1128
/home/eoseret/llm-attention/attention_v2.cpp:237-238

The related source loop is multi-versionned.

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. Only 14% of vector register length is used (average across all VPU instructions). By fully vectorizing your loop, you can lower the cost of an iteration from 2.33 to 0.33 cycles (7.00x speedup).

Details

14% of VPU instructions are used in vector version (process two or more data elements in vector registers):

33% of VPU loads are used in vector version.
0% of VPU stores are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant unknown stride: 1 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 6 bytes. The binary loop is storing 12 bytes.

General properties

nb instructions	10
nb uops	10
loop length	40
used w registers	0
used x registers	7
used b registers	0
used h registers	0
used s registers	4
used d registers	0
used q registers	0
used v registers	0
used z registers	0
nb stack references	0

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	1.25 cycles
front end	1.25 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	0.50	0.50	0.75	0.75	0.75	0.75	2.00	2.00	0.00	0.00	2.33	2.33	2.33	0.00	0.00
cycles	0.50	0.50	0.75	0.75	0.75	0.75	2.00	2.00	0.00	0.00	2.33	2.33	2.33	0.00	0.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	1.25
Dispatch	2.33
Data deps.	1.00
Overall L1	2.33

Vectorization ratios

all	14%
load	33%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

Vector efficiency ratios

all	14%
load	16%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 2.33 cycles. At this rate:

2% of peak load performance is reached (2.57 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
10% of peak store performance is reached (5.14 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 410d80

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P10	P11	P12	Latency	Recip. throughput	Vectorization
LDR S31, [X2, #12]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (12.5%)
LDP S29, S30, [X2, #4]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (25.0%)
LDR S28, [X2], #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0.33	0.33	0.33	6	0.33	scal (12.5%)
STR S28, [X0]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50	scal (12.5%)
STR S29, [X0, X6,LSL #2]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50	scal (12.5%)
STR S30, [X0, X9]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50	scal (12.5%)
STR S31, [X0, X7]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50	scal (12.5%)
ADD X0, X0, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
CMP X5, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	N/A
B.NE 410d80 <main+0xbc0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Function	main
Source file and lines	attention_v2.cpp:237-238
Module	attention-gcc-native

The loop is defined in:

/usr/include/c++/14/bits/stl_vector.h:1128
/home/eoseret/llm-attention/attention_v2.cpp:237-238

The related source loop is multi-versionned.

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. Only 14% of vector register length is used (average across all VPU instructions). By fully vectorizing your loop, you can lower the cost of an iteration from 2.33 to 0.33 cycles (7.00x speedup).

Details

14% of VPU instructions are used in vector version (process two or more data elements in vector registers):

33% of VPU loads are used in vector version.
0% of VPU stores are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant unknown stride: 1 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 6 bytes. The binary loop is storing 12 bytes.

General properties

nb instructions	10
nb uops	10
loop length	40
used w registers	0
used x registers	7
used b registers	0
used h registers	0
used s registers	4
used d registers	0
used q registers	0
used v registers	0
used z registers	0
nb stack references	0

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	1.25 cycles
front end	1.25 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	0.50	0.50	0.75	0.75	0.75	0.75	2.00	2.00	0.00	0.00	2.33	2.33	2.33	0.00	0.00
cycles	0.50	0.50	0.75	0.75	0.75	0.75	2.00	2.00	0.00	0.00	2.33	2.33	2.33	0.00	0.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	1.25
Dispatch	2.33
Data deps.	1.00
Overall L1	2.33

Vectorization ratios

all	14%
load	33%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

Vector efficiency ratios

all	14%
load	16%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 2.33 cycles. At this rate:

2% of peak load performance is reached (2.57 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
10% of peak store performance is reached (5.14 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 410d80

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P10	P11	P12	Latency	Recip. throughput	Vectorization
LDR S31, [X2, #12]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (12.5%)
LDP S29, S30, [X2, #4]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (25.0%)
LDR S28, [X2], #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0.33	0.33	0.33	6	0.33	scal (12.5%)
STR S28, [X0]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50	scal (12.5%)
STR S29, [X0, X6,LSL #2]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50	scal (12.5%)
STR S30, [X0, X9]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50	scal (12.5%)
STR S31, [X0, X7]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50	scal (12.5%)
ADD X0, X0, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
CMP X5, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	N/A
B.NE 410d80 <main+0xbc0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Report Configuration

Vectorization

Details

Workaround

Slow data structures access

Details

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Workaround

Slow data structures access

Details

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code