OV - attention-gcc-native - Loop 15

	Loop Id: 15	Module: attention-gcc-native	Source: attention_v2.cpp:27-233 [...]	Coverage: 0.44%

0x410ea4 MOVI	D21, #0

0x410ea8 ORR	W10, WZR, W13

0x410eac MOVZ	W0, #0

  (14) 0x410eb0 ADD	W12, W0, W3

  (14) 0x410eb4 LDR	S22, [X22, W10,UXTW #2]

  (14) 0x410eb8 ADD	W0, W0, #1

  (14) 0x410ebc ADD	W10, W10, W5

  (14) 0x410ec0 LDR	S20, [X20, X12,LSL #2]

  (14) 0x410ec4 FCVT	D22, S22

  (14) 0x410ec8 FCVT	D20, S20

  (14) 0x410ecc FMADD	D21, D20, D22, D21

  (14) 0x410ed0 CMP	W0, W4

  (14) 0x410ed4 B.CC	410eb0

0x410ed8 FCVT	S21, D21

0x410edc ADD	W0, W13, W11

0x410ee0 ADD	W13, W13, #1

0x410ee4 FMUL	S21, S21, S15

0x410ee8 STR	S21, [X28, X0,LSL #2]

0x410eec CMP	W5, W13

0x410ef0 B.HI	410ea4

/home/eoseret/llm-attention/attention_v2.cpp: 27 - 233

--------------------------------------------------------------------------------

27:       for (unsigned int j = 0; j < N; ++j) {  //vectorized

28:          double sum = 0.0;

29: #pragma clang loop vectorize(enable)

30:          for (unsigned int k = 0; k < K; ++k) { //vectorized

31:             sum += (double)A[i * K + k] * (double)B[k * N + j];

32:          }

33:          C[i * N + j] = alpha * static_cast<float>(sum);

[...]

233:       start = std::chrono::steady_clock::now();

Coverage (%)	Name	Source Location	Module
►100.00+	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start	stl_vector.h:1920	attention-gcc-native

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	1.25
CQA speedup if FP arith vectorized	1.25
CQA speedup if fully vectorized	7.27
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.25
Bottlenecks	micro-operation queue, P2, P3, P4, P5,
Function	main
Source	attention_v2.cpp:27-30,attention_v2.cpp:33-33,attention_v2.cpp:233-233
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	1.25
CQA cycles if no scalar integer	1.00
CQA cycles if FP arith vectorized	1.00
CQA cycles if fully vectorized	0.17
Front-end cycles	1.25
P0 cycles	0.50
P1 cycles	0.50
P2 cycles	1.25
P3 cycles	1.25
P4 cycles	1.25
P5 cycles	1.25
P6 cycles	1.00
P7 cycles	1.00
P8 cycles	1.00
P9 cycles	1.00
P10 cycles	0.50
P11 cycles	0.50
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	0.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	10.00
Nb uops	10.00
Nb loads	NA
Nb stores	1.00
Nb stack references	0.00
FLOP/cycle	0.80
Nb FLOP add-sub	0.00
Nb FLOP mul	1.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	2.40
Bytes prefetched	0.00
Bytes loaded	0.00
Bytes stored	3.00
Stride 0	0.00
Stride 1	0.00
Stride n	0.00
Stride unknown	2.00
Stride indirect	0.00
Vectorization ratio all	0.00
Vectorization ratio load	NA
Vectorization ratio store	0.00
Vectorization ratio mul	0.00
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	17.50
Vector-efficiency ratio load	NA
Vector-efficiency ratio store	12.50
Vector-efficiency ratio mul	12.50
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	20.83

Metric	Value
CQA speedup if no scalar integer	1.25
CQA speedup if FP arith vectorized	1.25
CQA speedup if fully vectorized	7.27
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.25
Bottlenecks	micro-operation queue, P2, P3, P4, P5,
Function	main
Source	attention_v2.cpp:27-30,attention_v2.cpp:33-33,attention_v2.cpp:233-233
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	1.25
CQA cycles if no scalar integer	1.00
CQA cycles if FP arith vectorized	1.00
CQA cycles if fully vectorized	0.17
Front-end cycles	1.25
P0 cycles	0.50
P1 cycles	0.50
P2 cycles	1.25
P3 cycles	1.25
P4 cycles	1.25
P5 cycles	1.25
P6 cycles	1.00
P7 cycles	1.00
P8 cycles	1.00
P9 cycles	1.00
P10 cycles	0.50
P11 cycles	0.50
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	0.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	10.00
Nb uops	10.00
Nb loads	NA
Nb stores	1.00
Nb stack references	0.00
FLOP/cycle	0.80
Nb FLOP add-sub	0.00
Nb FLOP mul	1.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	2.40
Bytes prefetched	0.00
Bytes loaded	0.00
Bytes stored	3.00
Stride 0	0.00
Stride 1	0.00
Stride n	0.00
Stride unknown	2.00
Stride indirect	0.00
Vectorization ratio all	0.00
Vectorization ratio load	NA
Vectorization ratio store	0.00
Vectorization ratio mul	0.00
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	17.50
Vector-efficiency ratio load	NA
Vector-efficiency ratio store	12.50
Vector-efficiency ratio mul	12.50
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	20.83

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	main
Source file and lines	attention_v2.cpp:27-233
Module	attention-gcc-native

The loop is defined in /home/eoseret/llm-attention/attention_v2.cpp:27-33,233.

Analyzed code is defined in /home/eoseret/llm-attention/attention_v2.cpp:27-30,33,233.

Warnings:
Non-innermost loop: analyzing only self part (ignoring child loops).

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 1.25 to 1.00 cycles (1.25x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is not vectorized. Only 17% of vector register length is used (average across all VPU instructions). By vectorizing your loop, you can lower the cost of an iteration from 1.25 to 0.17 cycles (7.27x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant unknown stride: 2 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Conversion instructions

Detected expensive conversion instructions.

Details

FCVT: 1 occurrences►
- /home/eoseret/llm-attention/attention_v2.cpp:33

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 1 FP arithmetical operations:

1: multiply

The binary loop is storing 3 bytes.

Arithmetic intensity

Arithmetic intensity is 0.33 FP operations per loaded or stored byte.

General properties

nb instructions	10
nb uops	10
loop length	40
used w registers	6
used x registers	2
used b registers	0
used h registers	0
used s registers	2
used d registers	1
used q registers	0
used v registers	0
used z registers	0
nb stack references	0

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	1.25 cycles
front end	1.25 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	0.50	0.50	1.25	1.25	1.25	1.25	1.00	1.00	1.00	1.00	0.50	0.50	0.00	0.00	0.00
cycles	0.50	0.50	1.25	1.25	1.25	1.25	1.00	1.00	1.00	1.00	0.50	0.50	0.00	0.00	0.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	1.25
Dispatch	1.25
Data deps.	1.00
Overall L1	1.25

Vectorization ratios

INT

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	0%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

INT+FP

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	0%
mul	0%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

INT

all	16%
load	NA (no load vectorizable/vectorized instructions)
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	18%

all	18%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	12%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	25%

INT+FP

all	17%
load	NA (no load vectorizable/vectorized instructions)
store	12%
mul	12%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	20%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 1.25 cycles. At this rate:

5% of peak store performance is reached (2.40 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 1.25 to 1.00 cycles (1.25x speedup).

ASM code

In the binary file, the address of the loop is: 410ea4

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
MOVI D21, #0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	2	0.25	scal (25.0%)
ORR W10, WZR, W13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	scal (12.5%)
MOVZ W0, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
FCVT S21, D21	1	0	0	0	0	0	0	0.50	0	0.50	0	0	0	3	0.50	scal (25.0%)
ADD W0, W13, W11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
ADD W13, W13, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
FMUL S21, S21, S15	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	scal (12.5%)
STR S21, [X28, X0,LSL #2]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	2	0.50	scal (12.5%)
CMP W5, W13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.33	N/A
B.HI 410ea4 <main+0xce4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Function	main
Source file and lines	attention_v2.cpp:27-233
Module	attention-gcc-native

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 1.25 to 1.00 cycles (1.25x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant unknown stride: 2 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Conversion instructions

Detected expensive conversion instructions.

Details

FCVT: 1 occurrences►
- /home/eoseret/llm-attention/attention_v2.cpp:33

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 1 FP arithmetical operations:

1: multiply

The binary loop is storing 3 bytes.

Arithmetic intensity

Arithmetic intensity is 0.33 FP operations per loaded or stored byte.

General properties

nb instructions	10
nb uops	10
loop length	40
used w registers	6
used x registers	2
used b registers	0
used h registers	0
used s registers	2
used d registers	1
used q registers	0
used v registers	0
used z registers	0
nb stack references	0

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	1.25 cycles
front end	1.25 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	0.50	0.50	1.25	1.25	1.25	1.25	1.00	1.00	1.00	1.00	0.50	0.50	0.00	0.00	0.00
cycles	0.50	0.50	1.25	1.25	1.25	1.25	1.00	1.00	1.00	1.00	0.50	0.50	0.00	0.00	0.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	1.25
Dispatch	1.25
Data deps.	1.00
Overall L1	1.25

Vectorization ratios

INT

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	0%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

INT+FP

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	0%
mul	0%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

INT

all	16%
load	NA (no load vectorizable/vectorized instructions)
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	18%

all	18%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	12%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	25%

INT+FP

all	17%
load	NA (no load vectorizable/vectorized instructions)
store	12%
mul	12%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	20%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 1.25 cycles. At this rate:

5% of peak store performance is reached (2.40 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the loop is: 410ea4

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
MOVI D21, #0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	2	0.25	scal (25.0%)
ORR W10, WZR, W13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	scal (12.5%)
MOVZ W0, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
FCVT S21, D21	1	0	0	0	0	0	0	0.50	0	0.50	0	0	0	3	0.50	scal (25.0%)
ADD W0, W13, W11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
ADD W13, W13, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
FMUL S21, S21, S15	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	scal (12.5%)
STR S21, [X28, X0,LSL #2]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	2	0.50	scal (12.5%)
CMP W5, W13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.33	N/A
B.HI 410ea4 <main+0xce4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

Slow data structures access

Details

Workaround

Conversion instructions

Details

Workaround

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Slow data structures access

Details

Workaround

Conversion instructions

Details

Workaround

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code