OV - attention-gcc-native

	Function: main	Module: attention-gcc-native	Source: attention_v2.cpp:26-332 [...]	Coverage (incl. loops): 89.26% \| (excl. loops): 0.00%

/usr/include/c++/14/bits/stl_algobase.h: 952 - 1146

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952: 	*__first = __tmp;

[...]

1140:     __fill_n_a(_OutputIterator __first, _Size __n, const _Tp& __value,

[...]

1146:       if (__n <= 0)

/usr/include/c++/14/bits/chrono.h: 214 - 716

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214: 	      static_cast<_CR>(__d.count()) / static_cast<_CR>(_CF::den)));

[...]

627: 	  __r += __d.count();

[...]

716: 	return __cd(__cd(__lhs).count() - __cd(__rhs).count());

/usr/include/stdlib.h: 363 - 363

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363:   return (int) strtol (__nptr, (char **) NULL, 10);

/usr/include/c++/14/bits/stl_construct.h: 109 - 119

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109:     _Construct(_Tp* __p, _Args&&... __args)

[...]

119:       ::new((void*)__p) _Tp(std::forward<_Args>(__args)...);

/usr/include/c++/14/bits/stl_uninitialized.h: 668 - 668

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668: 	      __first = std::fill_n(__first, __n - 1, *__val);

/usr/include/c++/14/cmath: 443 - 443

--------------------------------------------------------------------------------

443:   { return __builtin_sqrtf(__x); }

/usr/include/c++/14/bits/char_traits.h: 350 - 427

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350: 	__c1 = __c2;

[...]

427: 	return static_cast<char_type*>(__builtin_memcpy(__s1, __s2, __n));

/usr/include/c++/14/bits/basic_string.h: 194 - 809

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194: 	: allocator_type(__a), _M_p(__dat) { }

[...]

223:       { _M_string_length = __length; }

224:

225:       _GLIBCXX20_CONSTEXPR

226:       pointer

227:       _M_data() const

228:       { return _M_dataplus._M_p; }

[...]

243:       _M_local_data() const

[...]

269: 	if (_M_data() == _M_local_data())

[...]

294:       { _Alloc_traits::deallocate(_M_get_allocator(), _M_data(), __size + 1); }

[...]

809:       { _M_dispose(); }

/usr/include/c++/14/bits/stl_vector.h: 1128 - 1920

--------------------------------------------------------------------------------

1128:       operator[](size_type __n) _GLIBCXX_NOEXCEPT

1129:       {

1130: 	__glibcxx_requires_subscript(__n);

1131: 	return *(this->_M_impl._M_start + __n);

[...]

1919: 	if (__n > _S_max_size(_Tp_alloc_type(__a)))

1920: 	  __throw_length_error(

/usr/include/c++/14/bits/random.h: 248 - 1782

--------------------------------------------------------------------------------

248: 	    __res %= __m;

[...]

1760:     random_device() { _M_init("default"); }

[...]

1766:     { _M_fini(); }

[...]

1782:     { return this->_M_getval(); }

/home/eoseret/llm-attention/attention_v2.cpp: 26 - 332

--------------------------------------------------------------------------------

26:    for (unsigned int i = 0; i < M; ++i) {

27:       for (unsigned int j = 0; j < N; ++j) {  //vectorized

28:          double sum = 0.0;

29: #pragma clang loop vectorize(enable)

30:          for (unsigned int k = 0; k < K; ++k) { //vectorized

31:             sum += (double)A[i * K + k] * (double)B[k * N + j];

32:          }

33:          C[i * N + j] = alpha * static_cast<float>(sum);

[...]

97: {

98:    if (argc < 4) {

99:       std::cerr << "Usage: " << argv[0] << " <context_size> <dim> <rept>\n";

100:       return 1;

[...]

107:    if (context_size <= 0 || dim <= 0) {

108:       std::cerr << "Both context_size and dim must be positive integers.\n";

109:       return 1;

[...]

129:       x = std::chrono::microseconds{0};

130:    }

131: #endif

132:

133:    size_t elemsX  = static_cast<size_t>(context_size) * dim;

134:    size_t elemsW  = static_cast<size_t>(dim) * dim;

135:    size_t elemsS  = static_cast<size_t>(context_size) * context_size;

[...]

144:    for (size_t r = 0; r < rept; r++) {

[...]

160:       std::mt19937 rng(rd());

161:       std::uniform_real_distribution<float> dist(0.0f, 1.0f);

162:

163:       for (size_t i = 0; i < elemsX; ++i) h_X[i] = dist(rng);

164:       for (size_t i = 0; i < elemsW; ++i) {

165:          h_WQ[i] = dist(rng);

166:          h_WK[i] = dist(rng);

167:          h_WV[i] = dist(rng);

[...]

175:       start = std::chrono::steady_clock::now();

176: #endif

177:

178:       MatMul(h_X.data(), h_WQ.data(), h_Q.data(), context_size, dim, dim);

[...]

185:       end = std::chrono::steady_clock::now();

[...]

194:       start = std::chrono::steady_clock::now();

[...]

204:       end = std::chrono::steady_clock::now();

[...]

213:       start = std::chrono::steady_clock::now();

[...]

223:       end = std::chrono::steady_clock::now();

224:       elapsed[2] += std::chrono::duration_cast<std::chrono::microseconds>(end - start);

225: #endif

226:       float scale = 1.0f / std::sqrt(static_cast<float>(dim));

[...]

233:       start = std::chrono::steady_clock::now();

234: #endif

235:

236:       for (int i = 0; i < context_size; ++i)

237:          for (int j = 0; j < dim; ++j)// vectorized

238:             h_KT[j * context_size + i] = h_K[i * dim + j];

[...]

245:       end = std::chrono::steady_clock::now();

[...]

254:       start = std::chrono::steady_clock::now();

[...]

264:       end = std::chrono::steady_clock::now();

[...]

273:       start = std::chrono::steady_clock::now();

274: #endif

275:

276:       softmax(h_S.data(), h_D.data(), h_P.data(), context_size);

[...]

283:       end = std::chrono::steady_clock::now();

[...]

292:       start = std::chrono::steady_clock::now();

[...]

302:       end = std::chrono::steady_clock::now();

303:       elapsed[6] += std::chrono::duration_cast<std::chrono::microseconds>(end - start);

304: #endif

305:

306:       if (r == rept - 1) {

307:          bool softmax_ok = ValidateSoftmax(h_S.data(), h_P.data(), h_D.data(), context_size);

308:

309:          std::cout << "Validation results:\n";

310:          std::cout << "  Softmax (rows sum & D) : " << (softmax_ok ? "OK" : "FAILED") << "\n";

[...]

317:          if (!(softmax_ok && all_finite)) return 1;

318:       }

319:    } // repetition

320:

321: #if !defined (_EXTRAE) && !defined (_RAVETRACE)

322:    std::cout << "Elapsed Matmul_Query: " << elapsed[0].count() << " us\n";

323:    std::cout << "Elapsed Matmul_Key: "   << elapsed[1].count() << " us\n";

324:    std::cout << "Elapsed Matmul_Value: " << elapsed[2].count() << " us\n";

325:    std::cout << "Elapsed Transpose: "    << elapsed[3].count() << " us\n";

326:    std::cout << "Elapsed Matmul_QKt: "   << elapsed[4].count() << " us\n";

327:    std::cout << "Elapsed Softmax: "      << elapsed[5].count() << " us\n";

328:    std::cout << "Elapsed Matmul_Output: "<< elapsed[6].count() << " us\n";

329: #endif

330:

331:    return 0;

332: }

/usr/include/c++/14/bits/new_allocator.h: 104 - 172

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104:       ~__new_allocator() _GLIBCXX_USE_NOEXCEPT { }

[...]

126:       allocate(size_type __n, const void* = static_cast<const void*>(0))

[...]

151: 	return static_cast<_Tp*>(_GLIBCXX_OPERATOR_NEW(__n * sizeof(_Tp)));

152:       }

153:

154:       // __p is not permitted to be a null pointer.

155:       void

156:       deallocate(_Tp* __p, size_type __n __attribute__ ((__unused__)))

[...]

172: 	_GLIBCXX_OPERATOR_DELETE(_GLIBCXX_SIZED_DEALLOC(__p, __n));

/usr/include/c++/14/bits/basic_string.tcc: 242 - 242

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242: 	  ~_Guard() { if (_M_guarded) _M_guarded->_M_dispose(); }

/usr/include/c++/14/bits/random.tcc: 326 - 3374

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326:     mersenne_twister_engine<_UIntType, __w, __n, __m, __r, __a, __u, __d,

327: 			    __s, __b, __t, __c, __l, __f>::

328:     seed(result_type __sd)

329:     {

330:       _M_x[0] = __detail::__mod<_UIntType,

331: 	__detail::_Shift<_UIntType, __w>::__value>(__sd);

332:

333:       for (size_t __i = 1; __i < state_size; ++__i)

334: 	{

335: 	  _UIntType __x = _M_x[__i - 1];

336: 	  __x ^= __x >> (__w - 2);

337: 	  __x *= __f;

338: 	  __x += __detail::__mod<_UIntType, __n>(__i);

339: 	  _M_x[__i] = __detail::__mod<_UIntType,

340: 	    __detail::_Shift<_UIntType, __w>::__value>(__x);

341: 	}

342:       _M_p = state_size;

[...]

458:       if (_M_p >= state_size)

459: 	_M_gen_rand();

460:

461:       // Calculate o(x(i)).

462:       result_type __z = _M_x[_M_p++];

463:       __z ^= (__z >> __u) & __d;

464:       __z ^= (__z << __s) & __b;

465:       __z ^= (__z << __t) & __c;

466:       __z ^= (__z >> __l);

[...]

3367: 	  __sum += _RealType(__urng() - __urng.min()) * __tmp;

3368: 	  __tmp *= __r;

3369: 	}

3370:       __ret = __sum / __tmp;

3371:       if (__builtin_expect(__ret >= _RealType(1), 0))

3372: 	{

3373: #if _GLIBCXX_USE_C99_MATH_FUNCS

3374: 	  __ret = std::nextafter(_RealType(1), _RealType(0));

/usr/include/c++/14/ostream: 175 - 673

--------------------------------------------------------------------------------

175:       { return _M_insert(__n); }

[...]

673: 	__ostream_insert(__out, __s,

0x4101c0 MOVZ	X12, #10400

0x4101c4 SUB	SP, SP, X12,UXTX

0x4101c8 STP	X29, X30, [SP]

0x4101cc ADD	X29, SP, #0

0x4101d0 STP	X19, X20, [SP, #16]

0x4101d4 STP	X21, X22, [SP, #32]

0x4101d8 ORR	X21, XZR, X1

0x4101dc CMP	W0, #3

0x4101e0 B.LE	411624

0x4101e4 MOVZ	W2, #10

0x4101e8 MOVZ	X1, #0

0x4101ec STP	D14, D15, [SP, #112]

0x4101f0 LDR	X0, [X21, #8]

0x4101f4 BL	410040

0x4101f8 ORR	X20, XZR, X0

0x4101fc LDR	X0, [X21, #16]

0x410200 MOVZ	W2, #10

0x410204 MOVZ	X1, #0

0x410208 STR	W20, [SP, #212]

0x41020c BL	410040

0x410210 FMOV	S14, W0

0x410214 ORR	X19, XZR, X0

0x410218 MOVZ	W2, #10

0x41021c LDR	X0, [X21, #24]

0x410220 MOVZ	X1, #0

0x410224 BL	410040

0x410228 CMP	W20, #0

0x41022c STR	W0, [SP, #304]

0x410230 CCMP	W19, #0, #4, #12

0x410234 B.LE	411660

0x410238 SBFM	X2, X0, #0, #31

0x41023c MOVI	V31.4S, #0

0x410240 SBFM	X1, X19, #0, #31

0x410244 STR	XZR, [SP, #392]

0x410248 SBFM	X6, X20, #0, #31

0x41024c STR	X2, [SP, #312]

0x410250 UMULL	X2, W19, W19

0x410254 STR	X1, [SP, #296]

0x410258 UMULL	X1, W20, W19

0x41025c STR	X2, [SP, #136]

0x410260 UMULL	X2, W20, W20

0x410264 STR	X2, [SP, #216]

0x410268 ADD	X2, SP, #512

0x41026c STUR	Q31, [X2, #344]

0x410270 STUR	Q31, [X2, #360]

0x410274 STUR	Q31, [X2, #376]

0x410278 CBZ	W0, 4114dc

0x41027c MOVN	X0, #57344

0x410280 STP	X23, X24, [SP, #48]

0x410284 STP	X25, X26, [SP, #64]

0x410288 STP	X27, X28, [SP, #80]

0x41028c STP	D12, D13, [SP, #96]

0x410290 CMP	X1, X0

0x410294 B.HI	4117d0

0x410298 ORR	W5, WZR, W20

0x41029c UBFM	X0, X1, #62, #61

0x4102a0 STR	W19, [SP, #200]

0x4102a4 SUB	X20, X1, #1

0x4102a8 UMULL	X1, W19, W19

0x4102ac UBFM	X9, X6, #61, #31

0x4102b0 MOVZ	W7, #12

0x4102b4 UBFM	X8, X6, #60, #31

0x4102b8 STR	X0, [SP, #144]

0x4102bc STR	W5, [SP, #240]

0x4102c0 UBFM	X1, X1, #62, #61

0x4102c4 UMULL	X7, W6, W7

0x4102c8 STP	X6, X8, [SP, #184]

0x4102cc STP	X1, X9, [SP, #160]

0x4102d0 LDR	X1, [SP, #216]

0x4102d4 STP	X20, X7, [SP, #224]

0x4102d8 UBFM	X1, X1, #62, #61

0x4102dc STR	X1, [SP, #152]

0x4102e0 UBFM	X1, X6, #62, #31

0x4102e4 STR	X1, [SP, #176]

0x4102e8 SBFM	X1, X19, #0, #31

0x4102ec UBFM	X1, X1, #62, #31

0x4102f0 STR	X1, [SP, #320]

0x4102f4 SUB	W1, W19, #1

0x4102f8 STR	W1, [SP, #308]

0x4102fc BL	4100b0

0x410300 LDR	W4, [SP, #200]

0x410304 ORR	X19, XZR, X0

0x410308 STR	WZR, [X0]

0x41030c STR	XZR, [SP, #200]

0x410310 LDR	X9, [SP, #168]

0x410314 LDP	X6, X8, [SP, #184]

0x410318 LDR	X7, [SP, #232]

0x41031c LDR	W5, [SP, #240]

0x410320 CBZ	X20, 410360

(20) 0x410324 MOVZ	W1, #0

(20) 0x410328 STR	X6, [SP, #168]

(20) 0x41032c LDR	X0, [SP, #144]

(20) 0x410330 STR	W5, [SP, #184]

(20) 0x410334 STR	X8, [SP, #192]

(20) 0x410338 STR	W4, [SP, #232]

(20) 0x41033c STP	X7, X9, [SP, #240]

(20) 0x410340 SUB	X2, X0, #4

(20) 0x410344 ADD	X0, X19, #4

(20) 0x410348 BL	410060

(20) 0x41034c LDR	X6, [SP, #168]

(20) 0x410350 LDP	X7, X9, [SP, #240]

(20) 0x410354 LDR	X8, [SP, #192]

(20) 0x410358 LDR	W5, [SP, #184]

(20) 0x41035c LDR	W4, [SP, #232]

(20) 0x410360 MOVN	X0, #57344

(20) 0x410364 LDR	X1, [SP, #136]

(20) 0x410368 CMP	X1, X0

(20) 0x41036c B.HI	4117bc

(20) 0x410370 MOVZ	X13, #5400

(20) 0x410374 ADD	X0, SP, X13,UXTX

(20) 0x410378 ADD	X0, X0, #16

(20) 0x41037c STR	X0, [SP, #240]

  (21) 0x410380 LDR	X0, [SP, #160]

  (21) 0x410384 STR	X6, [SP, #168]

  (21) 0x410388 STR	W5, [SP, #184]

  (21) 0x41038c STR	X8, [SP, #192]

  (21) 0x410390 STR	W4, [SP, #232]

  (21) 0x410394 STP	X7, X9, [SP, #248]

  (21) 0x410398 BL	4100b0

  (21) 0x41039c ORR	X25, XZR, X0

  (21) 0x4103a0 STR	WZR, [X0]

  (21) 0x4103a4 LDR	X0, [SP, #136]

  (21) 0x4103a8 LDP	X7, X9, [SP, #248]

  (21) 0x4103ac LDR	X6, [SP, #168]

  (21) 0x4103b0 LDR	X8, [SP, #192]

  (21) 0x4103b4 LDR	W5, [SP, #184]

  (21) 0x4103b8 LDR	W4, [SP, #232]

  (21) 0x4103bc CMP	X0, #1

  (21) 0x4103c0 B.EQ	41147c

  (21) 0x4103c4 MOVZ	W1, #0

  (21) 0x4103c8 ADD	X0, X25, #4

  (21) 0x4103cc STR	X6, [SP, #168]

  (21) 0x4103d0 LDR	X21, [SP, #160]

  (21) 0x4103d4 STR	W5, [SP, #184]

  (21) 0x4103d8 STR	X8, [SP, #192]

  (21) 0x4103dc STR	W4, [SP, #232]

  (21) 0x4103e0 STP	X7, X9, [SP, #248]

  (21) 0x4103e4 SUB	X20, X21, #4

  (21) 0x4103e8 ORR	X2, XZR, X20

  (21) 0x4103ec BL	410060

  (21) 0x4103f0 ORR	X0, XZR, X21

  (21) 0x4103f4 BL	4100b0

  (21) 0x4103f8 ORR	X23, XZR, X0

  (21) 0x4103fc ORR	X2, XZR, X20

  (21) 0x410400 STR	WZR, [X0], #4

  (21) 0x410404 MOVZ	W1, #0

  (21) 0x410408 BL	410060

  (21) 0x41040c ORR	X0, XZR, X21

  (21) 0x410410 BL	4100b0

  (21) 0x410414 ORR	X24, XZR, X0

  (21) 0x410418 ORR	X2, XZR, X20

  (21) 0x41041c STR	WZR, [X0], #4

  (21) 0x410420 MOVZ	W1, #0

  (21) 0x410424 BL	410060

  (21) 0x410428 LDR	X6, [SP, #168]

  (21) 0x41042c LDP	X7, X9, [SP, #248]

  (21) 0x410430 LDR	X8, [SP, #192]

  (21) 0x410434 LDR	W5, [SP, #184]

  (21) 0x410438 LDR	W4, [SP, #232]

  (21) 0x41043c STR	X6, [SP, #168]

  (21) 0x410440 LDR	X0, [SP, #144]

  (21) 0x410444 STR	W5, [SP, #184]

  (21) 0x410448 STR	X8, [SP, #232]

  (21) 0x41044c STR	W4, [SP, #248]

  (21) 0x410450 STP	X7, X9, [SP, #256]

  (21) 0x410454 BL	4100b0

  (21) 0x410458 STR	WZR, [X0]

  (21) 0x41045c STR	X0, [SP, #192]

  (21) 0x410460 LDR	X0, [SP, #224]

  (21) 0x410464 LDP	X7, X9, [SP, #256]

  (21) 0x410468 LDR	X6, [SP, #168]

  (21) 0x41046c LDR	X8, [SP, #232]

  (21) 0x410470 LDR	W5, [SP, #184]

  (21) 0x410474 LDR	W4, [SP, #248]

  (21) 0x410478 CBZ	X0, 41140c

  (21) 0x41047c MOVZ	W1, #0

  (21) 0x410480 STR	X6, [SP, #168]

  (21) 0x410484 LDR	X21, [SP, #144]

  (21) 0x410488 STR	W5, [SP, #184]

  (21) 0x41048c LDR	X0, [SP, #192]

  (21) 0x410490 STR	X8, [SP, #232]

  (21) 0x410494 STR	W4, [SP, #248]

  (21) 0x410498 SUB	X26, X21, #4

  (21) 0x41049c STP	X7, X9, [SP, #256]

  (21) 0x4104a0 ORR	X2, XZR, X26

  (21) 0x4104a4 ADD	X0, X0, #4

  (21) 0x4104a8 BL	410060

  (21) 0x4104ac ORR	X0, XZR, X21

  (21) 0x4104b0 BL	4100b0

  (21) 0x4104b4 ORR	X20, XZR, X0

  (21) 0x4104b8 ORR	X2, XZR, X26

  (21) 0x4104bc STR	WZR, [X0], #4

  (21) 0x4104c0 MOVZ	W1, #0

  (21) 0x4104c4 BL	410060

  (21) 0x4104c8 ORR	X0, XZR, X21

  (21) 0x4104cc BL	4100b0

  (21) 0x4104d0 ORR	X27, XZR, X0

  (21) 0x4104d4 ORR	X2, XZR, X26

  (21) 0x4104d8 STR	WZR, [X0], #4

  (21) 0x4104dc MOVZ	W1, #0

  (21) 0x4104e0 BL	410060

  (21) 0x4104e4 ORR	X0, XZR, X21

  (21) 0x4104e8 BL	4100b0

  (21) 0x4104ec LDR	W5, [SP, #184]

  (21) 0x4104f0 ORR	X22, XZR, X0

  (21) 0x4104f4 ORR	X2, XZR, X26

  (21) 0x4104f8 MOVZ	W1, #0

  (21) 0x4104fc STR	WZR, [X0], #4

  (21) 0x410500 LDR	W4, [SP, #248]

  (21) 0x410504 STR	W5, [SP, #184]

  (21) 0x410508 STR	W4, [SP, #248]

  (21) 0x41050c BL	410060

  (21) 0x410510 LDR	X0, [SP, #144]

  (21) 0x410514 BL	4100b0

  (21) 0x410518 LDR	W5, [SP, #184]

  (21) 0x41051c ORR	X21, XZR, X0

  (21) 0x410520 ORR	X2, XZR, X26

  (21) 0x410524 MOVZ	W1, #0

  (21) 0x410528 STR	WZR, [X0], #4

  (21) 0x41052c LDR	W4, [SP, #248]

  (21) 0x410530 STR	W5, [SP, #184]

  (21) 0x410534 STR	W4, [SP, #248]

  (21) 0x410538 BL	410060

  (21) 0x41053c LDR	X6, [SP, #168]

  (21) 0x410540 LDP	X7, X9, [SP, #256]

  (21) 0x410544 LDR	X8, [SP, #232]

  (21) 0x410548 LDR	W5, [SP, #184]

  (21) 0x41054c LDR	W4, [SP, #248]

  (21) 0x410550 MOVN	X0, #57344

  (21) 0x410554 LDR	X1, [SP, #216]

  (21) 0x410558 CMP	X1, X0

  (21) 0x41055c B.HI	41175c

  (21) 0x410560 LDR	X0, [SP, #152]

  (21) 0x410564 STR	X6, [SP, #168]

  (21) 0x410568 STR	W5, [SP, #184]

  (21) 0x41056c STR	X8, [SP, #232]

  (21) 0x410570 STR	W4, [SP, #248]

  (21) 0x410574 STP	X7, X9, [SP, #256]

  (21) 0x410578 BL	4100b0

  (21) 0x41057c ORR	X28, XZR, X0

  (21) 0x410580 STR	WZR, [X0]

  (21) 0x410584 LDR	X0, [SP, #216]

  (21) 0x410588 LDP	X7, X9, [SP, #256]

  (21) 0x41058c LDR	X6, [SP, #168]

  (21) 0x410590 LDR	X8, [SP, #232]

  (21) 0x410594 LDR	W5, [SP, #184]

  (21) 0x410598 LDR	W4, [SP, #248]

  (21) 0x41059c CMP	X0, #1

  (21) 0x4105a0 B.EQ	4113dc

  (21) 0x4105a4 MOVZ	W1, #0

  (21) 0x4105a8 STR	X6, [SP, #168]

  (21) 0x4105ac LDR	X0, [SP, #152]

  (21) 0x4105b0 STR	W5, [SP, #184]

  (21) 0x4105b4 STR	X8, [SP, #232]

  (21) 0x4105b8 STR	W4, [SP, #248]

  (21) 0x4105bc STP	X7, X9, [SP, #256]

  (21) 0x4105c0 SUB	X26, X0, #4

  (21) 0x4105c4 ADD	X0, X28, #4

  (21) 0x4105c8 ORR	X2, XZR, X26

  (21) 0x4105cc BL	410060

  (21) 0x4105d0 LDR	X0, [SP, #152]

  (21) 0x4105d4 BL	4100b0

  (21) 0x4105d8 ORR	X2, XZR, X26

  (21) 0x4105dc MOVZ	W1, #0

  (21) 0x4105e0 ORR	X26, XZR, X0

  (21) 0x4105e4 STR	WZR, [X0], #4

  (21) 0x4105e8 BL	410060

  (21) 0x4105ec LDR	X6, [SP, #168]

  (21) 0x4105f0 LDP	X7, X9, [SP, #256]

  (21) 0x4105f4 LDR	X8, [SP, #232]

  (21) 0x4105f8 LDR	W5, [SP, #184]

  (21) 0x4105fc LDR	W4, [SP, #248]

  (21) 0x410600 STR	X6, [SP, #168]

  (21) 0x410604 LDR	X0, [SP, #176]

  (21) 0x410608 STR	W5, [SP, #232]

  (21) 0x41060c STR	X8, [SP, #248]

  (21) 0x410610 STR	W4, [SP, #256]

  (21) 0x410614 STP	X7, X9, [SP, #264]

  (21) 0x410618 BL	4100b0

  (21) 0x41061c LDR	X6, [SP, #168]

  (21) 0x410620 STR	WZR, [X0]

  (21) 0x410624 STR	X0, [SP, #184]

  (21) 0x410628 LDR	X8, [SP, #248]

  (21) 0x41062c LDP	X7, X9, [SP, #264]

  (21) 0x410630 CMP	X6, #1

  (21) 0x410634 LDR	W5, [SP, #232]

  (21) 0x410638 LDR	W4, [SP, #256]

  (21) 0x41063c B.EQ	410680

  (21) 0x410640 MOVZ	W1, #0

  (21) 0x410644 STR	X6, [SP, #168]

  (21) 0x410648 LDR	X0, [SP, #176]

  (21) 0x41064c STR	W5, [SP, #232]

  (21) 0x410650 STR	X8, [SP, #248]

  (21) 0x410654 STR	W4, [SP, #256]

  (21) 0x410658 STP	X7, X9, [SP, #264]

  (21) 0x41065c SUB	X2, X0, #4

  (21) 0x410660 LDR	X0, [SP, #184]

  (21) 0x410664 ADD	X0, X0, #4

  (21) 0x410668 BL	410060

  (21) 0x41066c LDR	X6, [SP, #168]

  (21) 0x410670 LDP	X7, X9, [SP, #264]

  (21) 0x410674 LDR	X8, [SP, #248]

  (21) 0x410678 LDR	W5, [SP, #232]

  (21) 0x41067c LDR	W4, [SP, #256]

  (21) 0x410680 STR	W4, [SP, #256]

  (21) 0x410684 ADRP	X1,

  (21) 0x410688 MOVZ	X11, #4304

  (21) 0x41068c LDR	X4, [SP, #240]

  (21) 0x410690 ADD	X1, X1, #512

  (21) 0x410694 ADD	X2, SP, X11,UXTX

  (21) 0x410698 STP	X7, X9, [SP, #264]

  (21) 0x41069c MOVZ	X0, #7

  (21) 0x4106a0 MOVZ	X12, #5400

  (21) 0x4106a4 LDR	W3, [X1]

  (21) 0x4106a8 STR	X4, [SP, #5400]

  (21) 0x4106ac STRB	WZR, [X2, #1119]

  (21) 0x4106b0 LDUR	W2, [X1, #3]

  (21) 0x4106b4 ADD	X1, SP, X12,UXTX

  (21) 0x4106b8 STR	X0, [SP, #5408]

  (21) 0x4106bc ADD	X0, SP, #400

  (21) 0x4106c0 STR	W3, [X4]

  (21) 0x4106c4 STR	X6, [SP, #168]

  (21) 0x4106c8 STR	W5, [SP, #232]

  (21) 0x4106cc STUR	W2, [X4, #3]

  (21) 0x4106d0 STR	X8, [SP, #248]

  (21) 0x4106d4 BL	410150

  (21) 0x4106d8 LDR	X0, [SP, #5400]

  (21) 0x4106dc LDP	X1, X8, [SP, #240]

  (21) 0x4106e0 LDP	X7, X9, [SP, #264]

  (21) 0x4106e4 LDR	X6, [SP, #168]

  (21) 0x4106e8 LDR	W5, [SP, #232]

  (21) 0x4106ec LDR	W4, [SP, #256]

  (21) 0x4106f0 CMP	X0, X1

  (21) 0x4106f4 B.EQ	410720

  (21) 0x4106f8 STR	W5, [SP, #232]

  (21) 0x4106fc LDR	X1, [SP, #5416]

  (21) 0x410700 STR	W4, [SP, #256]

  (21) 0x410704 ADD	X1, X1, #1

  (21) 0x410708 BL	4100c0

  (21) 0x41070c LDR	X6, [SP, #168]

  (21) 0x410710 LDP	X7, X9, [SP, #264]

  (21) 0x410714 LDR	X8, [SP, #248]

  (21) 0x410718 LDR	W5, [SP, #232]

  (21) 0x41071c LDR	W4, [SP, #256]

  (21) 0x410720 ADD	X0, SP, #400

  (21) 0x410724 STR	X6, [SP, #168]

  (21) 0x410728 STR	W5, [SP, #232]

  (21) 0x41072c STR	X8, [SP, #248]

  (21) 0x410730 STR	W4, [SP, #256]

  (21) 0x410734 STP	X7, X9, [SP, #264]

  (21) 0x410738 BL	410100

  (21) 0x41073c LDR	X6, [SP, #168]

  (21) 0x410740 MOVZ	X10, #5400

  (21) 0x410744 MOVZ	W3, #35173

  (21) 0x410748 LDP	X7, X9, [SP, #264]

  (21) 0x41074c ADD	X1, SP, X10,UXTX

  (21) 0x410750 ORR	W0, WZR, W0

  (21) 0x410754 ADD	X2, X1, #8

  (21) 0x410758 MOVK	W3, #27655

  (21) 0x41075c MOVZ	X1, #1

  (21) 0x410760 STR	X0, [SP, #5400]

  (21) 0x410764 LDR	X8, [SP, #248]

  (21) 0x410768 LDR	W5, [SP, #232]

  (21) 0x41076c LDR	W4, [SP, #256]

    (1) 0x410770 EOR	X0, X0, X0,LSR #30

    (1) 0x410774 MADD	W0, W3, W0, W1

    (1) 0x410778 ADD	X1, X1, #1

    (1) 0x41077c STR	X0, [X2], #8

    (1) 0x410780 CMP	X1, #624

    (1) 0x410784 B.NE	410770

  (21) 0x410788 LDR	X3, [SP, #144]

  (21) 0x41078c MOVZ	W0, #12160

  (21) 0x410790 FMOV	S13, #1.0000000

  (21) 0x410794 STR	X6, [SP, #168]

  (21) 0x410798 MOVZ	X10, #61382

  (21) 0x41079c STR	W5, [SP, #232]

  (21) 0x4107a0 STP	X8, X19, [SP, #248]

  (21) 0x4107a4 ADD	X11, X3, X19

  (21) 0x4107a8 STR	X20, [SP, #264]

  (21) 0x4107ac ORR	X20, XZR, X11

  (21) 0x4107b0 STR	W4, [SP, #272]

  (21) 0x4107b4 STP	X7, X9, [SP, #280]

  (21) 0x4107b8 STR	X1, [SP, #10392]

  (21) 0x4107bc FMOV	S15, W0

  (21) 0x4107c0 CMP	X1, #623

  (21) 0x4107c4 B.HI	410828

    (2) 0x4107c8 MOVZ	X7, #5400

    (2) 0x4107cc ADD	X3, X1, #1

    (2) 0x4107d0 ADD	X0, SP, X7,UXTX

    (2) 0x4107d4 LDR	X0, [X0, X1,LSL #3]

    (2) 0x4107d8 STR	X3, [SP, #10392]

    (2) 0x4107dc UBFM	X1, X0, #11, #42

    (2) 0x4107e0 EOR	X0, X0, X1

    (2) 0x4107e4 MOVZ	X1, #22144

    (2) 0x4107e8 MOVK	X1, #40236

    (2) 0x4107ec AND	X1, X1, X0,LSL #7

    (2) 0x4107f0 EOR	X0, X0, X1

    (2) 0x4107f4 AND	X1, X10, X0,LSL #15

    (2) 0x4107f8 EOR	X0, X0, X1

    (2) 0x4107fc EOR	X0, X0, X0,LSR #18

    (2) 0x410800 UCVTF	S31, X0

    (2) 0x410804 FMUL	S31, S31, S15

    (2) 0x410808 FCMPE	S31, S13

    (2) 0x41080c B.GE	410840

    (2) 0x410810 STR	S31, [X19], #4

    (2) 0x410814 CMP	X19, X20

    (2) 0x410818 B.EQ	410850

    (2) 0x41081c ORR	X1, XZR, X3

    (2) 0x410820 CMP	X1, #623

    (2) 0x410824 B.LS	4107c8

    (3) 0x410828 MOVZ	X8, #5400

    (3) 0x41082c ADD	X0, SP, X8,UXTX

    (3) 0x410830 BL	411f40

  (21) 0x410834 LDR	X1, [SP, #10392]

  (21) 0x410838 MOVZ	X10, #61382

  (21) 0x41083c B	4107c8

    (2) 0x410840 MOVN	W0, #49280

    (2) 0x410844 STR	W0, [X19], #4

    (2) 0x410848 CMP	X20, X19

    (2) 0x41084c B.NE	41081c

  (21) 0x410850 LDR	X6, [SP, #168]

  (21) 0x410854 MOVZ	W0, #12160

  (21) 0x410858 MOVN	W10, #49280

  (21) 0x41085c LDP	X7, X9, [SP, #280]

  (21) 0x410860 MOVZ	X1, #0

  (21) 0x410864 FMOV	S13, #1.0000000

  (21) 0x410868 MOVZ	X2, #61382

  (21) 0x41086c LDP	X8, X19, [SP, #248]

  (21) 0x410870 FMOV	S15, W0

  (21) 0x410874 LDR	X20, [SP, #264]

  (21) 0x410878 FMOV	S12, W10

  (21) 0x41087c LDR	W4, [SP, #272]

  (21) 0x410880 STR	X6, [SP, #168]

  (21) 0x410884 LDR	W5, [SP, #232]

  (21) 0x410888 STP	X8, X19, [SP, #248]

  (21) 0x41088c ORR	X19, XZR, X25

  (21) 0x410890 ORR	X25, XZR, X9

  (21) 0x410894 STP	X20, X22, [SP, #264]

  (21) 0x410898 ORR	X20, XZR, X24

  (21) 0x41089c ORR	X22, XZR, X1

  (21) 0x4108a0 ORR	X24, XZR, X7

  (21) 0x4108a4 STR	W5, [SP, #232]

  (21) 0x4108a8 STR	X21, [SP, #280]

  (21) 0x4108ac ORR	X21, XZR, X23

  (21) 0x4108b0 ORR	W23, WZR, W4

  (21) 0x4108b4 B	4109bc

    (24) 0x4108b8 MOVZ	X5, #5400

    (24) 0x4108bc ADD	X8, X3, #1

    (24) 0x4108c0 ADD	X0, SP, X5,UXTX

    (24) 0x4108c4 MOVZ	X1, #22144

    (24) 0x4108c8 LDR	X0, [X0, X3,LSL #3]

    (24) 0x4108cc MOVK	X1, #40236

    (24) 0x4108d0 STR	X8, [SP, #10392]

    (24) 0x4108d4 UBFM	X3, X0, #11, #42

    (24) 0x4108d8 EOR	X0, X0, X3

    (24) 0x4108dc AND	X3, X1, X0,LSL #7

    (24) 0x4108e0 EOR	X0, X0, X3

    (24) 0x4108e4 AND	X3, X2, X0,LSL #15

    (24) 0x4108e8 EOR	X0, X0, X3

    (24) 0x4108ec EOR	X0, X0, X0,LSR #18

    (24) 0x4108f0 UCVTF	S31, X0

    (24) 0x4108f4 FMUL	S31, S31, S15

    (24) 0x4108f8 FCMPE	S31, S13

    (24) 0x4108fc FCSEL	S31, S31, S12, #4

    (24) 0x410900 STR	S31, [X19, X22,LSL #2]

    (24) 0x410904 CMP	X8, #623

    (24) 0x410908 B.HI	4109f4

    (24) 0x41090c MOVZ	X3, #5400

    (24) 0x410910 MOVZ	X1, #22144

    (24) 0x410914 ADD	X0, SP, X3,UXTX

    (24) 0x410918 MOVK	X1, #40236

    (24) 0x41091c LDR	X0, [X0, X8,LSL #3]

    (24) 0x410920 ADD	X7, X8, #1

    (24) 0x410924 STR	X7, [SP, #10392]

    (24) 0x410928 UBFM	X3, X0, #11, #42

    (24) 0x41092c EOR	X0, X0, X3

    (24) 0x410930 AND	X3, X1, X0,LSL #7

    (24) 0x410934 EOR	X0, X0, X3

    (24) 0x410938 AND	X3, X2, X0,LSL #15

    (24) 0x41093c EOR	X0, X0, X3

    (24) 0x410940 EOR	X0, X0, X0,LSR #18

    (24) 0x410944 UCVTF	S31, X0

    (24) 0x410948 FMUL	S31, S31, S15

    (24) 0x41094c FCMPE	S31, S13

    (24) 0x410950 FCSEL	S31, S31, S12, #4

    (24) 0x410954 STR	S31, [X21, X22,LSL #2]

    (24) 0x410958 CMP	X7, #623

    (24) 0x41095c B.HI	4109dc

    (24) 0x410960 MOVZ	X0, #5400

    (24) 0x410964 ADD	X3, X7, #1

    (24) 0x410968 ADD	X0, SP, X0,UXTX

    (24) 0x41096c MOVZ	X1, #22144

    (24) 0x410970 LDR	X0, [X0, X7,LSL #3]

    (24) 0x410974 MOVK	X1, #40236

    (24) 0x410978 STR	X3, [SP, #10392]

    (24) 0x41097c UBFM	X7, X0, #11, #42

    (24) 0x410980 EOR	X0, X0, X7

    (24) 0x410984 AND	X7, X1, X0,LSL #7

    (24) 0x410988 EOR	X0, X0, X7

    (24) 0x41098c AND	X7, X2, X0,LSL #15

    (24) 0x410990 EOR	X0, X0, X7

    (24) 0x410994 EOR	X0, X0, X0,LSR #18

    (24) 0x410998 UCVTF	S31, X0

    (24) 0x41099c FMUL	S31, S31, S15

    (24) 0x4109a0 FCMPE	S31, S13

    (24) 0x4109a4 B.GE	4111e4

    (24) 0x4109a8 LDR	X0, [SP, #136]

    (24) 0x4109ac STR	S31, [X20, X22,LSL #2]

    (24) 0x4109b0 ADD	X22, X22, #1

    (24) 0x4109b4 CMP	X22, X0

    (24) 0x4109b8 B.CS	410a0c

    (24) 0x4109bc CMP	X3, #623

    (24) 0x4109c0 B.LS	4108b8

    (24) 0x4109c4 MOVZ	X6, #5400

    (24) 0x4109c8 ADD	X0, SP, X6,UXTX

    (24) 0x4109cc BL	411f40

    (24) 0x4109d0 LDR	X3, [SP, #10392]

    (24) 0x4109d4 MOVZ	X2, #61382

    (24) 0x4109d8 B	4108b8

    (24) 0x4109dc MOVZ	X1, #5400

    (24) 0x4109e0 ADD	X0, SP, X1,UXTX

    (24) 0x4109e4 BL	411f40

    (24) 0x4109e8 LDR	X7, [SP, #10392]

    (24) 0x4109ec MOVZ	X2, #61382

    (24) 0x4109f0 B	410960

    (24) 0x4109f4 MOVZ	X4, #5400

    (24) 0x4109f8 ADD	X0, SP, X4,UXTX

    (24) 0x4109fc BL	411f40

    (24) 0x410a00 LDR	X8, [SP, #10392]

    (24) 0x410a04 MOVZ	X2, #61382

    (24) 0x410a08 B	41090c

  (21) 0x410a0c LDR	X6, [SP, #168]

  (21) 0x410a10 ORR	X9, XZR, X25

  (21) 0x410a14 ORR	X25, XZR, X19

  (21) 0x410a18 LDP	X8, X19, [SP, #248]

  (21) 0x410a1c ORR	W4, WZR, W23

  (21) 0x410a20 ORR	X7, XZR, X24

  (21) 0x410a24 ORR	X23, XZR, X21

  (21) 0x410a28 ORR	X24, XZR, X20

  (21) 0x410a2c LDP	X20, X22, [SP, #264]

  (21) 0x410a30 STR	X6, [SP, #168]

  (21) 0x410a34 LDR	W5, [SP, #232]

  (21) 0x410a38 STR	X8, [SP, #248]

  (21) 0x410a3c LDR	X21, [SP, #280]

  (21) 0x410a40 STR	W4, [SP, #256]

  (21) 0x410a44 STP	X7, X9, [SP, #264]

  (21) 0x410a48 STR	W5, [SP, #232]

  (21) 0x410a4c BL	4100f0

  (21) 0x410a50 LDR	X6, [SP, #168]

  (21) 0x410a54 MOVZ	W3, #0

  (21) 0x410a58 MOVZ	W1, #0

  (21) 0x410a5c LDP	X7, X9, [SP, #264]

  (21) 0x410a60 ORR	X2, XZR, X0

  (21) 0x410a64 LDR	X8, [SP, #248]

  (21) 0x410a68 LDR	W5, [SP, #232]

  (21) 0x410a6c LDR	W4, [SP, #256]

    (6) 0x410a70 MOVZ	W12, #0

    (6) 0x410a74 HINT	#0

    (6) 0x410a78 HINT	#0

    (6) 0x410a7c HINT	#0

      (5) 0x410a80 MOVI	D31, #0

      (5) 0x410a84 ORR	W10, WZR, W12

      (5) 0x410a88 MOVZ	W0, #0

        (4) 0x410a8c ADD	W11, W0, W3

        (4) 0x410a90 LDR	S29, [X25, W10,UXTW #2]

        (4) 0x410a94 ADD	W0, W0, #1

        (4) 0x410a98 ADD	W10, W10, W4

        (4) 0x410a9c LDR	S30, [X19, X11,LSL #2]

        (4) 0x410aa0 FCVT	D29, S29

        (4) 0x410aa4 FCVT	D30, S30

        (4) 0x410aa8 FMADD	D31, D30, D29, D31

        (4) 0x410aac CMP	W0, W4

        (4) 0x410ab0 B.CC	410a8c

      (5) 0x410ab4 FCVT	S31, D31

      (5) 0x410ab8 ADD	W0, W12, W3

      (5) 0x410abc ADD	W12, W12, #1

      (5) 0x410ac0 STR	S31, [X20, X0,LSL #2]

      (5) 0x410ac4 CMP	W12, W4

      (5) 0x410ac8 B.CC	410a80

    (6) 0x410acc ADD	W1, W1, #1

    (6) 0x410ad0 ADD	W3, W3, W4

    (6) 0x410ad4 CMP	W5, W1

    (6) 0x410ad8 B.NE	410a70

  (21) 0x410adc STR	X9, [SP, #168]

  (21) 0x410ae0 STR	X7, [SP, #232]

  (21) 0x410ae4 STR	X2, [SP, #248]

  (21) 0x410ae8 STR	W4, [SP, #256]

  (21) 0x410aec STR	X8, [SP, #264]

  (21) 0x410af0 STR	W5, [SP, #272]

  (21) 0x410af4 STR	X6, [SP, #280]

  (21) 0x410af8 BL	4100f0

  (21) 0x410afc LDR	X2, [SP, #248]

  (21) 0x410b00 LDR	X1, [SP, #344]

  (21) 0x410b04 SUB	X0, X0, X2

  (21) 0x410b08 MOVZ	X2, #63439

  (21) 0x410b0c MOVK	X2, #58195

  (21) 0x410b10 MOVK	X2, #39845

  (21) 0x410b14 MOVK	X2, #8388

  (21) 0x410b18 SMULH	X2, X0, X2

  (21) 0x410b1c SBFM	X2, X2, #7, #63

  (21) 0x410b20 SUB	X0, X2, X0,ASR #63

  (21) 0x410b24 ADD	X1, X1, X0

  (21) 0x410b28 STR	X1, [SP, #344]

  (21) 0x410b2c BL	4100f0

  (21) 0x410b30 LDR	X9, [SP, #168]

  (21) 0x410b34 MOVZ	W3, #0

  (21) 0x410b38 MOVZ	W1, #0

  (21) 0x410b3c ORR	X2, XZR, X0

  (21) 0x410b40 LDR	X7, [SP, #232]

  (21) 0x410b44 LDR	X8, [SP, #264]

  (21) 0x410b48 LDR	X6, [SP, #280]

  (21) 0x410b4c LDR	W4, [SP, #256]

  (21) 0x410b50 LDR	W5, [SP, #272]

  (21) 0x410b54 HINT	#0

  (21) 0x410b58 HINT	#0

  (21) 0x410b5c HINT	#0

    (9) 0x410b60 MOVZ	W12, #0

      (8) 0x410b64 MOVI	D28, #0

      (8) 0x410b68 ORR	W10, WZR, W12

      (8) 0x410b6c MOVZ	W0, #0

        (7) 0x410b70 ADD	W11, W0, W3

        (7) 0x410b74 LDR	S26, [X23, W10,UXTW #2]

        (7) 0x410b78 ADD	W0, W0, #1

        (7) 0x410b7c ADD	W10, W10, W4

        (7) 0x410b80 LDR	S27, [X19, X11,LSL #2]

        (7) 0x410b84 FCVT	D26, S26

        (7) 0x410b88 FCVT	D27, S27

        (7) 0x410b8c FMADD	D28, D27, D26, D28

        (7) 0x410b90 CMP	W0, W4

        (7) 0x410b94 B.CC	410b70

      (8) 0x410b98 FCVT	S28, D28

      (8) 0x410b9c ADD	W0, W12, W3

      (8) 0x410ba0 ADD	W12, W12, #1

      (8) 0x410ba4 STR	S28, [X27, X0,LSL #2]

      (8) 0x410ba8 CMP	W12, W4

      (8) 0x410bac B.CC	410b64

    (9) 0x410bb0 ADD	W1, W1, #1

    (9) 0x410bb4 ADD	W3, W3, W4

    (9) 0x410bb8 CMP	W5, W1

    (9) 0x410bbc B.HI	410b60

  (21) 0x410bc0 STR	X9, [SP, #168]

  (21) 0x410bc4 STR	X7, [SP, #232]

  (21) 0x410bc8 STR	X2, [SP, #248]

  (21) 0x410bcc STR	W4, [SP, #256]

  (21) 0x410bd0 STR	X8, [SP, #264]

  (21) 0x410bd4 STR	W5, [SP, #272]

  (21) 0x410bd8 STR	X6, [SP, #280]

  (21) 0x410bdc BL	4100f0

  (21) 0x410be0 LDR	X2, [SP, #248]

  (21) 0x410be4 LDR	X1, [SP, #352]

  (21) 0x410be8 SUB	X0, X0, X2

  (21) 0x410bec MOVZ	X2, #63439

  (21) 0x410bf0 MOVK	X2, #58195

  (21) 0x410bf4 MOVK	X2, #39845

  (21) 0x410bf8 MOVK	X2, #8388

  (21) 0x410bfc SMULH	X2, X0, X2

  (21) 0x410c00 SBFM	X2, X2, #7, #63

  (21) 0x410c04 SUB	X0, X2, X0,ASR #63

  (21) 0x410c08 ADD	X1, X1, X0

  (21) 0x410c0c STR	X1, [SP, #352]

  (21) 0x410c10 BL	4100f0

  (21) 0x410c14 LDR	X9, [SP, #168]

  (21) 0x410c18 MOVZ	W3, #0

  (21) 0x410c1c MOVZ	W1, #0

  (21) 0x410c20 ORR	X2, XZR, X0

  (21) 0x410c24 LDR	X7, [SP, #232]

  (21) 0x410c28 LDR	X8, [SP, #264]

  (21) 0x410c2c LDR	X6, [SP, #280]

  (21) 0x410c30 LDR	W4, [SP, #256]

  (21) 0x410c34 LDR	W5, [SP, #272]

  (21) 0x410c38 HINT	#0

  (21) 0x410c3c HINT	#0

    (12) 0x410c40 MOVZ	W12, #0

      (11) 0x410c44 MOVI	D25, #0

      (11) 0x410c48 ORR	W10, WZR, W12

      (11) 0x410c4c MOVZ	W0, #0

        (10) 0x410c50 ADD	W11, W0, W3

        (10) 0x410c54 LDR	S23, [X24, W10,UXTW #2]

        (10) 0x410c58 ADD	W0, W0, #1

        (10) 0x410c5c ADD	W10, W10, W4

        (10) 0x410c60 LDR	S24, [X19, X11,LSL #2]

        (10) 0x410c64 FCVT	D23, S23

        (10) 0x410c68 FCVT	D24, S24

        (10) 0x410c6c FMADD	D25, D24, D23, D25

        (10) 0x410c70 CMP	W0, W4

        (10) 0x410c74 B.CC	410c50

      (11) 0x410c78 FCVT	S25, D25

      (11) 0x410c7c ADD	W0, W12, W3

      (11) 0x410c80 ADD	W12, W12, #1

      (11) 0x410c84 STR	S25, [X21, X0,LSL #2]

      (11) 0x410c88 CMP	W12, W4

      (11) 0x410c8c B.CC	410c44

    (12) 0x410c90 ADD	W1, W1, #1

    (12) 0x410c94 ADD	W3, W3, W4

    (12) 0x410c98 CMP	W5, W1

    (12) 0x410c9c B.HI	410c40

  (21) 0x410ca0 STR	W4, [SP, #168]

  (21) 0x410ca4 STR	X2, [SP, #232]

  (21) 0x410ca8 STR	X8, [SP, #248]

  (21) 0x410cac STR	W5, [SP, #256]

  (21) 0x410cb0 STR	X6, [SP, #264]

  (21) 0x410cb4 STP	X9, X7, [SP, #280]

  (21) 0x410cb8 BL	4100f0

  (21) 0x410cbc SCVTF	S0, S14

  (21) 0x410cc0 LDR	X2, [SP, #232]

  (21) 0x410cc4 FMOV	S15, #1.0000000

  (21) 0x410cc8 LDR	X1, [SP, #360]

  (21) 0x410ccc SUB	X0, X0, X2

  (21) 0x410cd0 MOVZ	X2, #63439

  (21) 0x410cd4 FSQRT	S0, S0

  (21) 0x410cd8 MOVK	X2, #58195

  (21) 0x410cdc MOVK	X2, #39845

  (21) 0x410ce0 MOVK	X2, #8388

  (21) 0x410ce4 SMULH	X2, X0, X2

  (21) 0x410ce8 SBFM	X2, X2, #7, #63

  (21) 0x410cec SUB	X0, X2, X0,ASR #63

  (21) 0x410cf0 ADD	X1, X1, X0

  (21) 0x410cf4 FDIV	S15, S15, S0

  (21) 0x410cf8 STR	X1, [SP, #360]

  (21) 0x410cfc BL	4100f0

  (21) 0x410d00 LDR	W4, [SP, #168]

  (21) 0x410d04 ORR	X3, XZR, X27

  (21) 0x410d08 MOVZ	X10, #0

  (21) 0x410d0c LDP	X9, X7, [SP, #280]

  (21) 0x410d10 ORR	X14, XZR, X0

  (21) 0x410d14 ORR	X12, XZR, X22

  (21) 0x410d18 MOVZ	X1, #0

  (21) 0x410d1c STR	X26, [SP, #232]

  (21) 0x410d20 LDR	X26, [SP, #176]

  (21) 0x410d24 AND	W30, W4, #0x3

  (21) 0x410d28 UBFM	W18, W4, #2, #31

  (21) 0x410d2c AND	W16, W4, #0xfffffffc

  (21) 0x410d30 LDR	X8, [SP, #248]

  (21) 0x410d34 LDR	X6, [SP, #264]

  (21) 0x410d38 STP	X23, X19, [SP, #264]

  (21) 0x410d3c LDR	X23, [SP, #296]

  (21) 0x410d40 LDR	W5, [SP, #256]

  (21) 0x410d44 STP	X25, X24, [SP, #248]

  (21) 0x410d48 LDR	X24, [SP, #320]

  (21) 0x410d4c STR	W5, [SP, #168]

  (21) 0x410d50 LDR	W17, [SP, #212]

  (21) 0x410d54 LDR	W25, [SP, #308]

  (21) 0x410d58 HINT	#0

  (21) 0x410d5c HINT	#0

    (13) 0x410d60 ORR	W15, WZR, W1

    (13) 0x410d64 ORR	W11, WZR, W10

    (13) 0x410d68 CMP	W25, #2

    (13) 0x410d6c B.LS	4111d8

    (23) 0x410d70 ORR	X2, XZR, X3

    (23) 0x410d74 ORR	X0, XZR, X12

    (23) 0x410d78 ADD	X5, X3, W18,UXTW #4

    (23) 0x410d7c HINT	#0

      (22) 0x410d80 LDR	S31, [X2, #12]

      (22) 0x410d84 LDP	S29, S30, [X2, #4]

      (22) 0x410d88 LDR	S28, [X2], #16

      (22) 0x410d8c STR	S28, [X0]

      (22) 0x410d90 STR	S29, [X0, X6,LSL #2]

      (22) 0x410d94 STR	S30, [X0, X9]

      (22) 0x410d98 STR	S31, [X0, X7]

      (22) 0x410d9c ADD	X0, X0, X8

      (22) 0x410da0 CMP	X5, X2

      (22) 0x410da4 B.NE	410d80

    (23) 0x410da8 CBZ	W30, 4111b4

    (13) 0x410dac ORR	W0, WZR, W16

    (13) 0x410db0 ORR	W2, WZR, W16

    (13) 0x410db4 SUB	W5, W4, W0

    (13) 0x410db8 CMP	W5, #1

    (13) 0x410dbc B.EQ	410dec

    (13) 0x410dc0 ADD	X13, X10, W0,UXTW

    (13) 0x410dc4 ADD	X19, X27, X13,LSL #2

    (13) 0x410dc8 LDR	S30, [X27, X13,LSL #2]

    (13) 0x410dcc UMADDL	X0, W6, W0, X1

    (13) 0x410dd0 LDR	S31, [X19, #4]

    (13) 0x410dd4 ADD	X13, X22, X0,LSL #2

    (13) 0x410dd8 STR	S30, [X22, X0,LSL #2]

    (13) 0x410ddc STR	S31, [X13, X26]

    (13) 0x410de0 TBZ	W5, #0, 410dfc

    (13) 0x410de4 AND	W5, W5, #0xfffffffe

    (13) 0x410de8 ADD	W2, W2, W5

    (13) 0x410dec ADD	W11, W2, W11

    (13) 0x410df0 MADD	W2, W17, W2, W15

    (13) 0x410df4 LDR	S31, [X27, X11,LSL #2]

    (13) 0x410df8 STR	S31, [X22, X2,LSL #2]

    (13) 0x410dfc ADD	X1, X1, #1

    (13) 0x410e00 ADD	X3, X3, X24

    (13) 0x410e04 ADD	X12, X12, #4

    (13) 0x410e08 ADD	X10, X10, X23

    (13) 0x410e0c CMP	W17, W1

    (13) 0x410e10 B.GT	410d60

  (21) 0x410e14 LDR	W5, [SP, #168]

  (21) 0x410e18 LDP	X25, X24, [SP, #248]

  (21) 0x410e1c LDP	X23, X19, [SP, #264]

  (21) 0x410e20 STR	X6, [SP, #168]

  (21) 0x410e24 LDR	X26, [SP, #232]

  (21) 0x410e28 STR	W5, [SP, #232]

  (21) 0x410e2c STR	X8, [SP, #248]

  (21) 0x410e30 STR	W4, [SP, #256]

  (21) 0x410e34 STP	X14, X7, [SP, #264]

  (21) 0x410e38 STR	X9, [SP, #280]

  (21) 0x410e3c BL	4100f0

  (21) 0x410e40 LDR	X14, [SP, #264]

  (21) 0x410e44 MOVZ	X2, #63439

  (21) 0x410e48 MOVK	X2, #58195

  (21) 0x410e4c MOVK	X2, #39845

  (21) 0x410e50 LDR	X1, [SP, #368]

  (21) 0x410e54 MOVK	X2, #8388

  (21) 0x410e58 SUB	X0, X0, X14

  (21) 0x410e5c SMULH	X2, X0, X2

  (21) 0x410e60 SBFM	X2, X2, #7, #63

  (21) 0x410e64 SUB	X0, X2, X0,ASR #63

  (21) 0x410e68 ADD	X1, X1, X0

  (21) 0x410e6c STR	X1, [SP, #368]

  (21) 0x410e70 BL	4100f0

  (21) 0x410e74 LDR	X6, [SP, #168]

  (21) 0x410e78 MOVZ	W3, #0

  (21) 0x410e7c MOVZ	W11, #0

  (21) 0x410e80 LDP	X7, X9, [SP, #272]

  (21) 0x410e84 ORR	X2, XZR, X0

  (21) 0x410e88 MOVZ	W1, #0

  (21) 0x410e8c LDR	X8, [SP, #248]

  (21) 0x410e90 LDR	W5, [SP, #232]

  (21) 0x410e94 LDR	W4, [SP, #256]

  (21) 0x410e98 HINT	#0

  (21) 0x410e9c HINT	#0

    (16) 0x410ea0 MOVZ	W13, #0

      (15) 0x410ea4 MOVI	D21, #0

      (15) 0x410ea8 ORR	W10, WZR, W13

      (15) 0x410eac MOVZ	W0, #0

        (14) 0x410eb0 ADD	W12, W0, W3

        (14) 0x410eb4 LDR	S22, [X22, W10,UXTW #2]

        (14) 0x410eb8 ADD	W0, W0, #1

        (14) 0x410ebc ADD	W10, W10, W5

        (14) 0x410ec0 LDR	S20, [X20, X12,LSL #2]

        (14) 0x410ec4 FCVT	D22, S22

        (14) 0x410ec8 FCVT	D20, S20

        (14) 0x410ecc FMADD	D21, D20, D22, D21

        (14) 0x410ed0 CMP	W0, W4

        (14) 0x410ed4 B.CC	410eb0

      (15) 0x410ed8 FCVT	S21, D21

      (15) 0x410edc ADD	W0, W13, W11

      (15) 0x410ee0 ADD	W13, W13, #1

      (15) 0x410ee4 FMUL	S21, S21, S15

      (15) 0x410ee8 STR	S21, [X28, X0,LSL #2]

      (15) 0x410eec CMP	W5, W13

      (15) 0x410ef0 B.HI	410ea4

    (16) 0x410ef4 ADD	W1, W1, #1

    (16) 0x410ef8 ADD	W11, W11, W5

    (16) 0x410efc ADD	W3, W3, W4

    (16) 0x410f00 CMP	W5, W1

    (16) 0x410f04 B.HI	410ea0

  (21) 0x410f08 STR	X2, [SP, #168]

  (21) 0x410f0c STR	X9, [SP, #232]

  (21) 0x410f10 STR	X7, [SP, #248]

  (21) 0x410f14 STR	W4, [SP, #256]

  (21) 0x410f18 STR	X8, [SP, #264]

  (21) 0x410f1c STR	W5, [SP, #272]

  (21) 0x410f20 STR	X6, [SP, #280]

  (21) 0x410f24 BL	4100f0

  (21) 0x410f28 LDR	X2, [SP, #168]

  (21) 0x410f2c LDR	X1, [SP, #376]

  (21) 0x410f30 SUB	X0, X0, X2

  (21) 0x410f34 MOVZ	X2, #63439

  (21) 0x410f38 MOVK	X2, #58195

  (21) 0x410f3c MOVK	X2, #39845

  (21) 0x410f40 MOVK	X2, #8388

  (21) 0x410f44 SMULH	X2, X0, X2

  (21) 0x410f48 SBFM	X2, X2, #7, #63

  (21) 0x410f4c SUB	X0, X2, X0,ASR #63

  (21) 0x410f50 ADD	X1, X1, X0

  (21) 0x410f54 STR	X1, [SP, #376]

  (21) 0x410f58 BL	4100f0

  (21) 0x410f5c LDR	X1, [SP, #184]

  (21) 0x410f60 ORR	X10, XZR, X0

  (21) 0x410f64 ORR	X2, XZR, X26

  (21) 0x410f68 ORR	X0, XZR, X28

  (21) 0x410f6c LDR	W3, [SP, #212]

  (21) 0x410f70 STR	X10, [SP, #168]

  (21) 0x410f74 BL	4119e0

  (21) 0x410f78 BL	4100f0

  (21) 0x410f7c LDR	X10, [SP, #168]

  (21) 0x410f80 MOVZ	X2, #63439

  (21) 0x410f84 MOVK	X2, #58195

  (21) 0x410f88 MOVK	X2, #39845

  (21) 0x410f8c LDR	X1, [SP, #384]

  (21) 0x410f90 MOVK	X2, #8388

  (21) 0x410f94 SUB	X0, X0, X10

  (21) 0x410f98 SMULH	X2, X0, X2

  (21) 0x410f9c SBFM	X2, X2, #7, #63

  (21) 0x410fa0 SUB	X0, X2, X0,ASR #63

  (21) 0x410fa4 ADD	X1, X1, X0

  (21) 0x410fa8 STR	X1, [SP, #384]

  (21) 0x410fac BL	4100f0

  (21) 0x410fb0 LDR	X14, [SP, #192]

  (21) 0x410fb4 MOVZ	W3, #0

  (21) 0x410fb8 MOVZ	W11, #0

  (21) 0x410fbc ORR	X2, XZR, X0

  (21) 0x410fc0 MOVZ	W1, #0

  (21) 0x410fc4 LDR	X9, [SP, #232]

  (21) 0x410fc8 LDR	X7, [SP, #248]

  (21) 0x410fcc LDR	X8, [SP, #264]

  (21) 0x410fd0 LDR	X6, [SP, #280]

  (21) 0x410fd4 LDR	W4, [SP, #256]

  (21) 0x410fd8 LDR	W5, [SP, #272]

  (21) 0x410fdc HINT	#0

    (19) 0x410fe0 MOVZ	W13, #0

      (18) 0x410fe4 MOVI	D19, #0

      (18) 0x410fe8 ORR	W10, WZR, W13

      (18) 0x410fec MOVZ	W0, #0

        (17) 0x410ff0 ADD	W12, W0, W3

        (17) 0x410ff4 LDR	S17, [X21, W10,UXTW #2]

        (17) 0x410ff8 ADD	W0, W0, #1

        (17) 0x410ffc ADD	W10, W10, W4

        (17) 0x411000 LDR	S18, [X26, X12,LSL #2]

        (17) 0x411004 FCVT	D17, S17

        (17) 0x411008 FCVT	D18, S18

        (17) 0x41100c FMADD	D19, D18, D17, D19

        (17) 0x411010 CMP	W5, W0

        (17) 0x411014 B.HI	410ff0

      (18) 0x411018 FCVT	S19, D19

      (18) 0x41101c ADD	W0, W13, W11

      (18) 0x411020 ADD	W13, W13, #1

      (18) 0x411024 STR	S19, [X14, X0,LSL #2]

      (18) 0x411028 CMP	W13, W4

      (18) 0x41102c B.CC	410fe4

    (19) 0x411030 ADD	W1, W1, #1

    (19) 0x411034 ADD	W11, W11, W4

    (19) 0x411038 ADD	W3, W3, W5

    (19) 0x41103c CMP	W5, W1

    (19) 0x411040 B.HI	410fe0

  (21) 0x411044 STR	X9, [SP, #168]

  (21) 0x411048 STR	X7, [SP, #232]

  (21) 0x41104c STR	W4, [SP, #248]

  (21) 0x411050 STP	X2, X8, [SP, #256]

  (21) 0x411054 STR	W5, [SP, #272]

  (21) 0x411058 STR	X6, [SP, #280]

  (21) 0x41105c BL	4100f0

  (21) 0x411060 LDP	X2, X8, [SP, #256]

  (21) 0x411064 LDR	X3, [SP, #392]

  (21) 0x411068 SUB	X0, X0, X2

  (21) 0x41106c MOVZ	X2, #63439

  (21) 0x411070 MOVK	X2, #58195

  (21) 0x411074 LDR	W1, [SP, #304]

  (21) 0x411078 MOVK	X2, #39845

  (21) 0x41107c MOVK	X2, #8388

  (21) 0x411080 LDR	X9, [SP, #168]

  (21) 0x411084 SMULH	X2, X0, X2

  (21) 0x411088 LDR	X7, [SP, #232]

  (21) 0x41108c SUB	W1, W1, #1

  (21) 0x411090 LDR	X6, [SP, #280]

  (21) 0x411094 SBFM	X2, X2, #7, #63

  (21) 0x411098 SUB	X0, X2, X0,ASR #63

  (21) 0x41109c LDR	W4, [SP, #248]

  (21) 0x4110a0 ADD	X3, X3, X0

  (21) 0x4110a4 LDR	W5, [SP, #272]

  (21) 0x4110a8 ORR	W0, WZR, W1

  (21) 0x4110ac STR	X3, [SP, #392]

  (21) 0x4110b0 LDR	X1, [SP, #200]

  (21) 0x4110b4 CMP	X1, W0,SXTW

  (21) 0x4110b8 B.EQ	4111f0

  (21) 0x4110bc ADD	X0, SP, #400

  (21) 0x4110c0 STR	X6, [SP, #168]

  (21) 0x4110c4 STR	W5, [SP, #232]

  (21) 0x4110c8 STR	X8, [SP, #248]

  (21) 0x4110cc STR	W4, [SP, #256]

  (21) 0x4110d0 STP	X7, X9, [SP, #264]

  (21) 0x4110d4 BL	410080

  (21) 0x4110d8 LDP	X1, X0, [SP, #176]

  (21) 0x4110dc BL	4100c0

  (21) 0x4110e0 LDR	X1, [SP, #152]

  (21) 0x4110e4 ORR	X0, XZR, X26

  (21) 0x4110e8 BL	4100c0

  (21) 0x4110ec LDR	X1, [SP, #152]

  (21) 0x4110f0 ORR	X0, XZR, X28

  (21) 0x4110f4 BL	4100c0

  (21) 0x4110f8 LDR	X26, [SP, #144]

  (21) 0x4110fc ORR	X0, XZR, X21

  (21) 0x411100 ORR	X1, XZR, X26

  (21) 0x411104 BL	4100c0

  (21) 0x411108 ORR	X1, XZR, X26

  (21) 0x41110c ORR	X0, XZR, X22

  (21) 0x411110 BL	4100c0

  (21) 0x411114 ORR	X1, XZR, X26

  (21) 0x411118 ORR	X0, XZR, X27

  (21) 0x41111c BL	4100c0

  (21) 0x411120 ORR	X1, XZR, X26

  (21) 0x411124 ORR	X0, XZR, X20

  (21) 0x411128 BL	4100c0

  (21) 0x41112c LDR	X0, [SP, #192]

  (21) 0x411130 ORR	X1, XZR, X26

  (21) 0x411134 BL	4100c0

  (21) 0x411138 LDR	X21, [SP, #160]

  (21) 0x41113c ORR	X0, XZR, X24

  (21) 0x411140 ORR	X1, XZR, X21

  (21) 0x411144 BL	4100c0

  (21) 0x411148 ORR	X1, XZR, X21

  (21) 0x41114c ORR	X0, XZR, X23

  (21) 0x411150 BL	4100c0

  (21) 0x411154 ORR	X1, XZR, X21

  (21) 0x411158 ORR	X0, XZR, X25

  (21) 0x41115c BL	4100c0

  (21) 0x411160 ORR	X1, XZR, X26

  (21) 0x411164 ORR	X0, XZR, X19

  (21) 0x411168 BL	4100c0

  (21) 0x41116c LDR	X0, [SP, #200]

  (21) 0x411170 LDR	X1, [SP, #312]

  (21) 0x411174 ADD	X0, X0, #1

  (21) 0x411178 STR	X0, [SP, #200]

  (21) 0x41117c CMP	X0, X1

  (21) 0x411180 B.EQ	4114cc

  (21) 0x411184 ORR	X0, XZR, X26

  (21) 0x411188 BL	4100b0

  (21) 0x41118c ORR	X19, XZR, X0

  (21) 0x411190 STR	WZR, [X0]

  (21) 0x411194 LDR	X0, [SP, #224]

  (21) 0x411198 LDP	X7, X9, [SP, #264]

  (21) 0x41119c LDR	X6, [SP, #168]

  (21) 0x4111a0 LDR	X8, [SP, #248]

  (21) 0x4111a4 LDR	W5, [SP, #232]

  (21) 0x4111a8 LDR	W4, [SP, #256]

  (21) 0x4111ac CBNZ	X0, 410324

  (21) 0x4111b0 B	410380

    (23) 0x4111b4 ADD	X1, X1, #1

    (23) 0x4111b8 ADD	X3, X3, X24

    (23) 0x4111bc ADD	X12, X12, #4

    (23) 0x4111c0 ADD	X10, X10, X23

    (23) 0x4111c4 CMP	W17, W1

    (23) 0x4111c8 B.LE	410e14

    (23) 0x4111cc ORR	W15, WZR, W1

    (23) 0x4111d0 ORR	W11, WZR, W10

    (23) 0x4111d4 B	410d70

    (13) 0x4111d8 MOVZ	W0, #0

    (13) 0x4111dc MOVZ	W2, #0

    (13) 0x4111e0 B	410db4

    (24) 0x4111e4 MOVN	W0, #49280

    (24) 0x4111e8 FMOV	S31, W0

    (24) 0x4111ec B	4109a8

  (21) 0x4111f0 MOVZ	W0, #46871

  (21) 0x4111f4 LDR	X2, [SP, #184]

  (21) 0x4111f8 ORR	X1, XZR, X26

  (21) 0x4111fc MOVK	W0, #14545

  (21) 0x411200 STR	X6, [SP, #256]

  (21) 0x411204 LDR	W3, [SP, #212]

  (21) 0x411208 FMOV	S0, W0

  (21) 0x41120c ORR	X0, XZR, X28

  (21) 0x411210 STR	W5, [SP, #264]

  (21) 0x411214 STR	X8, [SP, #272]

  (21) 0x411218 STR	W4, [SP, #280]

  (21) 0x41121c STR	X7, [SP, #288]

  (21) 0x411220 STR	X9, [SP, #328]

  (21) 0x411224 BL	411c20

  (21) 0x411228 AND	W3, W0, #0xff

  (21) 0x41122c ADRP	X0,

  (21) 0x411230 ADD	X0, X0, #192

  (21) 0x411234 ADRP	X1,

  (21) 0x411238 ADD	X1, X1, #520

  (21) 0x41123c MOVZ	X2, #20

  (21) 0x411240 STR	W3, [SP, #232]

  (21) 0x411244 STR	X0, [SP, #168]

  (21) 0x411248 BL	4100d0

  (21) 0x41124c ADRP	X1,

  (21) 0x411250 LDR	X0, [SP, #168]

  (21) 0x411254 MOVZ	X2, #27

  (21) 0x411258 ADD	X1, X1, #544

  (21) 0x41125c BL	4100d0

  (21) 0x411260 LDR	W0, [SP, #232]

  (21) 0x411264 LDR	X6, [SP, #256]

  (21) 0x411268 LDR	X8, [SP, #272]

  (21) 0x41126c AND	W1, W0, #0x1

  (21) 0x411270 LDR	X7, [SP, #288]

  (21) 0x411274 STR	W1, [SP, #248]

  (21) 0x411278 LDR	X9, [SP, #328]

  (21) 0x41127c LDR	W5, [SP, #264]

  (21) 0x411280 LDR	W4, [SP, #280]

  (21) 0x411284 TBNZ	W0, #0, 4114bc

  (21) 0x411288 ADRP	X1,

  (21) 0x41128c MOVZ	X2, #6

  (21) 0x411290 ADD	X1, X1, #176

  (21) 0x411294 LDR	X0, [SP, #168]

  (21) 0x411298 STR	X6, [SP, #256]

  (21) 0x41129c STR	W5, [SP, #264]

  (21) 0x4112a0 STR	X8, [SP, #272]

  (21) 0x4112a4 STR	W4, [SP, #280]

  (21) 0x4112a8 STR	X7, [SP, #288]

  (21) 0x4112ac STR	X9, [SP, #328]

  (21) 0x4112b0 BL	4100d0

  (21) 0x4112b4 ADRP	X0,

  (21) 0x4112b8 MOVZ	X2, #1

  (21) 0x4112bc ADD	X1, X0, #96

  (21) 0x4112c0 LDR	X0, [SP, #168]

  (21) 0x4112c4 STR	X1, [SP, #232]

  (21) 0x4112c8 BL	4100d0

  (21) 0x4112cc ADRP	X1,

  (21) 0x4112d0 LDR	X0, [SP, #168]

  (21) 0x4112d4 MOVZ	X2, #21

  (21) 0x4112d8 ADD	X1, X1, #576

  (21) 0x4112dc BL	4100d0

  (21) 0x4112e0 ADRP	X1,

  (21) 0x4112e4 LDR	X0, [SP, #168]

  (21) 0x4112e8 MOVZ	X2, #3

  (21) 0x4112ec ADD	X1, X1, #600

  (21) 0x4112f0 BL	4100d0

  (21) 0x4112f4 LDR	X0, [SP, #168]

  (21) 0x4112f8 MOVZ	X2, #1

  (21) 0x4112fc LDR	X1, [SP, #232]

  (21) 0x411300 BL	4100d0

  (21) 0x411304 LDR	W0, [SP, #248]

  (21) 0x411308 LDR	X6, [SP, #256]

  (21) 0x41130c LDR	X8, [SP, #272]

  (21) 0x411310 LDR	X7, [SP, #288]

  (21) 0x411314 LDR	X9, [SP, #328]

  (21) 0x411318 LDR	W5, [SP, #264]

  (21) 0x41131c LDR	W4, [SP, #280]

  (21) 0x411320 CBNZ	W0, 4110bc

0x411324 ADD	X0, SP, #400

0x411328 BL	410080

0x41132c LDP	X1, X0, [SP, #176]

0x411330 BL	4100c0

0x411334 LDR	X1, [SP, #152]

0x411338 ORR	X0, XZR, X26

0x41133c BL	4100c0

0x411340 LDR	X1, [SP, #152]

0x411344 ORR	X0, XZR, X28

0x411348 BL	4100c0

0x41134c LDR	X26, [SP, #144]

0x411350 ORR	X0, XZR, X21

0x411354 ORR	X1, XZR, X26

0x411358 BL	4100c0

0x41135c ORR	X1, XZR, X26

0x411360 ORR	X0, XZR, X22

0x411364 BL	4100c0

0x411368 ORR	X1, XZR, X26

0x41136c ORR	X0, XZR, X27

0x411370 BL	4100c0

0x411374 ORR	X1, XZR, X26

0x411378 ORR	X0, XZR, X20

0x41137c BL	4100c0

0x411380 LDR	X0, [SP, #192]

0x411384 ORR	X1, XZR, X26

0x411388 BL	4100c0

0x41138c LDR	X21, [SP, #160]

0x411390 ORR	X0, XZR, X24

0x411394 ORR	X1, XZR, X21

0x411398 BL	4100c0

0x41139c ORR	X0, XZR, X23

0x4113a0 ORR	X1, XZR, X21

0x4113a4 BL	4100c0

0x4113a8 ORR	X0, XZR, X25

0x4113ac ORR	X1, XZR, X21

0x4113b0 BL	4100c0

0x4113b4 ORR	X1, XZR, X26

0x4113b8 ORR	X0, XZR, X19

0x4113bc BL	4100c0

0x4113c0 LDP	D12, D13, [SP, #96]

0x4113c4 MOVZ	W0, #1

0x4113c8 LDP	X23, X24, [SP, #48]

0x4113cc LDP	X25, X26, [SP, #64]

0x4113d0 LDP	X27, X28, [SP, #80]

0x4113d4 LDP	D14, D15, [SP, #112]

0x4113d8 B	41160c

  (21) 0x4113dc MOVZ	X0, #4

  (21) 0x4113e0 STR	W5, [SP, #184]

  (21) 0x4113e4 STR	W4, [SP, #248]

  (21) 0x4113e8 BL	4100b0

  (21) 0x4113ec LDR	X6, [SP, #168]

  (21) 0x4113f0 ORR	X26, XZR, X0

  (21) 0x4113f4 STR	WZR, [X0]

  (21) 0x4113f8 LDR	X8, [SP, #232]

  (21) 0x4113fc LDP	X7, X9, [SP, #256]

  (21) 0x411400 LDR	W5, [SP, #184]

  (21) 0x411404 LDR	W4, [SP, #248]

  (21) 0x411408 B	410600

  (21) 0x41140c MOVZ	X0, #4

  (21) 0x411410 STR	W5, [SP, #184]

  (21) 0x411414 STR	W4, [SP, #248]

  (21) 0x411418 BL	4100b0

  (21) 0x41141c ORR	X20, XZR, X0

  (21) 0x411420 MOVZ	X0, #4

  (21) 0x411424 STR	WZR, [X20]

  (21) 0x411428 BL	4100b0

  (21) 0x41142c ORR	X27, XZR, X0

  (21) 0x411430 MOVZ	X0, #4

  (21) 0x411434 STR	WZR, [X27]

  (21) 0x411438 BL	4100b0

  (21) 0x41143c LDR	W5, [SP, #184]

  (21) 0x411440 ORR	X22, XZR, X0

  (21) 0x411444 MOVZ	X0, #4

  (21) 0x411448 LDR	W4, [SP, #248]

  (21) 0x41144c STR	WZR, [X22]

  (21) 0x411450 STR	W5, [SP, #184]

  (21) 0x411454 STR	W4, [SP, #248]

  (21) 0x411458 BL	4100b0

  (21) 0x41145c LDR	X6, [SP, #168]

  (21) 0x411460 ORR	X21, XZR, X0

  (21) 0x411464 STR	WZR, [X0]

  (21) 0x411468 LDR	X8, [SP, #232]

  (21) 0x41146c LDP	X7, X9, [SP, #256]

  (21) 0x411470 LDR	W5, [SP, #184]

  (21) 0x411474 LDR	W4, [SP, #248]

  (21) 0x411478 B	410550

  (21) 0x41147c MOVZ	X0, #4

  (21) 0x411480 STR	W5, [SP, #184]

  (21) 0x411484 STR	W4, [SP, #232]

  (21) 0x411488 BL	4100b0

  (21) 0x41148c ORR	X23, XZR, X0

  (21) 0x411490 MOVZ	X0, #4

  (21) 0x411494 STR	WZR, [X23]

  (21) 0x411498 BL	4100b0

  (21) 0x41149c LDR	X6, [SP, #168]

  (21) 0x4114a0 ORR	X24, XZR, X0

  (21) 0x4114a4 STR	WZR, [X0]

  (21) 0x4114a8 LDR	X8, [SP, #192]

  (21) 0x4114ac LDP	X7, X9, [SP, #248]

  (21) 0x4114b0 LDR	W5, [SP, #184]

  (21) 0x4114b4 LDR	W4, [SP, #232]

  (21) 0x4114b8 B	41043c

  (21) 0x4114bc ADRP	X1,

  (21) 0x4114c0 MOVZ	X2, #2

  (21) 0x4114c4 ADD	X1, X1, #168

  (21) 0x4114c8 B	411294

0x4114cc LDP	D12, D13, [SP, #96]

0x4114d0 LDP	X23, X24, [SP, #48]

0x4114d4 LDP	X25, X26, [SP, #64]

0x4114d8 LDP	X27, X28, [SP, #80]

0x4114dc ADRP	X19,

0x4114e0 ADRP	X1,

0x4114e4 ADD	X19, X19, #192

0x4114e8 MOVZ	X2, #22

0x4114ec ADD	X1, X1, #280

0x4114f0 ORR	X0, XZR, X19

0x4114f4 BL	4100d0

0x4114f8 LDR	X1, [SP, #344]

0x4114fc ORR	X0, XZR, X19

0x411500 ADRP	X20,

0x411504 ADD	X20, X20, #304

0x411508 BL	410090

0x41150c ORR	X1, XZR, X20

0x411510 BL	4100a0

0x411514 ADRP	X1,

0x411518 MOVZ	X2, #20

0x41151c ADD	X1, X1, #312

0x411520 ORR	X0, XZR, X19

0x411524 BL	4100d0

0x411528 LDR	X1, [SP, #352]

0x41152c ORR	X0, XZR, X19

0x411530 BL	410090

0x411534 ORR	X1, XZR, X20

0x411538 BL	4100a0

0x41153c ADRP	X1,

0x411540 MOVZ	X2, #22

0x411544 ADD	X1, X1, #336

0x411548 ORR	X0, XZR, X19

0x41154c BL	4100d0

0x411550 LDR	X1, [SP, #360]

0x411554 ORR	X0, XZR, X19

0x411558 BL	410090

0x41155c ORR	X1, XZR, X20

0x411560 BL	4100a0

0x411564 ADRP	X1,

0x411568 MOVZ	X2, #19

0x41156c ADD	X1, X1, #360

0x411570 ORR	X0, XZR, X19

0x411574 BL	4100d0

0x411578 LDR	X1, [SP, #368]

0x41157c ORR	X0, XZR, X19

0x411580 BL	410090

0x411584 ORR	X1, XZR, X20

0x411588 BL	4100a0

0x41158c ADRP	X1,

0x411590 MOVZ	X2, #20

0x411594 ADD	X1, X1, #384

0x411598 ORR	X0, XZR, X19

0x41159c BL	4100d0

0x4115a0 LDR	X1, [SP, #376]

0x4115a4 ORR	X0, XZR, X19

0x4115a8 BL	410090

0x4115ac ORR	X1, XZR, X20

0x4115b0 BL	4100a0

0x4115b4 ADRP	X1,

0x4115b8 MOVZ	X2, #17

0x4115bc ADD	X1, X1, #408

0x4115c0 ORR	X0, XZR, X19

0x4115c4 BL	4100d0

0x4115c8 LDR	X1, [SP, #384]

0x4115cc ORR	X0, XZR, X19

0x4115d0 BL	410090

0x4115d4 ORR	X1, XZR, X20

0x4115d8 BL	4100a0

0x4115dc ADRP	X1,

0x4115e0 MOVZ	X2, #23

0x4115e4 ADD	X1, X1, #432

0x4115e8 ORR	X0, XZR, X19

0x4115ec BL	4100d0

0x4115f0 LDR	X1, [SP, #392]

0x4115f4 ORR	X0, XZR, X19

0x4115f8 BL	410090

0x4115fc ORR	X1, XZR, X20

0x411600 BL	4100a0

0x411604 LDP	D14, D15, [SP, #112]

0x411608 MOVZ	W0, #0

0x41160c MOVZ	X12, #10400

0x411610 LDP	X29, X30, [SP]

0x411614 LDP	X19, X20, [SP, #16]

0x411618 LDP	X21, X22, [SP, #32]

0x41161c ADD	SP, SP, X12,UXTX

0x411620 RET

0x411624 ADRP	X19,

0x411628 ADRP	X1,

0x41162c ADD	X19, X19, #464

0x411630 MOVZ	X2, #7

0x411634 ADD	X1, X1, #184

0x411638 ORR	X0, XZR, X19

0x41163c BL	4100d0

0x411640 LDR	X1, [X21]

0x411644 ORR	X0, XZR, X19

0x411648 BL	4100a0

0x41164c ADRP	X1,

0x411650 ADD	X1, X1, #192

0x411654 BL	4100a0

0x411658 MOVZ	W0, #1

0x41165c B	41160c

0x411660 ADRP	X1,

0x411664 ADRP	X0,

0x411668 ADD	X1, X1, #224

0x41166c ADD	X0, X0, #464

0x411670 BL	4100a0

0x411674 LDP	D14, D15, [SP, #112]

0x411678 MOVZ	W0, #1

0x41167c B	41160c

0x411680 ORR	X1, XZR, X0

0x411684 ADD	X0, SP, #400

0x411688 STR	X1, [SP, #136]

0x41168c BL	410080

0x411690 LDR	X2, [SP, #136]

0x411694 LDP	X1, X0, [SP, #176]

0x411698 STR	X2, [SP, #136]

0x41169c BL	4100c0

0x4116a0 LDR	X2, [SP, #136]

0x4116a4 ORR	X0, XZR, X26

0x4116a8 STR	X2, [SP, #136]

0x4116ac LDR	X1, [SP, #152]

0x4116b0 BL	4100c0

0x4116b4 LDR	X2, [SP, #136]

0x4116b8 ORR	X26, XZR, X2

0x4116bc LDR	X1, [SP, #152]

0x4116c0 ORR	X0, XZR, X28

0x4116c4 BL	4100c0

0x4116c8 LDR	X1, [SP, #144]

0x4116cc ORR	X0, XZR, X21

0x4116d0 ORR	X21, XZR, X26

0x4116d4 BL	4100c0

0x4116d8 LDR	X1, [SP, #144]

0x4116dc ORR	X0, XZR, X22

0x4116e0 BL	4100c0

0x4116e4 LDR	X1, [SP, #144]

0x4116e8 ORR	X0, XZR, X27

0x4116ec BL	4100c0

(0) 0x4116f0 LDR	X1, [SP, #144]

(0) 0x4116f4 ORR	X0, XZR, X20

(0) 0x4116f8 ORR	X20, XZR, X21

(0) 0x4116fc BL	4100c0

(0) 0x411700 LDR	X1, [SP, #144]

(0) 0x411704 LDR	X0, [SP, #192]

(0) 0x411708 BL	4100c0

(0) 0x41170c LDR	X1, [SP, #160]

(0) 0x411710 ORR	X0, XZR, X24

(0) 0x411714 BL	4100c0

(0) 0x411718 LDR	X1, [SP, #160]

(0) 0x41171c ORR	X0, XZR, X23

(0) 0x411720 BL	4100c0

(0) 0x411724 LDR	X1, [SP, #160]

(0) 0x411728 ORR	X0, XZR, X25

(0) 0x41172c BL	4100c0

(0) 0x411730 LDR	X1, [SP, #144]

(0) 0x411734 ORR	X0, XZR, X19

(0) 0x411738 BL	4100c0

(0) 0x41173c ORR	X0, XZR, X20

(0) 0x411740 BL	410170

(0) 0x411744 ORR	X21, XZR, X0

(0) 0x411748 B	4116f0

0x41174c ORR	X21, XZR, X0

0x411750 B	4116e4

0x411754 ORR	X21, XZR, X0

0x411758 B	4116d8

0x41175c ADRP	X0,

0x411760 ADD	X0, X0, #456

0x411764 BL	410050

0x411768 ORR	X26, XZR, X0

0x41176c B	4116c8

0x411770 ORR	X26, XZR, X0

0x411774 B	4116bc

0x411778 ORR	X2, XZR, X0

0x41177c B	4116a4

0x411780 ORR	X1, XZR, X0

0x411784 MOVZ	X9, #5400

0x411788 ADD	X0, SP, X9,UXTX

0x41178c STR	X1, [SP, #136]

0x411790 BL	4100e0

0x411794 LDR	X2, [SP, #136]

0x411798 B	411694

0x41179c ORR	X20, XZR, X0

0x4117a0 B	411724

0x4117a4 ORR	X20, XZR, X0

0x4117a8 B	411718

0x4117ac ORR	X20, XZR, X0

0x4117b0 B	41170c

0x4117b4 ORR	X20, XZR, X0

0x4117b8 B	411700

0x4117bc ADRP	X0,

0x4117c0 ADD	X0, X0, #456

0x4117c4 BL	410050

0x4117c8 ORR	X20, XZR, X0

0x4117cc B	411730

0x4117d0 ADRP	X0,

0x4117d4 ADD	X0, X0, #456

0x4117d8 BL	410050

0x4117dc HINT	#0

0x4117e0 HINT	#0

0x4117e4 HINT	#0

0x4117e8 HINT	#0

0x4117ec HINT	#0

0x4117f0 HINT	#0

0x4117f4 HINT	#0

0x4117f8 HINT	#0

0x4117fc HINT	#0

Coverage (%)	Name	Source Location	Module
►100.00+	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start	stl_vector.h:1920	attention-gcc-native

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run run_0

Source file and lines	attention_v2.cpp:26-332
Module	attention-gcc-native

The function is defined in:

/usr/include/c++/14/bits/stl_algobase.h:952,1140,1146
/usr/include/c++/14/bits/chrono.h:214,627,716
/usr/include/stdlib.h:363
/usr/include/c++/14/bits/stl_construct.h:109,119
/usr/include/c++/14/bits/stl_uninitialized.h:668
/usr/include/c++/14/cmath:443
/usr/include/c++/14/bits/char_traits.h:350,427
/usr/include/c++/14/bits/basic_string.h:194,223-228,243,269,294,809
/usr/include/c++/14/bits/stl_vector.h:1128-1131,1919-1920
/usr/include/c++/14/bits/random.h:248,1760,1766,1782
/home/eoseret/llm-attention/attention_v2.cpp:26-33,97-100,107-109,129-135,144,160-167,175-178,185,194,204,213,223-226,233-238,245,254,264,273-276,283,292,302-310,317-332
/usr/include/c++/14/bits/new_allocator.h:104,126,151-156,172
/usr/include/c++/14/bits/basic_string.tcc:242
/usr/include/c++/14/bits/random.tcc:326-342,458-466,3367-3374
/usr/include/c++/14/ostream:175,673

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 51.25 to 11.00 cycles (4.66x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is not vectorized. Only 29% of vector register length is used (average across all VPU instructions). By fully vectorizing your function, you can lower the cost of an iteration from 51.25 to 37.62 cycles (1.36x speedup).

Details

6% of VPU instructions are used in vector version (process two or more data elements in vector registers):

14% of VPU loads are used in vector version.
14% of VPU stores are used in vector version.
0% of VPU addition or subtraction instructions are used in vector version.
0% of VPU multiply instructions are used in vector version.
0% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

@plt_start@: 3 occurrences►
- /usr/include/stdlib.h:363
- /usr/include/stdlib.h:363
- /usr/include/stdlib.h:363
unknown: 50 occurrences►
- /usr/include/c++/14/bits/new_allocator.h:151
- /usr/include/c++/14/bits/random.h:1766
- /usr/include/c++/14/bits/new_allocator.h:172
- /usr/include/c++/14/bits/new_allocator.h:172
- /usr/include/c++/14/bits/new_allocator.h:172
- /usr/include/c++/14/bits/new_allocator.h:172
- /usr/include/c++/14/bits/new_allocator.h:172
- /usr/include/c++/14/bits/new_allocator.h:172
- /usr/include/c++/14/bits/new_allocator.h:172
- /usr/include/c++/14/bits/new_allocator.h:172
- /usr/include/c++/14/bits/new_allocator.h:172
- /usr/include/c++/14/bits/new_allocator.h:172
- /usr/include/c++/14/bits/new_allocator.h:172
- /usr/include/c++/14/bits/new_allocator.h:172
- /usr/include/c++/14/ostream:673
- /usr/include/c++/14/ostream:175
- /home/eoseret/llm-attention/attention_v2.cpp:322
- /usr/include/c++/14/ostream:673
- /usr/include/c++/14/ostream:175
- /home/eoseret/llm-attention/attention_v2.cpp:323
- /usr/include/c++/14/ostream:673
- /usr/include/c++/14/ostream:175
- /home/eoseret/llm-attention/attention_v2.cpp:324
- /usr/include/c++/14/ostream:673
- /usr/include/c++/14/ostream:175
- /home/eoseret/llm-attention/attention_v2.cpp:325
- /usr/include/c++/14/ostream:673
- /usr/include/c++/14/ostream:175
- /home/eoseret/llm-attention/attention_v2.cpp:326
- /usr/include/c++/14/ostream:673
- /usr/include/c++/14/ostream:175
- /home/eoseret/llm-attention/attention_v2.cpp:327
- /usr/include/c++/14/ostream:673
- /usr/include/c++/14/ostream:175
- /home/eoseret/llm-attention/attention_v2.cpp:328
- /usr/include/c++/14/ostream:673
- /home/eoseret/llm-attention/attention_v2.cpp:99
- /home/eoseret/llm-attention/attention_v2.cpp:99
- /home/eoseret/llm-attention/attention_v2.cpp:108
- /usr/include/c++/14/bits/random.h:1766
- /usr/include/c++/14/bits/new_allocator.h:172
- /usr/include/c++/14/bits/new_allocator.h:172
- /usr/include/c++/14/bits/new_allocator.h:172
- /usr/include/c++/14/bits/new_allocator.h:172
- /usr/include/c++/14/bits/new_allocator.h:172
- /usr/include/c++/14/bits/new_allocator.h:172
- /usr/include/c++/14/bits/stl_vector.h:1920
- /usr/include/c++/14/bits/basic_string.h:809
- /usr/include/c++/14/bits/stl_vector.h:1920
- /usr/include/c++/14/bits/stl_vector.h:1920

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 6 bytes. The binary function is storing 18 bytes.

General properties

nb instructions	317
nb uops	308
loop length	1268
used w registers	10
used x registers	21
used b registers	0
used h registers	0
used s registers	2
used d registers	4
used q registers	1
used v registers	1
used z registers	0
nb stack references	73

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	38.50 cycles
front end	38.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	36.50	36.50	51.25	51.25	51.25	51.25	2.50	2.50	1.00	1.00	27.00	27.00	27.00	14.50	14.50
cycles	36.50	36.50	51.25	51.25	51.25	51.25	2.50	2.50	1.00	1.00	27.00	27.00	27.00	14.50	14.50

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	38.50
Dispatch	51.25
Overall L1	51.25

Vectorization ratios

INT

all	6%
load	14%
store	14%
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

INT+FP

all	6%
load	14%
store	14%
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

INT

all	29%
load	34%
store	33%
mul	25%
add-sub	24%
fma	NA (no fma vectorizable/vectorized instructions)
other	27%

all	12%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	12%

INT+FP

all	29%
load	34%
store	33%
mul	25%
add-sub	24%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	27%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 51.25 cycles. At this rate:

0% of peak load performance is reached (0.12 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
0% of peak store performance is reached (0.35 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the function is: 4101c0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput	Vectorization
MOVZ X12, #10400	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
SUB SP, SP, X12,UXTX	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	N/A
STP X29, X30, [SP]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X29, SP, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ORR X21, XZR, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP W0, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.LE 411624 <main+0x1464>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVZ W2, #10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVZ X1, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
STP D14, D15, [SP, #112]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (50.0%)
LDR X0, [X21, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
BL 410040 <@plt_start@+0x20>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X20, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
LDR X0, [X21, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
MOVZ W2, #10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVZ X1, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
STR W20, [SP, #212]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (12.5%)
BL 410040 <@plt_start@+0x20>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
FMOV S14, W0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (12.5%)
ORR X19, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
MOVZ W2, #10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X0, [X21, #24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
MOVZ X1, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
BL 410040 <@plt_start@+0x20>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP W20, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
STR W0, [SP, #304]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (12.5%)
CCMP W19, #0, #4, #12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
B.LE 411660 <main+0x14a0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SBFM X2, X0, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVI V31.4S, #0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (12.5%)
SBFM X1, X19, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (100.0%)
STR XZR, [SP, #392]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
SBFM X6, X20, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (100.0%)
STR X2, [SP, #312]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
UMULL X2, W19, W19	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	N/A
STR X1, [SP, #296]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
UMULL X1, W20, W19	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	scal (25.0%)
STR X2, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
UMULL X2, W20, W20	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	N/A
STR X2, [SP, #216]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ADD X2, SP, #512	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STUR Q31, [X2, #344]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (50.0%)
STUR Q31, [X2, #360]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (50.0%)
STUR Q31, [X2, #376]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (50.0%)
CBZ W0, 4114dc <main+0x131c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVN X0, #57344	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X27, X28, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP D12, D13, [SP, #96]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (50.0%)
CMP X1, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.HI 4117d0 <main+0x1610>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR W5, WZR, W20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
UBFM X0, X1, #62, #61	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR W19, [SP, #200]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (12.5%)
SUB X20, X1, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
UMULL X1, W19, W19	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	scal (25.0%)
UBFM X9, X6, #61, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
MOVZ W7, #12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
UBFM X8, X6, #60, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
STR X0, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR W5, [SP, #240]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (12.5%)
UBFM X1, X1, #62, #61	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
UMULL X7, W6, W7	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	scal (25.0%)
STP X6, X8, [SP, #184]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X1, X9, [SP, #160]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X1, [SP, #216]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
STP X20, X7, [SP, #224]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
UBFM X1, X1, #62, #61	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
STR X1, [SP, #152]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
UBFM X1, X6, #62, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
STR X1, [SP, #176]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
SBFM X1, X19, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (100.0%)
UBFM X1, X1, #62, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
STR X1, [SP, #320]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
SUB W1, W19, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
STR W1, [SP, #308]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (12.5%)
BL 4100b0 <@plt_start@+0x90>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR W4, [SP, #200]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (12.5%)
ORR X19, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
STR WZR, [X0]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (12.5%)
STR XZR, [SP, #200]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X9, [SP, #168]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDP X6, X8, [SP, #184]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDR X7, [SP, #232]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR W5, [SP, #240]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (12.5%)
CBZ X20, 410360 <main+0x1a0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X0, SP, #400	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
BL 410080 <@plt_start@+0x60>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X1, X0, [SP, #176]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
BL 4100c0 <@plt_start@+0xa0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X1, [SP, #152]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ORR X0, XZR, X26	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
BL 4100c0 <@plt_start@+0xa0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X1, [SP, #152]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ORR X0, XZR, X28	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
BL 4100c0 <@plt_start@+0xa0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X26, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ORR X0, XZR, X21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR X1, XZR, X26	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
BL 4100c0 <@plt_start@+0xa0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X1, XZR, X26	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ORR X0, XZR, X22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
BL 4100c0 <@plt_start@+0xa0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X1, XZR, X26	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ORR X0, XZR, X27	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
BL 4100c0 <@plt_start@+0xa0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X1, XZR, X26	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ORR X0, XZR, X20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
BL 4100c0 <@plt_start@+0xa0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X0, [SP, #192]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ORR X1, XZR, X26	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
BL 4100c0 <@plt_start@+0xa0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X21, [SP, #160]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ORR X0, XZR, X24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR X1, XZR, X21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
BL 4100c0 <@plt_start@+0xa0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X0, XZR, X23	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR X1, XZR, X21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
BL 4100c0 <@plt_start@+0xa0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X0, XZR, X25	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR X1, XZR, X21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
BL 4100c0 <@plt_start@+0xa0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X1, XZR, X26	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ORR X0, XZR, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
BL 4100c0 <@plt_start@+0xa0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP D12, D13, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (50.0%)
MOVZ W0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X27, X28, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP D14, D15, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (50.0%)
B 41160c <main+0x144c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP D12, D13, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (50.0%)
LDP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X27, X28, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
ADRP X19, <4404dc>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADRP X1, <4204e0>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X19, X19, #192	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
MOVZ X2, #22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X1, X1, #280	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ORR X0, XZR, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
BL 4100d0 <@plt_start@+0xb0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X1, [SP, #344]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ORR X0, XZR, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADRP X20, <420500>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X20, X20, #304	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
BL 410090 <@plt_start@+0x70>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X1, XZR, X20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
BL 4100a0 <@plt_start@+0x80>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADRP X1, <420514>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
MOVZ X2, #20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X1, X1, #312	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ORR X0, XZR, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
BL 4100d0 <@plt_start@+0xb0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X1, [SP, #352]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ORR X0, XZR, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
BL 410090 <@plt_start@+0x70>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X1, XZR, X20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
BL 4100a0 <@plt_start@+0x80>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADRP X1, <42053c>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
MOVZ X2, #22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X1, X1, #336	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ORR X0, XZR, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
BL 4100d0 <@plt_start@+0xb0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X1, [SP, #360]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ORR X0, XZR, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
BL 410090 <@plt_start@+0x70>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X1, XZR, X20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
BL 4100a0 <@plt_start@+0x80>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADRP X1, <420564>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
MOVZ X2, #19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X1, X1, #360	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ORR X0, XZR, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
BL 4100d0 <@plt_start@+0xb0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X1, [SP, #368]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ORR X0, XZR, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
BL 410090 <@plt_start@+0x70>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X1, XZR, X20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
BL 4100a0 <@plt_start@+0x80>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADRP X1, <42058c>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
MOVZ X2, #20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X1, X1, #384	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ORR X0, XZR, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
BL 4100d0 <@plt_start@+0xb0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X1, [SP, #376]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ORR X0, XZR, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
BL 410090 <@plt_start@+0x70>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X1, XZR, X20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
BL 4100a0 <@plt_start@+0x80>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADRP X1, <4205b4>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
MOVZ X2, #17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X1, X1, #408	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ORR X0, XZR, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
BL 4100d0 <@plt_start@+0xb0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X1, [SP, #384]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ORR X0, XZR, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
BL 410090 <@plt_start@+0x70>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X1, XZR, X20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
BL 4100a0 <@plt_start@+0x80>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADRP X1, <4205dc>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
MOVZ X2, #23	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X1, X1, #432	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ORR X0, XZR, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
BL 4100d0 <@plt_start@+0xb0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X1, [SP, #392]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ORR X0, XZR, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
BL 410090 <@plt_start@+0x70>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X1, XZR, X20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
BL 4100a0 <@plt_start@+0x80>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP D14, D15, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (50.0%)
MOVZ W0, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVZ X12, #10400	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
LDP X29, X30, [SP]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
ADD SP, SP, X12,UXTX	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	N/A
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADRP X19, <440624>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADRP X1, <420628>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X19, X19, #464	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
MOVZ X2, #7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X1, X1, #184	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ORR X0, XZR, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
BL 4100d0 <@plt_start@+0xb0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X1, [X21]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ORR X0, XZR, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
BL 4100a0 <@plt_start@+0x80>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADRP X1, <42064c>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X1, X1, #192	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
BL 4100a0 <@plt_start@+0x80>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVZ W0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
B 41160c <main+0x144c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADRP X1, <420660>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADRP X0, <440664>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X1, X1, #224	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X0, X0, #464	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
BL 4100a0 <@plt_start@+0x80>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP D14, D15, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (50.0%)
MOVZ W0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
B 41160c <main+0x144c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X1, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X0, SP, #400	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR X1, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
BL 410080 <@plt_start@+0x60>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X2, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDP X1, X0, [SP, #176]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
STR X2, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
BL 4100c0 <@plt_start@+0xa0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X2, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ORR X0, XZR, X26	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR X2, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X1, [SP, #152]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
BL 4100c0 <@plt_start@+0xa0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X2, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ORR X26, XZR, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
LDR X1, [SP, #152]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ORR X0, XZR, X28	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
BL 4100c0 <@plt_start@+0xa0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X1, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ORR X0, XZR, X21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR X21, XZR, X26	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
BL 4100c0 <@plt_start@+0xa0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X1, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ORR X0, XZR, X22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
BL 4100c0 <@plt_start@+0xa0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X1, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ORR X0, XZR, X27	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
BL 4100c0 <@plt_start@+0xa0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X21, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
B 4116e4 <main+0x1524>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X21, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
B 4116d8 <main+0x1518>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADRP X0, <42075c>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X0, X0, #456	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
BL 410050 <@plt_start@+0x30>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X26, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
B 4116c8 <main+0x1508>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X26, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
B 4116bc <main+0x14fc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X2, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
B 4116a4 <main+0x14e4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X1, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
MOVZ X9, #5400	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X0, SP, X9,UXTX	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	N/A
STR X1, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
BL 4100e0 <@plt_start@+0xc0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X2, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
B 411694 <main+0x14d4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X20, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
B 411724 <main+0x1564>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X20, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
B 411718 <main+0x1558>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X20, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
B 41170c <main+0x154c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X20, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
B 411700 <main+0x1540>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADRP X0, <4207bc>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X0, X0, #456	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
BL 410050 <@plt_start@+0x30>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X20, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
B 411730 <main+0x1570>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADRP X0, <4207d0>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X0, X0, #456	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
BL 410050 <@plt_start@+0x30>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run run_0

Source file and lines	attention_v2.cpp:26-332
Module	attention-gcc-native

The function is defined in:

/usr/include/c++/14/bits/stl_algobase.h:952,1140,1146
/usr/include/c++/14/bits/chrono.h:214,627,716
/usr/include/stdlib.h:363
/usr/include/c++/14/bits/stl_construct.h:109,119
/usr/include/c++/14/bits/stl_uninitialized.h:668
/usr/include/c++/14/cmath:443
/usr/include/c++/14/bits/char_traits.h:350,427
/usr/include/c++/14/bits/basic_string.h:194,223-228,243,269,294,809
/usr/include/c++/14/bits/stl_vector.h:1128-1131,1919-1920
/usr/include/c++/14/bits/random.h:248,1760,1766,1782
/home/eoseret/llm-attention/attention_v2.cpp:26-33,97-100,107-109,129-135,144,160-167,175-178,185,194,204,213,223-226,233-238,245,254,264,273-276,283,292,302-310,317-332
/usr/include/c++/14/bits/new_allocator.h:104,126,151-156,172
/usr/include/c++/14/bits/basic_string.tcc:242
/usr/include/c++/14/bits/random.tcc:326-342,458-466,3367-3374
/usr/include/c++/14/ostream:175,673

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

6% of VPU instructions are used in vector version (process two or more data elements in vector registers):

14% of VPU loads are used in vector version.
14% of VPU stores are used in vector version.
0% of VPU addition or subtraction instructions are used in vector version.
0% of VPU multiply instructions are used in vector version.
0% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

CALL instructions

Detected function call instructions.

Details

@plt_start@: 3 occurrences►
- /usr/include/stdlib.h:363
- /usr/include/stdlib.h:363
- /usr/include/stdlib.h:363
unknown: 50 occurrences►
- /usr/include/c++/14/bits/new_allocator.h:151
- /usr/include/c++/14/bits/random.h:1766
- /usr/include/c++/14/bits/new_allocator.h:172
- /usr/include/c++/14/bits/new_allocator.h:172
- /usr/include/c++/14/bits/new_allocator.h:172
- /usr/include/c++/14/bits/new_allocator.h:172
- /usr/include/c++/14/bits/new_allocator.h:172
- /usr/include/c++/14/bits/new_allocator.h:172
- /usr/include/c++/14/bits/new_allocator.h:172
- /usr/include/c++/14/bits/new_allocator.h:172
- /usr/include/c++/14/bits/new_allocator.h:172
- /usr/include/c++/14/bits/new_allocator.h:172
- /usr/include/c++/14/bits/new_allocator.h:172
- /usr/include/c++/14/bits/new_allocator.h:172
- /usr/include/c++/14/ostream:673
- /usr/include/c++/14/ostream:175
- /home/eoseret/llm-attention/attention_v2.cpp:322
- /usr/include/c++/14/ostream:673
- /usr/include/c++/14/ostream:175
- /home/eoseret/llm-attention/attention_v2.cpp:323
- /usr/include/c++/14/ostream:673
- /usr/include/c++/14/ostream:175
- /home/eoseret/llm-attention/attention_v2.cpp:324
- /usr/include/c++/14/ostream:673
- /usr/include/c++/14/ostream:175
- /home/eoseret/llm-attention/attention_v2.cpp:325
- /usr/include/c++/14/ostream:673
- /usr/include/c++/14/ostream:175
- /home/eoseret/llm-attention/attention_v2.cpp:326
- /usr/include/c++/14/ostream:673
- /usr/include/c++/14/ostream:175
- /home/eoseret/llm-attention/attention_v2.cpp:327
- /usr/include/c++/14/ostream:673
- /usr/include/c++/14/ostream:175
- /home/eoseret/llm-attention/attention_v2.cpp:328
- /usr/include/c++/14/ostream:673
- /home/eoseret/llm-attention/attention_v2.cpp:99
- /home/eoseret/llm-attention/attention_v2.cpp:99
- /home/eoseret/llm-attention/attention_v2.cpp:108
- /usr/include/c++/14/bits/random.h:1766
- /usr/include/c++/14/bits/new_allocator.h:172
- /usr/include/c++/14/bits/new_allocator.h:172
- /usr/include/c++/14/bits/new_allocator.h:172
- /usr/include/c++/14/bits/new_allocator.h:172
- /usr/include/c++/14/bits/new_allocator.h:172
- /usr/include/c++/14/bits/new_allocator.h:172
- /usr/include/c++/14/bits/stl_vector.h:1920
- /usr/include/c++/14/bits/basic_string.h:809
- /usr/include/c++/14/bits/stl_vector.h:1920
- /usr/include/c++/14/bits/stl_vector.h:1920

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 6 bytes. The binary function is storing 18 bytes.

General properties

nb instructions	317
nb uops	308
loop length	1268
used w registers	10
used x registers	21
used b registers	0
used h registers	0
used s registers	2
used d registers	4
used q registers	1
used v registers	1
used z registers	0
nb stack references	73

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	38.50 cycles
front end	38.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	36.50	36.50	51.25	51.25	51.25	51.25	2.50	2.50	1.00	1.00	27.00	27.00	27.00	14.50	14.50
cycles	36.50	36.50	51.25	51.25	51.25	51.25	2.50	2.50	1.00	1.00	27.00	27.00	27.00	14.50	14.50

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	38.50
Dispatch	51.25
Overall L1	51.25

Vectorization ratios

INT

all	6%
load	14%
store	14%
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

INT+FP

all	6%
load	14%
store	14%
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

INT

all	29%
load	34%
store	33%
mul	25%
add-sub	24%
fma	NA (no fma vectorizable/vectorized instructions)
other	27%

all	12%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	12%

INT+FP

all	29%
load	34%
store	33%
mul	25%
add-sub	24%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	27%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 51.25 cycles. At this rate:

0% of peak load performance is reached (0.12 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
0% of peak store performance is reached (0.35 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the function is: 4101c0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput	Vectorization
MOVZ X12, #10400	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
SUB SP, SP, X12,UXTX	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	N/A
STP X29, X30, [SP]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X29, SP, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ORR X21, XZR, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP W0, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.LE 411624 <main+0x1464>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVZ W2, #10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVZ X1, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
STP D14, D15, [SP, #112]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (50.0%)
LDR X0, [X21, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
BL 410040 <@plt_start@+0x20>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X20, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
LDR X0, [X21, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
MOVZ W2, #10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVZ X1, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
STR W20, [SP, #212]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (12.5%)
BL 410040 <@plt_start@+0x20>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
FMOV S14, W0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (12.5%)
ORR X19, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
MOVZ W2, #10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X0, [X21, #24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
MOVZ X1, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
BL 410040 <@plt_start@+0x20>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP W20, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
STR W0, [SP, #304]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (12.5%)
CCMP W19, #0, #4, #12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
B.LE 411660 <main+0x14a0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SBFM X2, X0, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVI V31.4S, #0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (12.5%)
SBFM X1, X19, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (100.0%)
STR XZR, [SP, #392]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
SBFM X6, X20, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (100.0%)
STR X2, [SP, #312]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
UMULL X2, W19, W19	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	N/A
STR X1, [SP, #296]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
UMULL X1, W20, W19	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	scal (25.0%)
STR X2, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
UMULL X2, W20, W20	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	N/A
STR X2, [SP, #216]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ADD X2, SP, #512	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STUR Q31, [X2, #344]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (50.0%)
STUR Q31, [X2, #360]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (50.0%)
STUR Q31, [X2, #376]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (50.0%)
CBZ W0, 4114dc <main+0x131c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVN X0, #57344	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X27, X28, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP D12, D13, [SP, #96]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (50.0%)
CMP X1, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.HI 4117d0 <main+0x1610>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR W5, WZR, W20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
UBFM X0, X1, #62, #61	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR W19, [SP, #200]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (12.5%)
SUB X20, X1, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
UMULL X1, W19, W19	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	scal (25.0%)
UBFM X9, X6, #61, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
MOVZ W7, #12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
UBFM X8, X6, #60, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
STR X0, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR W5, [SP, #240]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (12.5%)
UBFM X1, X1, #62, #61	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
UMULL X7, W6, W7	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	scal (25.0%)
STP X6, X8, [SP, #184]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X1, X9, [SP, #160]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X1, [SP, #216]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
STP X20, X7, [SP, #224]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
UBFM X1, X1, #62, #61	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
STR X1, [SP, #152]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
UBFM X1, X6, #62, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
STR X1, [SP, #176]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
SBFM X1, X19, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (100.0%)
UBFM X1, X1, #62, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
STR X1, [SP, #320]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
SUB W1, W19, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
STR W1, [SP, #308]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (12.5%)
BL 4100b0 <@plt_start@+0x90>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR W4, [SP, #200]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (12.5%)
ORR X19, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
STR WZR, [X0]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (12.5%)
STR XZR, [SP, #200]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X9, [SP, #168]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDP X6, X8, [SP, #184]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDR X7, [SP, #232]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR W5, [SP, #240]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (12.5%)
CBZ X20, 410360 <main+0x1a0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X0, SP, #400	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
BL 410080 <@plt_start@+0x60>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X1, X0, [SP, #176]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
BL 4100c0 <@plt_start@+0xa0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X1, [SP, #152]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ORR X0, XZR, X26	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
BL 4100c0 <@plt_start@+0xa0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X1, [SP, #152]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ORR X0, XZR, X28	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
BL 4100c0 <@plt_start@+0xa0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X26, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ORR X0, XZR, X21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR X1, XZR, X26	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
BL 4100c0 <@plt_start@+0xa0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X1, XZR, X26	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ORR X0, XZR, X22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
BL 4100c0 <@plt_start@+0xa0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X1, XZR, X26	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ORR X0, XZR, X27	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
BL 4100c0 <@plt_start@+0xa0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X1, XZR, X26	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ORR X0, XZR, X20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
BL 4100c0 <@plt_start@+0xa0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X0, [SP, #192]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ORR X1, XZR, X26	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
BL 4100c0 <@plt_start@+0xa0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X21, [SP, #160]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ORR X0, XZR, X24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR X1, XZR, X21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
BL 4100c0 <@plt_start@+0xa0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X0, XZR, X23	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR X1, XZR, X21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
BL 4100c0 <@plt_start@+0xa0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X0, XZR, X25	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR X1, XZR, X21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
BL 4100c0 <@plt_start@+0xa0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X1, XZR, X26	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ORR X0, XZR, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
BL 4100c0 <@plt_start@+0xa0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP D12, D13, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (50.0%)
MOVZ W0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X27, X28, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP D14, D15, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (50.0%)
B 41160c <main+0x144c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP D12, D13, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (50.0%)
LDP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X27, X28, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
ADRP X19, <4404dc>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADRP X1, <4204e0>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X19, X19, #192	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
MOVZ X2, #22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X1, X1, #280	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ORR X0, XZR, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
BL 4100d0 <@plt_start@+0xb0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X1, [SP, #344]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ORR X0, XZR, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADRP X20, <420500>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X20, X20, #304	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
BL 410090 <@plt_start@+0x70>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X1, XZR, X20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
BL 4100a0 <@plt_start@+0x80>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADRP X1, <420514>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
MOVZ X2, #20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X1, X1, #312	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ORR X0, XZR, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
BL 4100d0 <@plt_start@+0xb0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X1, [SP, #352]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ORR X0, XZR, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
BL 410090 <@plt_start@+0x70>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X1, XZR, X20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
BL 4100a0 <@plt_start@+0x80>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADRP X1, <42053c>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
MOVZ X2, #22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X1, X1, #336	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ORR X0, XZR, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
BL 4100d0 <@plt_start@+0xb0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X1, [SP, #360]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ORR X0, XZR, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
BL 410090 <@plt_start@+0x70>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X1, XZR, X20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
BL 4100a0 <@plt_start@+0x80>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADRP X1, <420564>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
MOVZ X2, #19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X1, X1, #360	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ORR X0, XZR, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
BL 4100d0 <@plt_start@+0xb0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X1, [SP, #368]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ORR X0, XZR, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
BL 410090 <@plt_start@+0x70>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X1, XZR, X20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
BL 4100a0 <@plt_start@+0x80>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADRP X1, <42058c>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
MOVZ X2, #20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X1, X1, #384	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ORR X0, XZR, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
BL 4100d0 <@plt_start@+0xb0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X1, [SP, #376]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ORR X0, XZR, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
BL 410090 <@plt_start@+0x70>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X1, XZR, X20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
BL 4100a0 <@plt_start@+0x80>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADRP X1, <4205b4>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
MOVZ X2, #17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X1, X1, #408	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ORR X0, XZR, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
BL 4100d0 <@plt_start@+0xb0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X1, [SP, #384]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ORR X0, XZR, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
BL 410090 <@plt_start@+0x70>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X1, XZR, X20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
BL 4100a0 <@plt_start@+0x80>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADRP X1, <4205dc>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
MOVZ X2, #23	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X1, X1, #432	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ORR X0, XZR, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
BL 4100d0 <@plt_start@+0xb0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X1, [SP, #392]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ORR X0, XZR, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
BL 410090 <@plt_start@+0x70>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X1, XZR, X20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
BL 4100a0 <@plt_start@+0x80>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP D14, D15, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (50.0%)
MOVZ W0, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVZ X12, #10400	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
LDP X29, X30, [SP]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
ADD SP, SP, X12,UXTX	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	N/A
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADRP X19, <440624>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADRP X1, <420628>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X19, X19, #464	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
MOVZ X2, #7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X1, X1, #184	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ORR X0, XZR, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
BL 4100d0 <@plt_start@+0xb0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X1, [X21]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ORR X0, XZR, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
BL 4100a0 <@plt_start@+0x80>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADRP X1, <42064c>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X1, X1, #192	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
BL 4100a0 <@plt_start@+0x80>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVZ W0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
B 41160c <main+0x144c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADRP X1, <420660>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADRP X0, <440664>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X1, X1, #224	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X0, X0, #464	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
BL 4100a0 <@plt_start@+0x80>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP D14, D15, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (50.0%)
MOVZ W0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
B 41160c <main+0x144c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X1, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X0, SP, #400	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR X1, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
BL 410080 <@plt_start@+0x60>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X2, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDP X1, X0, [SP, #176]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
STR X2, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
BL 4100c0 <@plt_start@+0xa0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X2, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ORR X0, XZR, X26	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR X2, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X1, [SP, #152]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
BL 4100c0 <@plt_start@+0xa0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X2, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ORR X26, XZR, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
LDR X1, [SP, #152]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ORR X0, XZR, X28	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
BL 4100c0 <@plt_start@+0xa0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X1, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ORR X0, XZR, X21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR X21, XZR, X26	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
BL 4100c0 <@plt_start@+0xa0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X1, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ORR X0, XZR, X22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
BL 4100c0 <@plt_start@+0xa0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X1, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ORR X0, XZR, X27	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
BL 4100c0 <@plt_start@+0xa0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X21, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
B 4116e4 <main+0x1524>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X21, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
B 4116d8 <main+0x1518>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADRP X0, <42075c>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X0, X0, #456	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
BL 410050 <@plt_start@+0x30>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X26, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
B 4116c8 <main+0x1508>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X26, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
B 4116bc <main+0x14fc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X2, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
B 4116a4 <main+0x14e4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X1, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
MOVZ X9, #5400	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X0, SP, X9,UXTX	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	N/A
STR X1, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
BL 4100e0 <@plt_start@+0xc0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X2, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
B 411694 <main+0x14d4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X20, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
B 411724 <main+0x1564>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X20, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
B 411718 <main+0x1558>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X20, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
B 41170c <main+0x154c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X20, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
B 411700 <main+0x1540>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADRP X0, <4207bc>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X0, X0, #456	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
BL 410050 <@plt_start@+0x30>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X20, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
B 411730 <main+0x1570>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADRP X0, <4207d0>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X0, X0, #456	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
BL 410050 <@plt_start@+0x30>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A

Name	Coverage (%)	Time (s)
▼main–	89.26	9.23
○Loop 0 - new_allocator.h:104-172 - attention-gcc-native	0.00	0.00
▼Loop 20 - stl_algobase.h:952-1146 - attention-gcc-native–	0.00	0.00
▼Loop 21 - stl_algobase.h:952-1146 - attention-gcc-native–	0.00	0.00
○Loop 2 - random.tcc:333-3371 - attention-gcc-native	0.58	0.06
○Loop 24 - random.tcc:458-3374 - attention-gcc-native	0.34	0.04
▼Loop 19 - attention_v2.cpp:26-33 - attention-gcc-native–	0.24	0.03
▼Loop 18 - attention_v2.cpp:26-33 - attention-gcc-native–	0.05	0.00
○Loop 17 - attention_v2.cpp:30-31 - attention-gcc-native	34.69	3.59
▼Loop 16 - attention_v2.cpp:26-233 - attention-gcc-native–	0.15	0.02
▼Loop 15 - attention_v2.cpp:27-233 - attention-gcc-native–	0.44	0.05
○Loop 14 - attention_v2.cpp:30-31 - attention-gcc-native	30.00	3.10
○Loop 1 - random.tcc:333-339 - attention-gcc-native	0.10	0.01
▼Loop 6 - attention_v2.cpp:26-33 - attention-gcc-native–	0.10	0.01
▼Loop 5 - attention_v2.cpp:27-33 - attention-gcc-native–	0.00	0.00
○Loop 4 - attention_v2.cpp:30-31 - attention-gcc-native	7.55	0.78
▼Loop 12 - attention_v2.cpp:26-33 - attention-gcc-native–	0.05	0.00
▼Loop 11 - attention_v2.cpp:26-33 - attention-gcc-native–	0.05	0.00
○Loop 10 - attention_v2.cpp:30-31 - attention-gcc-native	7.01	0.73
▼Loop 9 - attention_v2.cpp:26-33 - attention-gcc-native–	0.05	0.00
▼Loop 8 - attention_v2.cpp:26-33 - attention-gcc-native–	0.19	0.02
○Loop 7 - attention_v2.cpp:30-31 - attention-gcc-native	7.35	0.76
○Loop 3 - random.tcc:459-459 - attention-gcc-native	0.00	0.00
▼Loop 23 - attention_v2.cpp:236-238 - attention-gcc-native–	0.00	0.00
○Loop 22 - attention_v2.cpp:237-238 - attention-gcc-native	0.34	0.04
○Loop 13 - attention_v2.cpp:233-238 - attention-gcc-native	0.00	0.00

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

CALL instructions

Details

Matching between your function (in the source code) and the binary function

General properties

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Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

CALL instructions

Details

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code