A brief introduction to FPGAs

2.5.1. Development boards

1. Digilent Arty Z7
   

   Development boards (or devboards) offer a large range of developer-friendly interfaces and tools for rapid prototyping, testing, debugging and tracing. For example, the Digilent Arty Z7 devboard shown below (Figure 9) offers two HDMI ports (input and output), a USB port, a 1 Gpbs Ethernet port, an audio port, and a large set of GPIO ports alongise an SD card reader (at the back of the board). This board also comes with a dual-core ARM Cortex-A9 CPU running at 650 MHz and tightly integrated to the Xiling FPGA that can be easily programmed/debugged using the micro-USB connector. Being afordable and This board was designed for three markets:

   • Electronics hobbyists: a niche of tech-savvy consumers re-implementing retro-computer architectures (Z80, 6502, …) in order to run retro games on more efficient modern hardware.
   • Video capture and analysis: this board has an input and output HDMI ports
   • Academic institutions:

   

   Figure 9: Digilent Arty Z7 FPGA devboard

2. Terasic Intel Pathfinder
   

   Another interesting devboard is the Terasic Intel Pathfinder for RISC-V designed for promoting RISC-V software and hardware development. This board comes with a Cyclone IV FPGA containing 114,480 Logic Elements, 3,888 Kbits of embedded memory, and 128 MB of SDRAM. It offers a slew of I/O capabilities for embedded systems development: 2 Ethernet ports, 4 USB ports, TV decoder, RS232 port, …

   

   Figure 10: Terasic Intel Pathfinder for RISC-V board

3. Lattice ICEStick
   

   For years, FPGA devices were very expensive and only accessible to those with the financial means to invest in the hardware and the software stack. Nowadays, with the democratisation of electronics, FPGA boards have become more accessible and affordable to the general public. For example, Lattice, an embedded semiconductor and FPGA manufacturer, proposes multiple affordable boards for students, universities, and hobbyists for less than 50$. The board shown below in Figure 11 is the Lattice Icestick HX1K, it costs 48$, is very low-power and comes with 1K LUTs, 5 LEDs, 12 GPIO pins, and an infrared receiver/transmitter.

   

   Figure 11: Lattice Icestick HX1K

   For more devboards, you can visit the following links:

4. Additional ressources
   
   • https://digilent.com/shop/boards-and-components/system-boards/fpga-boards/
   • https://www.xilinx.com/products/boards-and-kits/see-all-evaluation-boards.html
   • https://www.intel.com/content/www/us/en/developer/articles/technical/fpga-academic-boards.html

2.5.2. PCIe cards

3.2.1. Sound processing

3.2.2. Image/Video processing

3.6.1. Memory intensive workloads

3.6.2. Communication intensive workloads

3.6.3. Power/Energy efficiency

4.1.1. HDL languages

module count (input  clk,
              output LED1,
              output LED2,
              output LED3,
              output LED4,
             );

   localparam        BITS = 4; //Counter's bits
   localparam        LOG2DELAY = 16; //Delay

   reg               slowClock = 0; //Slow clock (delayed clock)
   reg [BITS-1:0]    counter = 0;   //4-bit counter   
   reg [BITS-1:0]    outcnt = 0;    //4-bit counter
   reg [BITS+LOG2DELAY-1:0] dcounter = 0; //Delay counter

   //
   always @(posedge clk) 
     begin
        if (!dcounter)
          slowClock <= !slowClock;

        dcounter <= dcounter + 1;
     end

   always @(posedge slowClock)
     begin
        outcnt <= counter;
        counter <= counter + 1;
     end

   assign { LED1, LED2, LED3, LED4 } = outcnt;

endmodule

4.1.2. OpenCL

4.1.3. Python

1. fpyga
   

   fpyga is a Python interface allowing for programming Intel/Altera's DE10 devices without having to write RTL-like code (Verilog, VHDL, …). It has no support for other devices.

   • https://noeloikeau.github.io/fpyga/
2. pyfpga
   

   pyfpga is also a Python interface but it only handles the tooling management. It can handle the recipes for building (synthesis) and verifying projects written in many languages and using multiple proprietary as well as open source synthesis tools.

   • https://pyfpga.github.io/pyfpga/
   • https://github.com/PyFPGA/pyfpga
3. pyRTL
   

   Python-based RTL language. Academic tool!

   • https://ucsbarchlab.github.io/PyRTL/
4. pyMTL
   

   Python-based hardware modeling language from Cornell University:

   • (deprecated version) https://github.com/cornell-brg/pymtl
   • https://github.com/pymtl/pymtl3
5. MyHDL
   

   This Python module can generate Verilog and VHDL code from Python based designs.

   • https://en.wikipedia.org/wiki/MyHDL

4.1.4. Verilog example of a Floating-Point unit

1. IEEE754 adder
   

   module FloatingAddition #(parameter XLEN=32)
      (
       input [XLEN-1:0]      A,
       input [XLEN-1:0]      B,
       input                 clk,
       output                overflow,
       output                underflow,
       output                exception,
       output reg [XLEN-1:0] result);
   
      reg [23:0]                                   A_Mantissa, B_Mantissa;
      reg [23:0]                                   Temp_Mantissa;
      reg [22:0]                                   Mantissa;
      reg [7:0]                                    Exponent;
      reg                                          Sign;
      wire                                         MSB;
      reg [7:0]                                    A_Exponent, B_Exponent, Temp_Exponent, diff_Exponent;
      reg                                          A_sign, B_sign, Temp_sign;
      reg [32:0]                                   Temp;
      reg                                          carry;
      reg [2:0]                                    one_hot;
      reg                                          comp;
      reg [7:0]                                    exp_adjust;
   
      always @ (*)
        begin
   
           comp =  (A[30:23] >= B[30:23])? 1'b1 : 1'b0;
   
           A_Mantissa = comp ? {1'b1, A[22:0]} : {1'b1, B[22:0]};
           A_Exponent = comp ? A[30:23] : B[30:23];
           A_sign = comp ? A[31] : B[31];
   
           B_Mantissa = comp ? {1'b1, B[22:0]} : {1'b1, A[22:0]};
           B_Exponent = comp ? B[30:23] : A[30:23];
           B_sign = comp ? B[31] : A[31];
   
           diff_Exponent = A_Exponent-B_Exponent;
           B_Mantissa = (B_Mantissa >> diff_Exponent);
           {carry,Temp_Mantissa} = (A_sign ~^ B_sign) ? A_Mantissa + B_Mantissa : A_Mantissa-B_Mantissa; 
           exp_adjust = A_Exponent;
   
           if (carry)
             begin
                Temp_Mantissa = Temp_Mantissa >> 1;
                exp_adjust = exp_adjust + 1'b1;
             end
           else
             begin
                while(!Temp_Mantissa[23])
                  begin
                     Temp_Mantissa = Temp_Mantissa << 1;
                     exp_adjust = exp_adjust - 1'b1;
                  end
             end
   
           Sign = A_sign;
           Mantissa = Temp_Mantissa[22:0];
           Exponent = exp_adjust;
           result = { Sign, Exponent, Mantissa };
        end
   
   endmodule
   
   

2. IEEE754 multiplier
   

   module FloatingMultiplication #(parameter XLEN=32)
      (
       input [XLEN-1:0]      A,
       input [XLEN-1:0]      B,
       input                 clk,
       output                overflow,
       output                underflow,
       output                exception,
       output reg [XLEN-1:0] result);
   
      reg [23:0]             A_Mantissa, B_Mantissa;
      reg [22:0]             Mantissa;
      reg [47:0]             Temp_Mantissa;
      reg [7:0]              A_Exponent, B_Exponent, Temp_Exponent, diff_Exponent, Exponent;
      reg                    A_sign, B_sign, Sign;
      reg [32:0]             Temp;
      reg [6:0]              exp_adjust;
   
     always @(*)
        begin
           A_Mantissa = {1'b1, A[22:0]};
           A_Exponent = A[30:23];
           A_sign = A[31];
   
           B_Mantissa = {1'b1, B[22:0]};
           B_Exponent = B[30:23];
           B_sign = B[31];
   
           Temp_Exponent = A_Exponent + B_Exponent - 127;
           Temp_Mantissa = A_Mantissa * B_Mantissa;
           Mantissa = Temp_Mantissa[47] ? Temp_Mantissa[46:24] : Temp_Mantissa[45:23];
           Exponent = Temp_Mantissa[47] ? Temp_Exponent + 1'b1 : Temp_Exponent;
           Sign = A_sign ^ B_sign;
           result = {Sign, Exponent, Mantissa};
        end
   
   endmodule
   
   

3. IEEE754 divider
   

   module FloatingDivision #(parameter XLEN=32)
      (
       input [XLEN-1:0]  A,
       input [XLEN-1:0]  B,
       input             clk,
       output            overflow,
       output            underflow,
       output            exception,
       output [XLEN-1:0] result);
   
      reg [23:0]         A_Mantissa, B_Mantissa;
      reg [22:0]         Mantissa;
      wire [7:0]         exp;
      reg [23:0]         Temp_Mantissa;
      reg [7:0]          A_Exponent, B_Exponent, Temp_Exponent, diff_Exponent;
      wire [7:0]         Exponent;
      reg [7:0]          A_adjust, B_adjust;
      reg                A_sign, B_sign, Sign;
      reg [32:0]         Temp;
      wire [31:0]        temp1, temp2, temp3, temp4, temp5, temp6, temp7, debug;
      wire [31:0]        reciprocal;
      wire [31:0]        x0, x1, x2, x3;
      reg [6:0]          exp_adjust;
      reg [XLEN-1:0]     B_scaled; 
      reg                en1, en2, en3, en4, en5;
      reg                dummy;
   
      /*----Initial value----*/
      FloatingMultiplication M1(.A({{1'b0,8'd126,B[22:0]}}), .B(32'h3ff0f0f1), .clk(clk), .result(temp1)); //verified
      assign debug = {1'b1, temp1[30:0]};
      FloatingAddition A1(.A(32'h4034b4b5), .B({1'b1,temp1[30:0]}), .result(x0));
   
      /*----First Iteration----*/
      FloatingMultiplication M2(.A({{1'b0, 8'd126,B[22:0]}}), .B(x0), .clk(clk), .result(temp2));
      FloatingAddition A2(.A(32'h40000000), .B({!temp2[31], temp2[30:0]}), .result(temp3));
      FloatingMultiplication M3(.A(x0), .B(temp3), .clk(clk), .result(x1));
   
      /*----Second Iteration----*/
      FloatingMultiplication M4(.A({1'b0,8'd126,B[22:0]}), .B(x1), .clk(clk), .result(temp4));
      FloatingAddition A3(.A(32'h40000000),.B({!temp4[31], temp4[30:0]}), .result(temp5));
      FloatingMultiplication M5(.A(x1), .B(temp5), .clk(clk), .result(x2));
   
      /*----Third Iteration----*/
      FloatingMultiplication M6(.A({1'b0,8'd126,B[22:0]}), .B(x2), .clk(clk), .result(temp6));
      FloatingAddition A4(.A(32'h40000000), .B({!temp6[31],temp6[30:0]}), .result(temp7));
      FloatingMultiplication M7(.A(x2), .B(temp7),.clk(clk),.result(x3));
   
      /*----Reciprocal : 1/B----*/
      assign Exponent = x3[30:23] + 8'd126 - B[30:23];
      assign reciprocal = {B[31], Exponent, x3[22:0]};
   
      /*----Multiplication A*1/B----*/
      FloatingMultiplication M8(.A(A), .B(reciprocal), .clk(clk), .result(result));
   
   endmodule
   
   

4. IEEE754 square root
   

   module FloatingSqrt #(parameter XLEN=32)
      (
       input [XLEN-1:0]  A,
       input             clk,
       output            overflow,
       output            underflow,
       output            exception,
       output [XLEN-1:0] result);
   
      wire [7:0]         Exponent;
      wire [22:0]        Mantissa;
      wire               Sign;
      wire [XLEN-1:0]    temp1, temp2, temp3, temp4, temp5, temp6, temp7, temp8, temp;
      wire [XLEN-1:0]    x0, x1, x2, x3;
      wire [XLEN-1:0]    sqrt_1by05, sqrt_2, sqrt_1by2;
      wire [7:0]         Exp_2, Exp_Adjust;
      wire               remainder;
      wire               pos;
   
      assign x0 = 32'h3f5a827a;
      assign sqrt_1by05 = 32'h3fb504f3;  // 1/sqrt(0.5)
      assign sqrt_2 = 32'h3fb504f3;
      assign sqrt_1by2 = 32'h3f3504f3;
      assign Sign = A[31];
      assign Exponent = A[30:23];
      assign Mantissa = A[22:0];
   
      /*----First Iteration----*/
      FloatingDivision D1(.A({1'b0, 8'd126, Mantissa}), .B(x0), .result(temp1));
      FloatingAddition A1(.A(temp1), .B(x0), .result(temp2));
      assign x1 = {temp2[31], temp2[30:23] - 1, temp2[22:0]};
   
      /*----Second Iteration----*/
      FloatingDivision D2(.A({1'b0, 8'd126, Mantissa}), .B(x1), .result(temp3));
      FloatingAddition A2(.A(temp3), .B(x1), .result(temp4));
      assign x2 = {temp4[31], temp4[30:23] - 1, temp4[22:0]};
   
      /*----Third Iteration----*/
      FloatingDivision D3(.A({1'b0,8'd126, Mantissa}), .B(x2), .result(temp5));
      FloatingAddition A3(.A(temp5), .B(x2), .result(temp6));
      assign x3 = {temp6[31], temp6[30:23] - 1, temp6[22:0]};
      FloatingMultiplication M1(.A(x3), .B(sqrt_1by05), .result(temp7));
   
      assign pos = (Exponent>=8'd127) ? 1'b1 : 1'b0;
      assign Exp_2 = pos ? (Exponent-8'd127) / 2 : (Exponent - 8'd127 - 1) / 2 ;
      assign remainder = (Exponent - 8'd127) % 2;
      assign temp = {temp7[31], Exp_2 + temp7[30:23], temp7[22:0]};
      FloatingMultiplication M2(.A(temp), .B(sqrt_2), .result(temp8));
      assign result = remainder ? temp8 : temp;
   
   endmodule
   
   

4.1.5. RISC-V cores

4.2.1. Vendor tools

4.2.2. Open Source FPGA centered projects

1. FloPoCo
   
   • https://www.flopoco.org/
2. ForwardCom
   
   • https://www.forwardcom.info/
   • https://www.agner.org/optimize/instructionset.pdf
   • https://raw.githubusercontent.com/ForwardCom/manual/master/forwardcom.pdf